f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an import... more f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an important subject for the design of analog/RF integrated circuits in scaled CMOS technology. In this paper, we report on the behavior of low frequency noise, including experimental characterization and compact modeling for NMOS and PMOS devices in 180nm CMOS technology. Aspects of bias dependence and scaling are examined. The compact model approach is based on the charge-based model, including carrier number fluctuation, mobility fluctuation and resistance fluctuation noise mechanisms. The low frequency noise model is related closely to the underlying charge-based model, and accounts for second-order effects such as mobility effects, velocity saturation and channel-length modulation effects. As a result, 1/f noise bias dependence and scaling is covered over a wide range of geometry and bias, ranging from long-to short-channel and weak to strong inversion conditions. Input referred noise shows ...
ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate... more ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate doping on the threshold voltage of MOS transistors. The new model is validated using 2D device simulations and measurements of a CMOS low-voltage process. A simple associated characterization method is also presented. The parameters related to the non-uniform doping are extracted from the pinch-off vs gate voltage characteristic, measured at constant current from a device biased in moderate inversion. (C) 1997 Elsevier Science Ltd.
... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is sho... more ... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is shown in Figure 6. The three voltage controlled current sources (VCCS) are defined as, Im = Ym · (V (gi) − V (bi)) Ims = Yms · (V (si) − V (bi)) (23) Imd = Ymd · (V (di) − V (bi)) ... gi si bi NQS ...
ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance ... more ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.
1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, ... more 1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, 73100 Chania, Greece 3 FPL, Semiconductor Physics Institute, 01108 Vilnius, Lithuania 4 Technical University of Dresden, 01069 Dresden, Germany 5 ECE Department, ...
International Journal of RF and Microwave Computer-Aided Engineering, 2008
ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the de... more ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The ...
A method of interpreting MOSFET behavior is described which is more coherent for modern analog CM... more A method of interpreting MOSFET behavior is described which is more coherent for modern analog CMOS circuit design. This method supercedes the use of simple but antiquated equations in design, and replaces them with an approach based on the inversion coefficient of the individual transistors in the design. Measurements and modeling confirm that this method can be used directly to arbitrate among the various countervailing requirements of demanding analog designs.
The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial comm... more The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.
f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an import... more f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an important subject for the design of analog/RF integrated circuits in scaled CMOS technology. In this paper, we report on the behavior of low frequency noise, including experimental characterization and compact modeling for NMOS and PMOS devices in 180nm CMOS technology. Aspects of bias dependence and scaling are examined. The compact model approach is based on the charge-based model, including carrier number fluctuation, mobility fluctuation and resistance fluctuation noise mechanisms. The low frequency noise model is related closely to the underlying charge-based model, and accounts for second-order effects such as mobility effects, velocity saturation and channel-length modulation effects. As a result, 1/f noise bias dependence and scaling is covered over a wide range of geometry and bias, ranging from long-to short-channel and weak to strong inversion conditions. Input referred noise shows ...
ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate... more ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate doping on the threshold voltage of MOS transistors. The new model is validated using 2D device simulations and measurements of a CMOS low-voltage process. A simple associated characterization method is also presented. The parameters related to the non-uniform doping are extracted from the pinch-off vs gate voltage characteristic, measured at constant current from a device biased in moderate inversion. (C) 1997 Elsevier Science Ltd.
... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is sho... more ... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is shown in Figure 6. The three voltage controlled current sources (VCCS) are defined as, Im = Ym · (V (gi) − V (bi)) Ims = Yms · (V (si) − V (bi)) (23) Imd = Ymd · (V (di) − V (bi)) ... gi si bi NQS ...
ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance ... more ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.
1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, ... more 1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, 73100 Chania, Greece 3 FPL, Semiconductor Physics Institute, 01108 Vilnius, Lithuania 4 Technical University of Dresden, 01069 Dresden, Germany 5 ECE Department, ...
International Journal of RF and Microwave Computer-Aided Engineering, 2008
ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the de... more ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The ...
A method of interpreting MOSFET behavior is described which is more coherent for modern analog CM... more A method of interpreting MOSFET behavior is described which is more coherent for modern analog CMOS circuit design. This method supercedes the use of simple but antiquated equations in design, and replaces them with an approach based on the inversion coefficient of the individual transistors in the design. Measurements and modeling confirm that this method can be used directly to arbitrate among the various countervailing requirements of demanding analog designs.
The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial comm... more The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.
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