IEIE Transactions on Smart Processing & Computing
In this paper, hardware acceleration using a field programmable gate array is proposed to provide... more In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
2017 International Conference on Field Programmable Technology (ICFPT)
Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to im... more Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to implement high-performance and low-power-consumption cloud capability. However, building or utilizing an FPGA-enabled cloud is still challenging due to the lack of fundamental tools. In our previous work, we proposed an hCODE base system for managing portable accelerator IPs on different hardware. In this paper, we extend the previous work and introduce the hCODE 2.0, which is an open-source toolkit for building efficient FPGA-enabled clouds. First, we provide a fundamental toolkit to simplify HW project management and FPGA management at a cluster scale. Second, we implement on-chip resource virtualization and accelerator scheduling capabilities to show possibilities of improving FPGA utilization efficiency with our tools.
Complex Event Processing (CEP) on data streaming are important for fast data access and big data ... more Complex Event Processing (CEP) on data streaming are important for fast data access and big data processing. From previous research, Field-Programmable Gate Arrays (FPGA) introduced in order to process real time continuous data stream in CEP. In this paper, Hardware CEP Framework is proposed to provide a low development costs, high energy efficiency (low power consumption) and good performance application. Based on our simulation, the results show that our low-cost ARM+FPGA based CEP achieve high productivity however currently still achieving lower performance compared to software based CEP running on Zynqberry ARM and Core i7 CPU.
the Institute of Electronics, Information and Communication Engineers (IEICE), 2018
Complex Event Processing (CEP) on data streaming are important for fast data access and big data ... more Complex Event Processing (CEP) on data streaming are important for fast data access and big data processing. From previous research, Field-Programmable Gate Arrays (FPGA) introduced in order to process real time continuous data stream in CEP. In this paper, Hardware CEP Framework is proposed to provide a low development costs, high energy efficiency (low power consumption) and good performance application. Based on our simulation, the results show that our low-cost ARM+FPGA based CEP achieve high productivity however currently still achieving lower performance compared to software based CEP running on Zynqberry ARM and Core i7 CPU.
2017 International Conference on Field Programmable Technology (ICFPT), 2017
Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to im... more Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to implement high-performance and low-power-consumption cloud capability. However, building or utilizing an FPGA-enabled cloud is still challenging due to the lack of fundamental tools. In our previous work, we proposed an hCODE base system for managing portable accelerator IPs on different hardware. In this paper, we extend the previous work and introduce the hCODE 2.0, which is an open-source toolkit for building efficient FPGA-enabled clouds. First, we provide a fundamental toolkit to simplify HW project management and FPGA management at a cluster scale. Second, we implement on-chip resource virtualization and accelerator scheduling capabilities to show possibilities of improving FPGA utilization efficiency with our tools.
IEIE Transactions on Smart Processing and Computing, 2017
In this paper, hardware acceleration using a field programmable gate array is proposed to provide... more In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
—In recent years, Stream processing is becoming an emerging concept and applications for processi... more —In recent years, Stream processing is becoming an emerging concept and applications for processing flow of streaming data to detect relevant information and providing necessary data for further steps. From previous research, Field-Programmable Gate Arrays (FPGA) are introduced in order to process real time continuous data stream. However, developers need months or years to develop FPGA which make development cost of FPGA very high. On the other hands, FPGA itself is offering high performance processing with high throughput, low latency, offering parallelism for scalability and low energy resources. In this paper, we try to simplify hardware accelerator development and how it can be implemented at low costs with high performance. Finally, we combine this approach with the heterogeneous Computing Oriented Development Environment (hCODE) Framework for easy Hardware and Software Integration. Experimental results show that the implemented hardware acceleration is faster than software implementation of regular expression for different sizes of data stream at low cost.
IEIE Transactions on Smart Processing & Computing
In this paper, hardware acceleration using a field programmable gate array is proposed to provide... more In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
2017 International Conference on Field Programmable Technology (ICFPT)
Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to im... more Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to implement high-performance and low-power-consumption cloud capability. However, building or utilizing an FPGA-enabled cloud is still challenging due to the lack of fundamental tools. In our previous work, we proposed an hCODE base system for managing portable accelerator IPs on different hardware. In this paper, we extend the previous work and introduce the hCODE 2.0, which is an open-source toolkit for building efficient FPGA-enabled clouds. First, we provide a fundamental toolkit to simplify HW project management and FPGA management at a cluster scale. Second, we implement on-chip resource virtualization and accelerator scheduling capabilities to show possibilities of improving FPGA utilization efficiency with our tools.
Complex Event Processing (CEP) on data streaming are important for fast data access and big data ... more Complex Event Processing (CEP) on data streaming are important for fast data access and big data processing. From previous research, Field-Programmable Gate Arrays (FPGA) introduced in order to process real time continuous data stream in CEP. In this paper, Hardware CEP Framework is proposed to provide a low development costs, high energy efficiency (low power consumption) and good performance application. Based on our simulation, the results show that our low-cost ARM+FPGA based CEP achieve high productivity however currently still achieving lower performance compared to software based CEP running on Zynqberry ARM and Core i7 CPU.
the Institute of Electronics, Information and Communication Engineers (IEICE), 2018
Complex Event Processing (CEP) on data streaming are important for fast data access and big data ... more Complex Event Processing (CEP) on data streaming are important for fast data access and big data processing. From previous research, Field-Programmable Gate Arrays (FPGA) introduced in order to process real time continuous data stream in CEP. In this paper, Hardware CEP Framework is proposed to provide a low development costs, high energy efficiency (low power consumption) and good performance application. Based on our simulation, the results show that our low-cost ARM+FPGA based CEP achieve high productivity however currently still achieving lower performance compared to software based CEP running on Zynqberry ARM and Core i7 CPU.
2017 International Conference on Field Programmable Technology (ICFPT), 2017
Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to im... more Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to implement high-performance and low-power-consumption cloud capability. However, building or utilizing an FPGA-enabled cloud is still challenging due to the lack of fundamental tools. In our previous work, we proposed an hCODE base system for managing portable accelerator IPs on different hardware. In this paper, we extend the previous work and introduce the hCODE 2.0, which is an open-source toolkit for building efficient FPGA-enabled clouds. First, we provide a fundamental toolkit to simplify HW project management and FPGA management at a cluster scale. Second, we implement on-chip resource virtualization and accelerator scheduling capabilities to show possibilities of improving FPGA utilization efficiency with our tools.
IEIE Transactions on Smart Processing and Computing, 2017
In this paper, hardware acceleration using a field programmable gate array is proposed to provide... more In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
—In recent years, Stream processing is becoming an emerging concept and applications for processi... more —In recent years, Stream processing is becoming an emerging concept and applications for processing flow of streaming data to detect relevant information and providing necessary data for further steps. From previous research, Field-Programmable Gate Arrays (FPGA) are introduced in order to process real time continuous data stream. However, developers need months or years to develop FPGA which make development cost of FPGA very high. On the other hands, FPGA itself is offering high performance processing with high throughput, low latency, offering parallelism for scalability and low energy resources. In this paper, we try to simplify hardware accelerator development and how it can be implemented at low costs with high performance. Finally, we combine this approach with the heterogeneous Computing Oriented Development Environment (hCODE) Framework for easy Hardware and Software Integration. Experimental results show that the implemented hardware acceleration is faster than software implementation of regular expression for different sizes of data stream at low cost.
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Papers by Radhen Hendarmawan