1. Abstract The integration of multimedia adaptive wireless networking capabilities in a PC-noteb... more 1. Abstract The integration of multimedia adaptive wireless networking capabilities in a PC-notebook platform are investigated. To sup-port mobile networking, while providing compatibility with the wired infrastructure, new functions are required for topology cre-ation using multihop ...
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 1996
A testbed has been constructed to evaluate node architectures that support multimedia application... more A testbed has been constructed to evaluate node architectures that support multimedia applications and services across a wireless network. Using this testbed, a low bitrate subband video compression algorithm has been prototyped in a field programmable gate array (FPGA) and evaluated for video networking across bandwidth-limited RF channels. A radio interface has been prototyped in an FPGA and a common applications programming interface (API) has been developed to allow experimentation with multiple radios. This testbed has been used to evaluate node performance under two different wireless applications: 1) simultaneous video and data networking (VTALK) and 2) TCP/IP utilities such as FTP and telnet. Based on this evaluation, the design of a battery-operated high throughput wireless multimedia node is presented.
IEEE Transactions on Acoustics, Speech, and Signal Processing, 1988
A multiprocessor architecture is presented that is suited for the customized and automated VLSI r... more A multiprocessor architecture is presented that is suited for the customized and automated VLSI realization of complex low-to-medium-speed digital signal processing applications. The proposed architecture is constructed from a set of flexible and parameterizable data paths, a selection of powerful control units (for decision-making tasks), and a number of protocols for fast interprocessor communication. The flexible nature of this system
Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is desc... more Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described
The authors describe automatic architecture and floorplan generation techniques for integrated ci... more The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz
Page 1. 1494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 6, DECEMBER 1990 A 100-MHz 64-Tap... more Page 1. 1494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 6, DECEMBER 1990 A 100-MHz 64-Tap FIR Digital Filter in 0.8-pm BiCMOS Gate Array Abstract -A 64-tap FIR digital filter has been designed using ...
A functional compiler system for the implementation of high-speed finite impulse-response (FIR) d... more A functional compiler system for the implementation of high-speed finite impulse-response (FIR) digital filters on gate-array ICs is presented. The system is capable of implementing complex digital filters directly from frequency-domain specifications. Fast turnaround and sample rates in excess of 100 MHz are achieved by using a combination of architectural optimization and advanced 0.8-μm BiCMOS gate-array technology. A 64-tap FIR digital filter synthesized using this new functional compiler system is presented. It has been fabricated and tested fully functional at a sample frequency of 100 MHz
1. Abstract The integration of multimedia adaptive wireless networking capabilities in a PC-noteb... more 1. Abstract The integration of multimedia adaptive wireless networking capabilities in a PC-notebook platform are investigated. To sup-port mobile networking, while providing compatibility with the wired infrastructure, new functions are required for topology cre-ation using multihop ...
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 1996
A testbed has been constructed to evaluate node architectures that support multimedia application... more A testbed has been constructed to evaluate node architectures that support multimedia applications and services across a wireless network. Using this testbed, a low bitrate subband video compression algorithm has been prototyped in a field programmable gate array (FPGA) and evaluated for video networking across bandwidth-limited RF channels. A radio interface has been prototyped in an FPGA and a common applications programming interface (API) has been developed to allow experimentation with multiple radios. This testbed has been used to evaluate node performance under two different wireless applications: 1) simultaneous video and data networking (VTALK) and 2) TCP/IP utilities such as FTP and telnet. Based on this evaluation, the design of a battery-operated high throughput wireless multimedia node is presented.
IEEE Transactions on Acoustics, Speech, and Signal Processing, 1988
A multiprocessor architecture is presented that is suited for the customized and automated VLSI r... more A multiprocessor architecture is presented that is suited for the customized and automated VLSI realization of complex low-to-medium-speed digital signal processing applications. The proposed architecture is constructed from a set of flexible and parameterizable data paths, a selection of powerful control units (for decision-making tasks), and a number of protocols for fast interprocessor communication. The flexible nature of this system
Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is desc... more Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described
The authors describe automatic architecture and floorplan generation techniques for integrated ci... more The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz
Page 1. 1494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 6, DECEMBER 1990 A 100-MHz 64-Tap... more Page 1. 1494 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 6, DECEMBER 1990 A 100-MHz 64-Tap FIR Digital Filter in 0.8-pm BiCMOS Gate Array Abstract -A 64-tap FIR digital filter has been designed using ...
A functional compiler system for the implementation of high-speed finite impulse-response (FIR) d... more A functional compiler system for the implementation of high-speed finite impulse-response (FIR) digital filters on gate-array ICs is presented. The system is capable of implementing complex digital filters directly from frequency-domain specifications. Fast turnaround and sample rates in excess of 100 MHz are achieved by using a combination of architectural optimization and advanced 0.8-μm BiCMOS gate-array technology. A 64-tap FIR digital filter synthesized using this new functional compiler system is presented. It has been fabricated and tested fully functional at a sample frequency of 100 MHz
Uploads
Papers by Rajeev Jain