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Jean-Didier Legat

UCLouvain (University of Louvain), ICTEAM, Faculty Member

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Papers by Jean-Didier Legat

A VLSI coprocessor for binary image processing and features extraction

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas

Modeling the impact of bitstreams transfer in dynamically reconfigurable platforms

AGADDIS : Authentication and Geometrical Attacks Detection for Digital Image Signature

Avertissement en matière de Droits d'auteurLe matériel présenté ci-dessous sert à assurer la... more

MOBILE Digital Circuits based on Negative-Differential-Resistance MOS Structures

Conference on Design of Circuits and Integrated Systems, 2006

Enabling certification for dynamic partial reconfiguration using a minimal flow

Design, Automation, and Test in Europe, Apr 16, 2007

Optimum Weighted Signal-Adapted Biorthogonal Wavelet Transform for Multiresolution Image Coding

Picture Coding Symposium, 1993

Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses

Green SoCs for a sustainable Internet-of-Things

RASH: RAdon soft hash algorithm

European Signal Processing Conference, Sep 1, 2002

Hardware Virtualization in FPGA for Software Defined Radion

Design techniques for reliable timing closure in ULV SoCs

Please be patient while the object screen loads. Change Site View : Select a site UCL FUNDP FUSL... more

A New Active Skeletal Model for Shape Description

Generation and Parallelization of Multibody System Equations of Motion by a Symbolic Approach

An associative processor architecture for pattern recognition

Using Dynamic Reconfiguration of FPGA for telecommunication applications

A Reconfigurable System for Intelligent Processing At Communication Terminal

PLL Jitter Behavioral Modeling and Simulation using HDL-A

Design of a processor dedicated to AC motor control in a multiprocessor structure

Comparative study of a synchronous motor current control loop stability, implanted on mono and multiprocessor architectures

Classically, the control algorithms of high performance motor control systems using PMSM synchron... more Classically, the control algorithms of high performance motor control systems using PMSM synchronous actuators are today implemented on DSP's. In previous papers, we have presented a multiprocessor architecture for such applications. The aim of this paper is to investigate how moving from a single processor to a multiprocessor architecture influences the stability of the motor current control loop. It is shown that, with a multi-processor architecture, higher loop gain can be used and that the damping of the response is much better.

A VLSI coprocessor for binary image processing and features extraction

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas

Modeling the impact of bitstreams transfer in dynamically reconfigurable platforms

AGADDIS : Authentication and Geometrical Attacks Detection for Digital Image Signature

Avertissement en matière de Droits d'auteurLe matériel présenté ci-dessous sert à assurer la... more

MOBILE Digital Circuits based on Negative-Differential-Resistance MOS Structures

Conference on Design of Circuits and Integrated Systems, 2006

Enabling certification for dynamic partial reconfiguration using a minimal flow

Design, Automation, and Test in Europe, Apr 16, 2007

Optimum Weighted Signal-Adapted Biorthogonal Wavelet Transform for Multiresolution Image Coding

Picture Coding Symposium, 1993

Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses

Green SoCs for a sustainable Internet-of-Things

RASH: RAdon soft hash algorithm

European Signal Processing Conference, Sep 1, 2002

Hardware Virtualization in FPGA for Software Defined Radion

Design techniques for reliable timing closure in ULV SoCs

Please be patient while the object screen loads. Change Site View : Select a site UCL FUNDP FUSL... more

A New Active Skeletal Model for Shape Description

Generation and Parallelization of Multibody System Equations of Motion by a Symbolic Approach

An associative processor architecture for pattern recognition

Using Dynamic Reconfiguration of FPGA for telecommunication applications

A Reconfigurable System for Intelligent Processing At Communication Terminal

PLL Jitter Behavioral Modeling and Simulation using HDL-A

Design of a processor dedicated to AC motor control in a multiprocessor structure

Comparative study of a synchronous motor current control loop stability, implanted on mono and multiprocessor architectures

Classically, the control algorithms of high performance motor control systems using PMSM synchron... more Classically, the control algorithms of high performance motor control systems using PMSM synchronous actuators are today implemented on DSP's. In previous papers, we have presented a multiprocessor architecture for such applications. The aim of this paper is to investigate how moving from a single processor to a multiprocessor architecture influences the stability of the motor current control loop. It is shown that, with a multi-processor architecture, higher loop gain can be used and that the damping of the response is much better.