This deliverable reports our early energy models for data structures and algorithms based on both... more This deliverable reports our early energy models for data structures and algorithms based on both micro-benchmarks and concurrent algorithms. It reports the early results of Task 2.1 on investigating and modeling the trade-off between energy and performance in concurrent data structures and algorithms, which forms the basis for the whole work package 2 (WP2). The work has been conducted on the two main EXCESS platforms: (1) Intel platform with recent Intel multi-core CPUs and (2) Movidius embedded platform.
This deliverable reports the results of the power models, energy models and libraries for energy-... more This deliverable reports the results of the power models, energy models and libraries for energy-efficient concurrent data structures and algorithms as available by project month 30 of Work Package 2 (WP2). It reports i) the latest results of Task 2.2-2.4 on providing programming abstractions and libraries for developing energy-efficient data structures and algorithms and ii) the improved results of Task 2.1 on investigating and modeling the trade-off between energy and performance of concurrent data structures and algorithms. The work has been conducted on two main EXCESS platforms: Intel platforms with recent Intel multicore CPUs and Movidius Myriad platforms.
2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016
Ultra-low power (ULP) embedded systems have become popular in the scientific community and indust... more Ultra-low power (ULP) embedded systems have become popular in the scientific community and industry, especially in media and wearable computing. In order to model ULP systems where energy per instruction can be as low as few pJ, more accurate fine-grained approaches are needed. However, there are no application-general, fine-grained and validated models yet that provide insights into how an application running on an ULP embedded system consumes energy and, particularly, whether the race-to-halt (RTH) strategy that are widely used in high-performance computing (HPC) systems is still applicable to ULP embedded systems. In this study, we propose new RTHpower models which provide insights into how an application consumes energy when running on an ULP embedded system. The models are trained and validated with data from 22 microbenchmarks. The experimental results show that RTH is not always applicable to ULP embedded systems, due to their low static power. RTHpower models support predicting when and when not to use RTH for a given application.
This deliverable reports the results of white-box methodologies and early results of the first pr... more This deliverable reports the results of white-box methodologies and early results of the first prototype of libraries and programming abstractions as available by project month 18 by Work Package 2 (WP2). It reports i) the latest results of Task 2.2 on white-box methodologies, programming abstractions and libraries for developing energy-efficient data structures and algorithms and ii) the improved results of Task 2.1 on investigating and modeling the trade-off between energy and performance of concurrent data structures and algorithms. The work has been conducted on two main EXCESS platforms: Intel platforms with recent Intel multicore CPUs and Movidius Myriad1 platform. Regarding white-box methodologies, we have devised new relaxed cache-oblivious models and proposed a new power model for Myriad1 platform and an energy model for lock-free queues on CPU platforms. For Myriad1 platform, the im- proved model now considers both computation and data movement cost as well as architecture...
This deliverable reports our early energy models for data structures and algorithms based on both... more This deliverable reports our early energy models for data structures and algorithms based on both micro-benchmarks and concurrent algorithms. It reports the early results of Task 2.1 on investigating and modeling the trade-off between energy and performance in concurrent data structures and algorithms, which forms the basis for the whole work package 2 (WP2). The work has been conducted on the two main EXCESS platforms: (1) Intel platform with recent Intel multi-core CPUs and (2) Movidius embedded platform.
This deliverable reports the results of the power models, energy models and libraries for energy-... more This deliverable reports the results of the power models, energy models and libraries for energy-efficient concurrent data structures and algorithms as available by project month 30 of Work Package 2 (WP2). It reports i) the latest results of Task 2.2-2.4 on providing programming abstractions and libraries for developing energy-efficient data structures and algorithms and ii) the improved results of Task 2.1 on investigating and modeling the trade-off between energy and performance of concurrent data structures and algorithms. The work has been conducted on two main EXCESS platforms: Intel platforms with recent Intel multicore CPUs and Movidius Myriad platforms.
2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016
Ultra-low power (ULP) embedded systems have become popular in the scientific community and indust... more Ultra-low power (ULP) embedded systems have become popular in the scientific community and industry, especially in media and wearable computing. In order to model ULP systems where energy per instruction can be as low as few pJ, more accurate fine-grained approaches are needed. However, there are no application-general, fine-grained and validated models yet that provide insights into how an application running on an ULP embedded system consumes energy and, particularly, whether the race-to-halt (RTH) strategy that are widely used in high-performance computing (HPC) systems is still applicable to ULP embedded systems. In this study, we propose new RTHpower models which provide insights into how an application consumes energy when running on an ULP embedded system. The models are trained and validated with data from 22 microbenchmarks. The experimental results show that RTH is not always applicable to ULP embedded systems, due to their low static power. RTHpower models support predicting when and when not to use RTH for a given application.
This deliverable reports the results of white-box methodologies and early results of the first pr... more This deliverable reports the results of white-box methodologies and early results of the first prototype of libraries and programming abstractions as available by project month 18 by Work Package 2 (WP2). It reports i) the latest results of Task 2.2 on white-box methodologies, programming abstractions and libraries for developing energy-efficient data structures and algorithms and ii) the improved results of Task 2.1 on investigating and modeling the trade-off between energy and performance of concurrent data structures and algorithms. The work has been conducted on two main EXCESS platforms: Intel platforms with recent Intel multicore CPUs and Movidius Myriad1 platform. Regarding white-box methodologies, we have devised new relaxed cache-oblivious models and proposed a new power model for Myriad1 platform and an energy model for lock-free queues on CPU platforms. For Myriad1 platform, the im- proved model now considers both computation and data movement cost as well as architecture...
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Papers by Vi Tran Ngoc Nha