Bulletin of Electrical Engineering and Informatics
In the present study, hematite (α-Fe2O3) nanostructures were deposited on fluorine doped tin oxid... more In the present study, hematite (α-Fe2O3) nanostructures were deposited on fluorine doped tin oxide (FTO) coated glass substrate using sonicated immersion synthesis method. The effect of FTO glass substrate placement in Schott vial during immersion process was studied on the growth of the hematite nanostructure and its properties. XRD pattern has revealed seven diffraction peaks of α-Fe2O3 for both hematite nanostructures samples attributed to polycrystalline with rhombohedral lattice structure. The surface morphologies from FESEM have shown that the hematite nanostructures were grown uniformly in both samples with FTO conductive layer facing up and down. Hematite sample with FTO facing down exhibits a smaller size of nanorod, 26.7 nm average diameter, compared to the hematite sample that FTO face up with 53.8nm average diameter. Optical properties revealed higher transmittance in the sample with FTO facing down, probably due to smaller size of nanostructure. The optical band gap ene...
This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Conve... more This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Converter (ADC) with high speed comparator. The objective of this paper is to design and identify the performance of the ADC with two types of comparator. Another objective of this paper is to minimize the power consumption of the ADC circuit from a comparator. Flash ADC is one of the faster ways to convert any analog signal to a digital signal. It uses folding and interpolating techniques allow each comparator of the ADC to be reused several times over the full scale input range. In addition, interpolating technique can reduce the number of folding circuit required in a folding ADC hence further improve the performance of the ADC in term of capacitive loading and power consumption. Besides that, 70 percent speed of the ADC also depends on the comparator. If we use very fast and stable comparator, the ADC will be more fast and effectively to do the next applications. The simulation results indicate that the comparator design 1 achieved lower power operation rather than comparator design 2 with a minimum number of transistors used, 2GHz of input signal and 497.02mW of power consumption from a single 2V supply based to Gateway Silvaco EDA tools simulation result.
Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively stu... more Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively studied as the potential absorber layer for solar cell thin film application. Using sputtering technique however could result in the formation of several types of defects for example microscopic defects. Microscopic defects are formed within the absorber layer due to the formation of pinholes after surface treatment process. Since the effects of the formation of pinholes in CIS-based thin film solar cell is not well understood yet, a detail study is therefore necessary. In this work, a solar cell model was developed and simulated using Silvaco TCAD tools. Cylindrical pinholes of various diameters and depths were created and analyzed. The simulation results predicted that the number and depth of the pinholes affect the performance of the CIS-based thin film solar cell. The variation of pinhole diameter however did not exhibit any significant effect. It was found that the increases in the number of the pinholes resulted in the increases of solar cell efficiency. The efficiency was predicted to be of around 17.5% when ten pinholes existed within the CIS layer. No significant effect was found as the diameter of the pinhole became wider. Deeper the pinhole depth into the layer however produced the solar cell efficiency of only 1.37%.
This paper proposed a method that can measure the shallow trench isolation (STI) stress effect on... more This paper proposed a method that can measure the shallow trench isolation (STI) stress effect on transistor in the direction of channel width. Instead of implanting the entire channel (fixed width of 10mum), one portion of the channel (with fixed implant opening width of 0.5mum) was only implanted. By using this method, the channel edge can be brought away from the STI edge, where the active area is under high compressive stress. The results show that when the effective channel is near to the STI edge (high transverse compressive stress), both NMOS and PMOS transistors have higher threshold voltage, Vt and lower drain current, Id
In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transisto... more In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transistors by improving the Inter Layer Dielectric (ILD) process. We changed the Etch Stop Liner (ESL) from single stack silicon nitride (SiN) to dual stack ESL SiN/SiON. We then simulate the stress in 2D for both n-and p-channel MOSFET, and investigate how an oxynitride (SiON) buffer layer under the SiN ESL can reduce the longitudinal (X) and the lateral (Y) stress in both n-and p-channel thus improving the overall CMOS performance. Our result shows that the dual SiN/SiON layer reduces the stress in the channel length, direction (Sxx), perpendicular to channel plane direction (Syy) and channel width direction (Szz). It is known that decreasing the compressive stress in the X direction improves NMOS but degrades PMOS. Our experimental data shows that the additional SiON layer reduces the stress in the channel, hence increases the electron mobility.
Bulletin of Electrical Engineering and Informatics
In the present study, hematite (α-Fe2O3) nanostructures were deposited on fluorine doped tin oxid... more In the present study, hematite (α-Fe2O3) nanostructures were deposited on fluorine doped tin oxide (FTO) coated glass substrate using sonicated immersion synthesis method. The effect of FTO glass substrate placement in Schott vial during immersion process was studied on the growth of the hematite nanostructure and its properties. XRD pattern has revealed seven diffraction peaks of α-Fe2O3 for both hematite nanostructures samples attributed to polycrystalline with rhombohedral lattice structure. The surface morphologies from FESEM have shown that the hematite nanostructures were grown uniformly in both samples with FTO conductive layer facing up and down. Hematite sample with FTO facing down exhibits a smaller size of nanorod, 26.7 nm average diameter, compared to the hematite sample that FTO face up with 53.8nm average diameter. Optical properties revealed higher transmittance in the sample with FTO facing down, probably due to smaller size of nanostructure. The optical band gap ene...
This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Conve... more This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Converter (ADC) with high speed comparator. The objective of this paper is to design and identify the performance of the ADC with two types of comparator. Another objective of this paper is to minimize the power consumption of the ADC circuit from a comparator. Flash ADC is one of the faster ways to convert any analog signal to a digital signal. It uses folding and interpolating techniques allow each comparator of the ADC to be reused several times over the full scale input range. In addition, interpolating technique can reduce the number of folding circuit required in a folding ADC hence further improve the performance of the ADC in term of capacitive loading and power consumption. Besides that, 70 percent speed of the ADC also depends on the comparator. If we use very fast and stable comparator, the ADC will be more fast and effectively to do the next applications. The simulation results indicate that the comparator design 1 achieved lower power operation rather than comparator design 2 with a minimum number of transistors used, 2GHz of input signal and 497.02mW of power consumption from a single 2V supply based to Gateway Silvaco EDA tools simulation result.
Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively stu... more Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively studied as the potential absorber layer for solar cell thin film application. Using sputtering technique however could result in the formation of several types of defects for example microscopic defects. Microscopic defects are formed within the absorber layer due to the formation of pinholes after surface treatment process. Since the effects of the formation of pinholes in CIS-based thin film solar cell is not well understood yet, a detail study is therefore necessary. In this work, a solar cell model was developed and simulated using Silvaco TCAD tools. Cylindrical pinholes of various diameters and depths were created and analyzed. The simulation results predicted that the number and depth of the pinholes affect the performance of the CIS-based thin film solar cell. The variation of pinhole diameter however did not exhibit any significant effect. It was found that the increases in the number of the pinholes resulted in the increases of solar cell efficiency. The efficiency was predicted to be of around 17.5% when ten pinholes existed within the CIS layer. No significant effect was found as the diameter of the pinhole became wider. Deeper the pinhole depth into the layer however produced the solar cell efficiency of only 1.37%.
This paper proposed a method that can measure the shallow trench isolation (STI) stress effect on... more This paper proposed a method that can measure the shallow trench isolation (STI) stress effect on transistor in the direction of channel width. Instead of implanting the entire channel (fixed width of 10mum), one portion of the channel (with fixed implant opening width of 0.5mum) was only implanted. By using this method, the channel edge can be brought away from the STI edge, where the active area is under high compressive stress. The results show that when the effective channel is near to the STI edge (high transverse compressive stress), both NMOS and PMOS transistors have higher threshold voltage, Vt and lower drain current, Id
In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transisto... more In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transistors by improving the Inter Layer Dielectric (ILD) process. We changed the Etch Stop Liner (ESL) from single stack silicon nitride (SiN) to dual stack ESL SiN/SiON. We then simulate the stress in 2D for both n-and p-channel MOSFET, and investigate how an oxynitride (SiON) buffer layer under the SiN ESL can reduce the longitudinal (X) and the lateral (Y) stress in both n-and p-channel thus improving the overall CMOS performance. Our result shows that the dual SiN/SiON layer reduces the stress in the channel length, direction (Sxx), perpendicular to channel plane direction (Syy) and channel width direction (Szz). It is known that decreasing the compressive stress in the X direction improves NMOS but degrades PMOS. Our experimental data shows that the additional SiON layer reduces the stress in the channel, hence increases the electron mobility.
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