: Increasing of design complexity of integrated circuits on one hand and need to segregate activi... more : Increasing of design complexity of integrated circuits on one hand and need to segregate activities of computation and communication sections in today's IC chips on the other hand, has directed design path towards systems based on network- on-chip. Nowadays, having high reliability in face of unwanted environmental factors is an important goal in the designing of computational systems; factors against which the vulnerabilities of circuits are ever more increasing as the sizes continually diminish in the areas of chip manufacturing technologies. In this respect, the networks-on-chip, as a scalable communication substructure in systems-on-chip, should possess this characteristic. In this thesis, the networks-on-chip have been examined with respect to their internal structure and various types of connections and breakdowns, and also different routing algorithms and fault-tolerant routing algorithms against permanent faults and problems have been introduced and presented. Then, the designs of two types of routing algorithms tolerant of connection faults, have been presented, that in first method we use ant colony algorithm and how ants can skip the obstacles when searching for food sources. In this method packets was considered as ants and obstacles as a failures. to further explore a second method is proposed. This algorithm is based on DyXY algorithm that tolerance permanent link failures and also the algorithm is aware of the congestion. The simulation results show that the proposed algorithm has better performance in all evaluation parameters such as delay and reliability than planar adapt routing algorithm.
... Javad Javidan1, Pooya Torkzadeh1, Mojtaba Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T.... more ... Javad Javidan1, Pooya Torkzadeh1, Mojtaba Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehran ... As far as, the output voltage peaks at the most negative input signal, in this architecture the peak voltage across the gate oxide of Q4 would be increased and severe ...
... For third two-turn transformer, higher efficiency is achieved on the condition which first an... more ... For third two-turn transformer, higher efficiency is achieved on the condition which first and third gain voltages are chosen by the same amount and ... In this condition, a curve-fitting approach would be used in extracting capacitor size ... 1] I. Aoki, S. Kee, D. Rutledge, A. Hajimiri, 2.4 ...
This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) u... more This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped VCO oscillating signal maximizing effectively signal slope at zero crossing points and with steering coupling section current transistors by quadrature signals. A comprehensive analysis for frequency and amplitude mismatch as high as 20% for third harmonic and its effect on phase noise improvement will be presented. It will be shown that by tuning the LC tank on fundamental and third harmonic and controlling current transistors, total phase noise improvement will be as high as 9 dB. Designed HT LC quadrature VCO has been implemented using TSMC 0.18 um 1P6M CMOS technology operating at 1.8 V for frequency band of 2.4-2.6 GHz (ISM band) with achieved phase noise of -139 dBc/Hz at frequency offset of 3 MHz. Total current drawn by VCO is 3.9 mA making the power consumption and its figure-of-merit (FOM) as low as 7 mW and -189 dB respectively.
... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 Nijad Anabtawi3 1 SICAS Group, EE Dept., Shari... more ... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 Nijad Anabtawi3 1 SICAS Group, EE Dept., Sharif U. of T., Tehran 2 Mix Core Design 3Arizona State University ... [1] K. Vleugels, S. Rabii, andBA Wooley, A 2.5 V broadband multi-bit modulator with 95 dB dynamic range, in Dig. ...
... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehr... more ... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehran 2 Mix Core Design ... REFERENCES [1] K. Vleugels, S. Rabii, and BA Wooley, A 2.5 V broadband multi-bit modulator with 95 dB dynamic range, in Dig. Tech. ...
... Power Combiner Blocks in CMOS Technology Javad Javidan1 Mojtaba Atarodi1,2 Pooya Torkzadeh1 1... more ... Power Combiner Blocks in CMOS Technology Javad Javidan1 Mojtaba Atarodi1,2 Pooya Torkzadeh1 1 SICAS Group, EE Dept., Sharif U. of T., Tehran ... As far as coupling factor is less than one in practice, the current of primary side is normally higher than secondary side one. ...
With the rapid development of information technology in various fields as well as need for high-s... more With the rapid development of information technology in various fields as well as need for high-speed storage and retrieval of information, It provides a bed to produce the high-speed memory and are also less hardware complexity. As a result, storage speed and hardware complexity as a major challenge in the memory structure has become. To meet this challenge in memory controller, the embedded Error Correction Codes (ECC) block called the main task is to overcome the high rate of error, as to increase the speed and reduce the complexity of hardware error correction codes are used. Error correction codes are used in a variety of studies that have been done in NAND Flash memory controller. Bose-Chaudhuri-Hocqunghem (BCH) error correction codes in this thesis structure and BCH encoder and decoder examined two blocks, and ways to optimize the BCH decoder blocks to be offered to enhance the efficiency of data storage. The BCH codeword is decoded by passing through three stages: calculatin...
The definition of actual framework of the motor cycle in engine combustion models needs to precis... more The definition of actual framework of the motor cycle in engine combustion models needs to precise and fast measurement of the experimental cycle of engine in order to evaluate operation of the simulator models and verify them. One of the difficult characteristics of measuring is determining the composition amount and the thermodynamic properties of remaining burned gases from the previous cycle. If performance of engine simulation model is control by using experimental cycles in which the burnt gases from the previous cycle is omitted, the evaluation of the model would be acceptable without any phenomenon of the remaining gases. In this thesis free residual gas cycles have been obtained by using skip fire (SF) method. For possibility of the proper adjustment of spark advance, equivalence ratio, the starting point of injection, the fuel injection length, and also SF, control device of engine configuration was designed and manfactured. As well for the extraction of precise pressure d...
International Journal of NanoScience and Nanotechnology, 2017
Multiplier is one of the important components in many systems such as digital filters, digital pr... more Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the area of multipliers. Compressors are adders which can be used to perform the partial product addition in Wallace tree. On the other hand, using new emerging technologies such as Carbon Nanotube Field Effect Transistors (CNTFET) leads to provide implementations faster and smaller circuits. This paper presents a new method to reduce the simplification of Wallace tree design using high order compressors based on carbon nanotube technology. These compressors use a high-speed full adder cell based on CNTFETs for low-voltage and high-frequency applications. The proposed method reduces the number of...
: Increasing of design complexity of integrated circuits on one hand and need to segregate activi... more : Increasing of design complexity of integrated circuits on one hand and need to segregate activities of computation and communication sections in today's IC chips on the other hand, has directed design path towards systems based on network- on-chip. Nowadays, having high reliability in face of unwanted environmental factors is an important goal in the designing of computational systems; factors against which the vulnerabilities of circuits are ever more increasing as the sizes continually diminish in the areas of chip manufacturing technologies. In this respect, the networks-on-chip, as a scalable communication substructure in systems-on-chip, should possess this characteristic. In this thesis, the networks-on-chip have been examined with respect to their internal structure and various types of connections and breakdowns, and also different routing algorithms and fault-tolerant routing algorithms against permanent faults and problems have been introduced and presented. Then, the designs of two types of routing algorithms tolerant of connection faults, have been presented, that in first method we use ant colony algorithm and how ants can skip the obstacles when searching for food sources. In this method packets was considered as ants and obstacles as a failures. to further explore a second method is proposed. This algorithm is based on DyXY algorithm that tolerance permanent link failures and also the algorithm is aware of the congestion. The simulation results show that the proposed algorithm has better performance in all evaluation parameters such as delay and reliability than planar adapt routing algorithm.
... Javad Javidan1, Pooya Torkzadeh1, Mojtaba Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T.... more ... Javad Javidan1, Pooya Torkzadeh1, Mojtaba Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehran ... As far as, the output voltage peaks at the most negative input signal, in this architecture the peak voltage across the gate oxide of Q4 would be increased and severe ...
... For third two-turn transformer, higher efficiency is achieved on the condition which first an... more ... For third two-turn transformer, higher efficiency is achieved on the condition which first and third gain voltages are chosen by the same amount and ... In this condition, a curve-fitting approach would be used in extracting capacitor size ... 1] I. Aoki, S. Kee, D. Rutledge, A. Hajimiri, 2.4 ...
This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) u... more This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped VCO oscillating signal maximizing effectively signal slope at zero crossing points and with steering coupling section current transistors by quadrature signals. A comprehensive analysis for frequency and amplitude mismatch as high as 20% for third harmonic and its effect on phase noise improvement will be presented. It will be shown that by tuning the LC tank on fundamental and third harmonic and controlling current transistors, total phase noise improvement will be as high as 9 dB. Designed HT LC quadrature VCO has been implemented using TSMC 0.18 um 1P6M CMOS technology operating at 1.8 V for frequency band of 2.4-2.6 GHz (ISM band) with achieved phase noise of -139 dBc/Hz at frequency offset of 3 MHz. Total current drawn by VCO is 3.9 mA making the power consumption and its figure-of-merit (FOM) as low as 7 mW and -189 dB respectively.
... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 Nijad Anabtawi3 1 SICAS Group, EE Dept., Shari... more ... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 Nijad Anabtawi3 1 SICAS Group, EE Dept., Sharif U. of T., Tehran 2 Mix Core Design 3Arizona State University ... [1] K. Vleugels, S. Rabii, andBA Wooley, A 2.5 V broadband multi-bit modulator with 95 dB dynamic range, in Dig. ...
... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehr... more ... Pooya Torkzadeh1, Javad Javidan1, M.Atarodi1,2 1 SICAS Group, EE Dept., Sharif U. of T., Tehran 2 Mix Core Design ... REFERENCES [1] K. Vleugels, S. Rabii, and BA Wooley, A 2.5 V broadband multi-bit modulator with 95 dB dynamic range, in Dig. Tech. ...
... Power Combiner Blocks in CMOS Technology Javad Javidan1 Mojtaba Atarodi1,2 Pooya Torkzadeh1 1... more ... Power Combiner Blocks in CMOS Technology Javad Javidan1 Mojtaba Atarodi1,2 Pooya Torkzadeh1 1 SICAS Group, EE Dept., Sharif U. of T., Tehran ... As far as coupling factor is less than one in practice, the current of primary side is normally higher than secondary side one. ...
With the rapid development of information technology in various fields as well as need for high-s... more With the rapid development of information technology in various fields as well as need for high-speed storage and retrieval of information, It provides a bed to produce the high-speed memory and are also less hardware complexity. As a result, storage speed and hardware complexity as a major challenge in the memory structure has become. To meet this challenge in memory controller, the embedded Error Correction Codes (ECC) block called the main task is to overcome the high rate of error, as to increase the speed and reduce the complexity of hardware error correction codes are used. Error correction codes are used in a variety of studies that have been done in NAND Flash memory controller. Bose-Chaudhuri-Hocqunghem (BCH) error correction codes in this thesis structure and BCH encoder and decoder examined two blocks, and ways to optimize the BCH decoder blocks to be offered to enhance the efficiency of data storage. The BCH codeword is decoded by passing through three stages: calculatin...
The definition of actual framework of the motor cycle in engine combustion models needs to precis... more The definition of actual framework of the motor cycle in engine combustion models needs to precise and fast measurement of the experimental cycle of engine in order to evaluate operation of the simulator models and verify them. One of the difficult characteristics of measuring is determining the composition amount and the thermodynamic properties of remaining burned gases from the previous cycle. If performance of engine simulation model is control by using experimental cycles in which the burnt gases from the previous cycle is omitted, the evaluation of the model would be acceptable without any phenomenon of the remaining gases. In this thesis free residual gas cycles have been obtained by using skip fire (SF) method. For possibility of the proper adjustment of spark advance, equivalence ratio, the starting point of injection, the fuel injection length, and also SF, control device of engine configuration was designed and manfactured. As well for the extraction of precise pressure d...
International Journal of NanoScience and Nanotechnology, 2017
Multiplier is one of the important components in many systems such as digital filters, digital pr... more Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the area of multipliers. Compressors are adders which can be used to perform the partial product addition in Wallace tree. On the other hand, using new emerging technologies such as Carbon Nanotube Field Effect Transistors (CNTFET) leads to provide implementations faster and smaller circuits. This paper presents a new method to reduce the simplification of Wallace tree design using high order compressors based on carbon nanotube technology. These compressors use a high-speed full adder cell based on CNTFETs for low-voltage and high-frequency applications. The proposed method reduces the number of...
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