TELKOMNIKA (Telecommunication Computing Electronics and Control)
This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for u... more This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for use in education, engineering, and research. Signals of interest are tapped throughout the microprocessor hierarchical design and are then output to the top-level entity and finally displayed to a VGA monitor. Input clock signal can be fed as slow as one wish to trace or debug the microprocessor being designed. An FPGA development board, along with its accompanying software package, is used as the design and test platform. The use of VHDL commands 'type' and 'record' in the hierarchy provides key ingredients in the overall design, since this allows simple, clean, and tractable code. The method is tested on MIPS single-cycle microprocessor blueprint. The result shows that the technique produces more consistent display of the true contents of registers, ALU input/output signals, and other wires-compared to the standard, widely-used simulation method. This approach is expected to increase confidence in students and designers since the reported signals' values are the true values. Its use is not limited to the development of microprocessors; every FPGA-based digital design can benefit from it. This is an open access article under the CC BY-SA license. 1. INTRODUCTION Digital device development depends greatly on precise understanding how data propagate between basic digital logic units, also called register transfer level. In design phase, designers often use simulation procedures to check whether their designs meet the logic requirements. An example of this is also encountered in senior level electrical/computer engineering bachelor-degree courses such as Programmable Logic Design or Computer Architecture [1-4]. In such courses, students are asked to design a micro-architecture of a microprocessor based on a given architecture (that is, the assembly language requirement). Students then write HDL code representing the micro-architecture and test the design against a set of instructions. Testing is generally done in simulation and, after a number of testing-coding iterations, hardware test is performed. Software simulation is indispensable for its quick setting, fast compilation, and-provided the designer is experienced-accuracy. However, mismatches between simulation and synthesized hardware are not entirely unheard of, even for simple design. Mismatches also occur between pre-synthesis and post-synthesis simulations. To make matter worse, in post-synthesis (netlist) simulation one generally can only monitor the top-level ports; signals deeper in hierarchy are inaccessible. To address this problem, we propose a closer-to-metal approach for the register transfer level inspection. Effectively, this is an on-chip debugging technique Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA
Khazanah Informatika: Jurnal Ilmu Komputer dan Informatika
Situs web dengan traffic yang tinggi dapat menyebabkan beban kerja yang berat di sisi server, yan... more Situs web dengan traffic yang tinggi dapat menyebabkan beban kerja yang berat di sisi server, yang pada gilirannya akan mengakibatkan turunnya kinerja server, bahkan kegagalan sistem secara keseluruhan. Salah satu solusi untuk mengatasi masalah tersebut adalah dengan menerapkan teknik load balancing dan failover. Load balancing merupakan teknologi untuk melakukan pembagian beban kepada beberapa server, memastikan tidak terjadi kelebihan beban pada salah satu server. Sementara itu, failover merupakan kemampuan suatu sistem untuk berpindah ke sistem cadangan jika sistem utama mengalami kegagalan. Dalam penelitian ini load balancing dengan teknik failover akan diimplementasikan pada sistem operasi Ubuntu. Software inti yang digunakan dalam penelitian ini adalah Nginx dan KeepAlived. Nginx akan berfungsi sebagai load balancer, sedangkan KeepAlived untuk mengimplementasikan teknik failover. Beberapa skenario telah disiapkan untuk menguji sistem load balancing yang telah dirancang. Penguj...
ABSTRACT In this paper we present a method to generate minimum-time constrained trajectories for ... more ABSTRACT In this paper we present a method to generate minimum-time constrained trajectories for a magnetic-levitation (Maglev) system. The Maglev model is a differentially flat system, and as such it has the useful property that the input and the state trajectories can be completely characterised by the so-called flat output. We propose a B-splines parameterisation for the flat output, and the corresponding parameterisation for the performance output, the states, and the inputs. Using this parameterisation the problem of minimum-time constrained trajectory planning is cast into a feasibility-search problem in the spline control-points space, in which the constraint region is characterised by a polytope. A close approximation of the minimum-time trajectory is obtained by systematically searching the end-time that makes the constraint polytope to be minimally feasible. Experimental results, validating the method on a laboratory real system, are presented.
In this preliminary report paper we discuss a low-cost approach to information system integration... more In this preliminary report paper we discuss a low-cost approach to information system integration (" ISI ") in an enterprise setup. The approach relies upon the notion of unique identifier (UID) and continual synchronization. The approach is low-cost since it does not require high-skill from the IT staff (as compared to, for example, enterprise-service-bus approach), relatively easy to develop, and can be built entirely on well-known open-source software packages. The approach can, and should, be regarded as an intermediary technology before a company is able to deploy and operate a full-fledged integration scheme for its information systems. The research is based on an ongoing design and study of ISI in a university setup.
2010 Conference on Control and Fault-Tolerant Systems (SysTol), 2010
This paper discusses fault detection and isolation for continuous-time systems using B-Splines an... more This paper discusses fault detection and isolation for continuous-time systems using B-Splines and the notion of differential flatness. The idea is, from the system's flat outputs (which are obtained directly from measurement or from an observer), we algebraically produce every other measured signal, including the inputs. The corresponding signals are then compared. In nominal condition, a measured signal and its
The main contribution of this paper is to provide a unified treatment to the problems of constrai... more The main contribution of this paper is to provide a unified treatment to the problems of constrained minimum-time trajectory generation, fault detection and identification, and (after a fault has been detected and identified) trajectory reconfiguration, in an integrated scheme using a differential flatness and B-splines parameterisation. Using the flatness/B-splines parameterisation the problem of minimum-time constrained trajectory planning is cast into a feasibility-search problem in the splines control-points space, in which the constraint region is characterised by a polytope. A close approximation of the minimum-time trajectory is obtained by systematically searching the end-time that makes the constraint polytope to be minimally feasible. Fault detection is carried out by using B-splines in an FIR filter implementation. Thus, the three—traditionally dealt with separately—problems (namely, trajectory generation, fault detection, and trajectory reconfiguration) are solved in a unified manner, using the same mathematical/computational tools. This, not only offers an elegant solution, but also has the potential to simplify the coding of the algorithms for the real-time application of the strategy. All through the paper, a case-study consisting in an input-constrained double-tank system is analysed in order to illustrate the techniques in an intuitive manner.
TELKOMNIKA (Telecommunication Computing Electronics and Control)
This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for u... more This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for use in education, engineering, and research. Signals of interest are tapped throughout the microprocessor hierarchical design and are then output to the top-level entity and finally displayed to a VGA monitor. Input clock signal can be fed as slow as one wish to trace or debug the microprocessor being designed. An FPGA development board, along with its accompanying software package, is used as the design and test platform. The use of VHDL commands 'type' and 'record' in the hierarchy provides key ingredients in the overall design, since this allows simple, clean, and tractable code. The method is tested on MIPS single-cycle microprocessor blueprint. The result shows that the technique produces more consistent display of the true contents of registers, ALU input/output signals, and other wires-compared to the standard, widely-used simulation method. This approach is expected to increase confidence in students and designers since the reported signals' values are the true values. Its use is not limited to the development of microprocessors; every FPGA-based digital design can benefit from it. This is an open access article under the CC BY-SA license. 1. INTRODUCTION Digital device development depends greatly on precise understanding how data propagate between basic digital logic units, also called register transfer level. In design phase, designers often use simulation procedures to check whether their designs meet the logic requirements. An example of this is also encountered in senior level electrical/computer engineering bachelor-degree courses such as Programmable Logic Design or Computer Architecture [1-4]. In such courses, students are asked to design a micro-architecture of a microprocessor based on a given architecture (that is, the assembly language requirement). Students then write HDL code representing the micro-architecture and test the design against a set of instructions. Testing is generally done in simulation and, after a number of testing-coding iterations, hardware test is performed. Software simulation is indispensable for its quick setting, fast compilation, and-provided the designer is experienced-accuracy. However, mismatches between simulation and synthesized hardware are not entirely unheard of, even for simple design. Mismatches also occur between pre-synthesis and post-synthesis simulations. To make matter worse, in post-synthesis (netlist) simulation one generally can only monitor the top-level ports; signals deeper in hierarchy are inaccessible. To address this problem, we propose a closer-to-metal approach for the register transfer level inspection. Effectively, this is an on-chip debugging technique Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA
Khazanah Informatika: Jurnal Ilmu Komputer dan Informatika
Situs web dengan traffic yang tinggi dapat menyebabkan beban kerja yang berat di sisi server, yan... more Situs web dengan traffic yang tinggi dapat menyebabkan beban kerja yang berat di sisi server, yang pada gilirannya akan mengakibatkan turunnya kinerja server, bahkan kegagalan sistem secara keseluruhan. Salah satu solusi untuk mengatasi masalah tersebut adalah dengan menerapkan teknik load balancing dan failover. Load balancing merupakan teknologi untuk melakukan pembagian beban kepada beberapa server, memastikan tidak terjadi kelebihan beban pada salah satu server. Sementara itu, failover merupakan kemampuan suatu sistem untuk berpindah ke sistem cadangan jika sistem utama mengalami kegagalan. Dalam penelitian ini load balancing dengan teknik failover akan diimplementasikan pada sistem operasi Ubuntu. Software inti yang digunakan dalam penelitian ini adalah Nginx dan KeepAlived. Nginx akan berfungsi sebagai load balancer, sedangkan KeepAlived untuk mengimplementasikan teknik failover. Beberapa skenario telah disiapkan untuk menguji sistem load balancing yang telah dirancang. Penguj...
ABSTRACT In this paper we present a method to generate minimum-time constrained trajectories for ... more ABSTRACT In this paper we present a method to generate minimum-time constrained trajectories for a magnetic-levitation (Maglev) system. The Maglev model is a differentially flat system, and as such it has the useful property that the input and the state trajectories can be completely characterised by the so-called flat output. We propose a B-splines parameterisation for the flat output, and the corresponding parameterisation for the performance output, the states, and the inputs. Using this parameterisation the problem of minimum-time constrained trajectory planning is cast into a feasibility-search problem in the spline control-points space, in which the constraint region is characterised by a polytope. A close approximation of the minimum-time trajectory is obtained by systematically searching the end-time that makes the constraint polytope to be minimally feasible. Experimental results, validating the method on a laboratory real system, are presented.
In this preliminary report paper we discuss a low-cost approach to information system integration... more In this preliminary report paper we discuss a low-cost approach to information system integration (" ISI ") in an enterprise setup. The approach relies upon the notion of unique identifier (UID) and continual synchronization. The approach is low-cost since it does not require high-skill from the IT staff (as compared to, for example, enterprise-service-bus approach), relatively easy to develop, and can be built entirely on well-known open-source software packages. The approach can, and should, be regarded as an intermediary technology before a company is able to deploy and operate a full-fledged integration scheme for its information systems. The research is based on an ongoing design and study of ISI in a university setup.
2010 Conference on Control and Fault-Tolerant Systems (SysTol), 2010
This paper discusses fault detection and isolation for continuous-time systems using B-Splines an... more This paper discusses fault detection and isolation for continuous-time systems using B-Splines and the notion of differential flatness. The idea is, from the system's flat outputs (which are obtained directly from measurement or from an observer), we algebraically produce every other measured signal, including the inputs. The corresponding signals are then compared. In nominal condition, a measured signal and its
The main contribution of this paper is to provide a unified treatment to the problems of constrai... more The main contribution of this paper is to provide a unified treatment to the problems of constrained minimum-time trajectory generation, fault detection and identification, and (after a fault has been detected and identified) trajectory reconfiguration, in an integrated scheme using a differential flatness and B-splines parameterisation. Using the flatness/B-splines parameterisation the problem of minimum-time constrained trajectory planning is cast into a feasibility-search problem in the splines control-points space, in which the constraint region is characterised by a polytope. A close approximation of the minimum-time trajectory is obtained by systematically searching the end-time that makes the constraint polytope to be minimally feasible. Fault detection is carried out by using B-splines in an FIR filter implementation. Thus, the three—traditionally dealt with separately—problems (namely, trajectory generation, fault detection, and trajectory reconfiguration) are solved in a unified manner, using the same mathematical/computational tools. This, not only offers an elegant solution, but also has the potential to simplify the coding of the algorithms for the real-time application of the strategy. All through the paper, a case-study consisting in an input-constrained double-tank system is analysed in order to illustrate the techniques in an intuitive manner.
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Papers by Fajar Suryawan