The current trend of increasing the complexity of hardware accelerators to improve their function... more The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, t...
— Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temp... more — Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data-paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption.
IEEE Transactions on Device and Materials Reliability, 2020
In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial... more In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial-of-service (DoS) attacks by causing voltage emergencies that may lead to data corruptions and system crashes in multi-core processors. This attack targets processors whose operating voltage has been reduced in-the-field for improving energy efficiency. To protect such undervolted processors from this type of attacks, we present a run-time system for detecting and mitigating power-noise viruses. We present voltage noise data from power-noise viruses and benchmarks collected from an Arm multi-core processor, and we observe that the frequency of voltage emergencies dramatically increases during the execution of power-noise attacks. Based on this observation, we propose a regression model that allows for a run-time estimation of the severity of voltage emergencies by monitoring the frequency of voltage emergencies and the operating frequency of the processor. For mitigating the problem, during the execution of critical tasks requiring protection, our system periodically evaluates the severity of voltage emergencies and adapts the operating frequency of the processor in order to reduce the severity of the attack according to a predefined constraint. We demonstrate the efficiency of the proposed run-time protection system on an actual Arm multi-core processor using two power-noise viruses, and we explore trade-offs between protection latency, CPU utilization and power cost. The proposed software achieves with a very low CPU utilization overhead of less than 0.11% to detect and mitigate power-noise DoS attacks with a latency of 100 $\mu {\mathrm{ s}}$ .
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)
We address the problem of devising the error correcting code which, if used to encode the informa... more We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses
11th IEEE International On-Line Testing Symposium, 2005
As device geometries shrink, power supply voltage de-creases, and chip complexity increases, the ... more As device geometries shrink, power supply voltage de-creases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming cru-cial in determining the signal integrity of a ...
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.
We propose a clock buffer that is able to compensate clock skews possibly due to process variatio... more We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution net-work or those due to power supply noise. Compensation/correction ...
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
We analyze the impact of clock faults on product quality and operation in the field. We show that... more We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generate... more In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the ...
Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay ... more Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses imple- menting an error detecting/correcting code. This tech- nique is based on the observation that the maximum delay on an encoded,bus is usually due to the check bits that are added to provide the desired error detec- tion/tolerance ability. These bits, in fact,
Proceedings. 10th IEEE International On-Line Testing Symposium
Abstract Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in... more Abstract Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in high reliability applications, can make them provide the fan-out logic with incorrect data, hence making the adoption of the TMR technique useless. In this paper we ...
Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decrease... more Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the de-sign phase, the robustness of circuits for high reliability ap-plications with respect to this kind of faults is generally val-idated through simulations. However, ...
In this paper we propose a novel buffer scheme that is able to compensate undesired skews between... more In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occur-rence, thus being suitable also for on-line clock-skew cor-rection. Clock signals are aligned one with ...
This paper presents a method to reduce area overhead and timing impact due to the implementation ... more This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of
The current trend of increasing the complexity of hardware accelerators to improve their function... more The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, t...
— Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temp... more — Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data-paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption.
IEEE Transactions on Device and Materials Reliability, 2020
In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial... more In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial-of-service (DoS) attacks by causing voltage emergencies that may lead to data corruptions and system crashes in multi-core processors. This attack targets processors whose operating voltage has been reduced in-the-field for improving energy efficiency. To protect such undervolted processors from this type of attacks, we present a run-time system for detecting and mitigating power-noise viruses. We present voltage noise data from power-noise viruses and benchmarks collected from an Arm multi-core processor, and we observe that the frequency of voltage emergencies dramatically increases during the execution of power-noise attacks. Based on this observation, we propose a regression model that allows for a run-time estimation of the severity of voltage emergencies by monitoring the frequency of voltage emergencies and the operating frequency of the processor. For mitigating the problem, during the execution of critical tasks requiring protection, our system periodically evaluates the severity of voltage emergencies and adapts the operating frequency of the processor in order to reduce the severity of the attack according to a predefined constraint. We demonstrate the efficiency of the proposed run-time protection system on an actual Arm multi-core processor using two power-noise viruses, and we explore trade-offs between protection latency, CPU utilization and power cost. The proposed software achieves with a very low CPU utilization overhead of less than 0.11% to detect and mitigate power-noise DoS attacks with a latency of 100 $\mu {\mathrm{ s}}$ .
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)
We address the problem of devising the error correcting code which, if used to encode the informa... more We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses
11th IEEE International On-Line Testing Symposium, 2005
As device geometries shrink, power supply voltage de-creases, and chip complexity increases, the ... more As device geometries shrink, power supply voltage de-creases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming cru-cial in determining the signal integrity of a ...
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.
We propose a clock buffer that is able to compensate clock skews possibly due to process variatio... more We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution net-work or those due to power supply noise. Compensation/correction ...
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
We analyze the impact of clock faults on product quality and operation in the field. We show that... more We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generate... more In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the ...
Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay ... more Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses imple- menting an error detecting/correcting code. This tech- nique is based on the observation that the maximum delay on an encoded,bus is usually due to the check bits that are added to provide the desired error detec- tion/tolerance ability. These bits, in fact,
Proceedings. 10th IEEE International On-Line Testing Symposium
Abstract Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in... more Abstract Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in high reliability applications, can make them provide the fan-out logic with incorrect data, hence making the adoption of the TMR technique useless. In this paper we ...
Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decrease... more Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the de-sign phase, the robustness of circuits for high reliability ap-plications with respect to this kind of faults is generally val-idated through simulations. However, ...
In this paper we propose a novel buffer scheme that is able to compensate undesired skews between... more In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occur-rence, thus being suitable also for on-line clock-skew cor-rection. Clock signals are aligned one with ...
This paper presents a method to reduce area overhead and timing impact due to the implementation ... more This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of
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