The paper presents a digital foreground calibration technique for pipeline analog-to-digital conv... more The paper presents a digital foreground calibration technique for pipeline analog-to-digital converters (ADCs). While the conventional calibration approach requires additional buffered voltage references, the proposed technique requires only a voltage reference, already available in the converter, thus allowing a significant circuit simplification and silicon area savings. Since the number of buffered voltage references in the conventional calibration algorithm increases exponentially with the resolution of the conversion stages to be calibrated, the proposed technique is suitable for high-resolution, high-speed pipeline ADCs.
The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-... more The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-μm CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.
A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed... more A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed. The structure consists of seven successive approximation A/D converters designed to pursue high speed and low power consumption. A merged-capacitor technique is implemented in the DAC, while the successive approximations register is based on a single-row architecture with D-FF's. The converter, designed in ST 90nm CMOS technology exhibits a maximum sampling frequency of 1.2 GHz at 1 V supply with a 500 mV input range and 16 mW of power consumption. The simulated figure of merit is 0.3 pJ/conv
This paper describes an accurate model for the systematic design and the simulation of high-resol... more This paper describes an accurate model for the systematic design and the simulation of high-resolution pipelined ADCs. The design is based on the non-linearities affecting the ADC whereas the goal is the evaluation of the best architecture matching the specifications (DNL and INL). Bit partitioning along pipeline chain, amplifiers specifications (designed down to transistor-level in both CMOS and BiCMOS technologies), capacitors size, power consumption and calibration requirements are delivered. An integrated simulation tool allows the performances evaluation of the converter. The complete design suite was implemented in MATLAB
The paper describes the design and the implementation of a track-and-hold (THA) amplifier suitabl... more The paper describes the design and the implementation of a track-and-hold (THA) amplifier suitable for a 14-b, 100 MS/s A/D converter, in 0.18 μm CMOS technology. The THA is based on the flip-around architecture with telescopic cascode OTA. Adequate settling behavior was achieved by means of accurate analysis and design of the boosting amplifier with respect to its impact on the pole-zero placement. A modified bootstrap switch featuring a high linearity and reduced complexity is also presented.
The paper presents a digital foreground calibration technique for pipeline analog-to-digital conv... more The paper presents a digital foreground calibration technique for pipeline analog-to-digital converters (ADCs). While the conventional calibration approach requires additional buffered voltage references, the proposed technique requires only a voltage reference, already available in the converter, thus allowing a significant circuit simplification and silicon area savings. Since the number of buffered voltage references in the conventional calibration algorithm increases exponentially with the resolution of the conversion stages to be calibrated, the proposed technique is suitable for high-resolution, high-speed pipeline ADCs.
The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-... more The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-μm CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.
A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed... more A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed. The structure consists of seven successive approximation A/D converters designed to pursue high speed and low power consumption. A merged-capacitor technique is implemented in the DAC, while the successive approximations register is based on a single-row architecture with D-FF's. The converter, designed in ST 90nm CMOS technology exhibits a maximum sampling frequency of 1.2 GHz at 1 V supply with a 500 mV input range and 16 mW of power consumption. The simulated figure of merit is 0.3 pJ/conv
This paper describes an accurate model for the systematic design and the simulation of high-resol... more This paper describes an accurate model for the systematic design and the simulation of high-resolution pipelined ADCs. The design is based on the non-linearities affecting the ADC whereas the goal is the evaluation of the best architecture matching the specifications (DNL and INL). Bit partitioning along pipeline chain, amplifiers specifications (designed down to transistor-level in both CMOS and BiCMOS technologies), capacitors size, power consumption and calibration requirements are delivered. An integrated simulation tool allows the performances evaluation of the converter. The complete design suite was implemented in MATLAB
The paper describes the design and the implementation of a track-and-hold (THA) amplifier suitabl... more The paper describes the design and the implementation of a track-and-hold (THA) amplifier suitable for a 14-b, 100 MS/s A/D converter, in 0.18 μm CMOS technology. The THA is based on the flip-around architecture with telescopic cascode OTA. Adequate settling behavior was achieved by means of accurate analysis and design of the boosting amplifier with respect to its impact on the pole-zero placement. A modified bootstrap switch featuring a high linearity and reduced complexity is also presented.
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