Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for h... more Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9
Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for h... more Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9
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Papers by Vijay Pawar