The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparat... more The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode ...
Analog Integrated Circuits and Signal Processing, 2004
We present in this paper an overview of circuit techniques dedicated to design reliable low-volta... more We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-of-the-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.
This paper presents the design and characterization of a sample-and-hold circuit based on a novel... more This paper presents the design and characterization of a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced, resulting in improved sample-and-hold accuracy. Experimental results in a 0.18 μm digital CMOS process show that a resolution greater than 10 bits can be obtained with a 1.0 V supply voltage. Circuit operation is also possible for supply voltages close to the transistor threshold (e.g., 0.65 V).
This paper addresses the selectivity problem, for the ultra-wide band (UWB), transform-domain rec... more This paper addresses the selectivity problem, for the ultra-wide band (UWB), transform-domain receiver loss of orthogonality. A novel selective time-domain direct-sequence front-end for transform-domain ultra-wideband (UWB) wireless local area network (WLAN) receiver is proposed. The architecture comprises a multi-block, linear, dynamic feedback low-noise amplifier (LNA), quadrature mixer, and baseband filter. The dynamic feedback with inductive output load reduces the LNA to a simple second-order filter, with zero at the origin, while improving the conversion gain (CG) and noise figure (NF). Thus, the CG is further maximized when limiting the two poles within the 5-6 GHz frequency band. The mixer, based on a merged quadrature topology, employs single-peak notch network, with benefits to the NF and IIP3 of CG at 5.6 GHz. The front-end dissipates a 19.6 mW from 1.8 V supply voltage and achieves at 5.6 GHz 34.8 dB conversion gain, 6.42 dB NF, and 1-dB gain desensitization with -8 dBm interferer power at 7 GHz. Other simulation results are -2.35 dBm minimum IIIP3, and -35 dBc rejection at the UWB group #3.
Analog Integrated Circuits and Signal Processing, 2007
We report a novel low voltage fully differential class AB operational amplifier and a fully balan... more We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.
A method for linearity correction of a three-transistor wide dynamic range current-mode active pi... more A method for linearity correction of a three-transistor wide dynamic range current-mode active pixel sensor is proposed. The pixel uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a liner-logarithmic response. One of the non-linearity contributions is the effect caused by the `on' resistance of the select transistor. To eliminate this effect, we apply a linearization function that can be performed in the digital domain. This paper discusses the sensor architecture, the pixel's design and its operation. Experimental results of the current response before and after linearization are presented. The pixel was implemented in the AMS CMOS 0.35μm process from Austrian Microsystem. The pixel size is 12×12 μm, with a fill factor of 37%.
The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparat... more The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode ...
Analog Integrated Circuits and Signal Processing, 2004
We present in this paper an overview of circuit techniques dedicated to design reliable low-volta... more We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-of-the-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.
This paper presents the design and characterization of a sample-and-hold circuit based on a novel... more This paper presents the design and characterization of a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced, resulting in improved sample-and-hold accuracy. Experimental results in a 0.18 μm digital CMOS process show that a resolution greater than 10 bits can be obtained with a 1.0 V supply voltage. Circuit operation is also possible for supply voltages close to the transistor threshold (e.g., 0.65 V).
This paper addresses the selectivity problem, for the ultra-wide band (UWB), transform-domain rec... more This paper addresses the selectivity problem, for the ultra-wide band (UWB), transform-domain receiver loss of orthogonality. A novel selective time-domain direct-sequence front-end for transform-domain ultra-wideband (UWB) wireless local area network (WLAN) receiver is proposed. The architecture comprises a multi-block, linear, dynamic feedback low-noise amplifier (LNA), quadrature mixer, and baseband filter. The dynamic feedback with inductive output load reduces the LNA to a simple second-order filter, with zero at the origin, while improving the conversion gain (CG) and noise figure (NF). Thus, the CG is further maximized when limiting the two poles within the 5-6 GHz frequency band. The mixer, based on a merged quadrature topology, employs single-peak notch network, with benefits to the NF and IIP3 of CG at 5.6 GHz. The front-end dissipates a 19.6 mW from 1.8 V supply voltage and achieves at 5.6 GHz 34.8 dB conversion gain, 6.42 dB NF, and 1-dB gain desensitization with -8 dBm interferer power at 7 GHz. Other simulation results are -2.35 dBm minimum IIIP3, and -35 dBc rejection at the UWB group #3.
Analog Integrated Circuits and Signal Processing, 2007
We report a novel low voltage fully differential class AB operational amplifier and a fully balan... more We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.
A method for linearity correction of a three-transistor wide dynamic range current-mode active pi... more A method for linearity correction of a three-transistor wide dynamic range current-mode active pixel sensor is proposed. The pixel uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a liner-logarithmic response. One of the non-linearity contributions is the effect caused by the `on' resistance of the select transistor. To eliminate this effect, we apply a linearization function that can be performed in the digital domain. This paper discusses the sensor architecture, the pixel's design and its operation. Experimental results of the current response before and after linearization are presented. The pixel was implemented in the AMS CMOS 0.35μm process from Austrian Microsystem. The pixel size is 12×12 μm, with a fill factor of 37%.
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