Article

An iterative division algorithm for FPGAs

Authors:

Jianhua Liu,

Michael Chang, and

Chung-Kuan ChengAuthors Info & Claims

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

Pages 83 - 89

https://doi.org/10.1145/1117201.1117213

Published: 22 February 2006 Publication History

Get Access

Abstract

Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, we propose a hybrid division algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms. The proposed algorithm boosts very-high radix division efficiently. The algorithm is multiplicative, and feasible for the modern FPGA devices with build-in multipliers. The algorithm is implemented in Altera StratixII FPGA devices and compared with the division IP core generated by MegaWizard. The result shows that the PST algorithm has higher clock frequency, lower execution time and also lower power consumption.

References

[1]

Robertson J, "A New Class of Digital Division Methods", IRE Trans. on Electronic Computers, vol. 7, 1958, pp. 218--222.

Crossref

Google Scholar

[2]

Tocher T, "Techniques of Multiplication and Division for Automatic Binary Computers", Quarterly J. Mech. App. Math., vol. 2, pt. 3, 1958, pp. 364--384.

Crossref

Google Scholar

[3]

Coe T, Tang P, "It takes six ones to reach a flaw {Pentium processor}", Computer Arithmetic, 1995., Proceedings of the 12th Symposium on 19-21 July 1995 Page(s):140--146.

Digital Library

Google Scholar

[4]

Svoboda A, "An Algorithm for Division", Information Processing Machines, vol. 9, 1963, pp. 183--190.

Google Scholar

[5]

Tung C, "A Division Algorithm for Signed-Digit Arithmetic", IEEE Trans. on Computers, vol.17, 1968, pp. 887--889.

Digital Library

Google Scholar

[6]

Oberman S, Flynn M, "Division Algorithms and Implementations", IEEE Trans. on Computers, vol. 46, NO. 8, 1997, pp. 833--854.

Digital Library

Google Scholar

[7]

Goldschmidt R, "Applications of Division by Convergence", MS thesis, Dept. of Electrical Eng., Massachusetts Inst. of Technology, Cambridge, Mass., June 1964.

Google Scholar

[8]

Hung P, Fahmy H, Mencer O, Flynn M, "Fast Division Algorithm with a Small Lookup Table", Conference Record of the 33rd Asilomar conference on Signals, Systems, and Computers, IEEE. Part vol. 2, 1999, pp. 1465--1468.

Google Scholar

[9]

Markstein P, "Computation of Elementary Functions on the IBM RISC System/6000 Processor", IBM J. Research and Development, vol. 34, no. 1, pp.111--119, Jan. 1990.

Digital Library

Google Scholar

[10]

Oberman S, "Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor", Proc. 14th IEEE Symp. Computer Arithmetic, I. Koren and P. Kornerup, eds., pp. 106--115, Apr. 1999.

Digital Library

Google Scholar

[11]

Ibrahem AA, Elsimary HA, Salama AE, "FPGA implementation of fast radix 4 division algorithm", 4th IEEE International Workshop on System-on-Chip for Real-Time Applications. IEEE Comput. Soc. 2004, pp.69--72. Los Alamitos, CA, USA.

Digital Library

Google Scholar

[12]

Sutter G, Bioul G, Deschamps J-P, "Comparative study of SRT-dividers in FPGA", Field-Programmable Logic and Applications. 14th International Conference, FPL 2004. Proceedings (Lecture Notes in Comput. Sci. Vol.3203). Springer-Verlag. 2004, pp.209--20. Berlin, Germany.

Google Scholar

[13]

Altera Documentation Group, "Stratix II Device Handbook"', Altera Corporation, July 2005.

Google Scholar

Cited By

View all

Patankar UFlores MKoel A(2023)Novel data dependent divider circuit block implementation for complex division and area critical applicationsScientific Reports10.1038/s41598-023-28343-313:1Online publication date: 21-Feb-2023
https://doi.org/10.1038/s41598-023-28343-3
Patankar UKoel APatankar SFlores M(2021)Area Efficient Hexadecimal Divider Circuit Implementation Based on USP-Awadhoot Division Algorithm2021 IEEE International Conference on Engineering, Technology and Innovation (ICE/ITMC)10.1109/ICE/ITMC52061.2021.9570263(1-8)Online publication date: 21-Jun-2021
https://doi.org/10.1109/ICE/ITMC52061.2021.9570263
Patankar UKoel A(2021)Review of Basic Classes of Dividers Based on Division AlgorithmIEEE Access10.1109/ACCESS.2021.30557359(23035-23069)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3055735
Show More Cited By

Index Terms

An iterative division algorithm for FPGAs
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits

Recommendations

Pipelining of double precision floating point division and square root operations
ACM-SE 44: Proceedings of the 44th annual Southeast regional conference

Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require ...
Read More
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division

A hardware architecture for quadruple precision floating point division arithmetic with multi-precision support is presented. Division is an important yet far more complex arithmetic operation than addition and multiplication, which demands significant ...
Read More
Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs
FPGAworld '09: Proceedings of the 6th FPGAworld Conference

Matrix multiplication is most often involved in graphics, image processing, digital signal processing, robotics and control engineering applications. In this paper we compared and analyzed the power and energy consumption in three different designs, ...
Read More

Comments

Information & Contributors

Information

Published In

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

248 pages

ISBN:1595932925

DOI:10.1145/1117201

General Chair:
Steve Wilton
University of British Columbia, Canada
,
Program Chair:
André DeHon
California Institute of Technology, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

FPGA06

Sponsor:

FPGA06: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2006

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
1,295
Total Downloads

Downloads (Last 12 months)11
Downloads (Last 6 weeks)0

Other Metrics

View Author Metrics

Citations

Cited By

View all

Patankar UFlores MKoel A(2023)Novel data dependent divider circuit block implementation for complex division and area critical applicationsScientific Reports10.1038/s41598-023-28343-313:1Online publication date: 21-Feb-2023
https://doi.org/10.1038/s41598-023-28343-3
Patankar UKoel APatankar SFlores M(2021)Area Efficient Hexadecimal Divider Circuit Implementation Based on USP-Awadhoot Division Algorithm2021 IEEE International Conference on Engineering, Technology and Innovation (ICE/ITMC)10.1109/ICE/ITMC52061.2021.9570263(1-8)Online publication date: 21-Jun-2021
https://doi.org/10.1109/ICE/ITMC52061.2021.9570263
Patankar UKoel A(2021)Review of Basic Classes of Dividers Based on Division AlgorithmIEEE Access10.1109/ACCESS.2021.30557359(23035-23069)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3055735
Muller JBrunie Nde Dinechin FJeannerod CJoldes MLefèvre VMelquiond GRevol NTorres SMuller JBrunie Nde Dinechin FJeannerod CJoldes MLefèvre VMelquiond GRevol NTorres S(2018)Hardware Implementation of Floating-Point ArithmeticHandbook of Floating-Point Arithmetic10.1007/978-3-319-76526-6_8(267-320)Online publication date: 3-May-2018
https://doi.org/10.1007/978-3-319-76526-6_8
Ndu GNavaridas JLuján MMcIntosh-Smith SBergen B(2015)CHOProceedings of the 3rd International Workshop on OpenCL10.1145/2791321.2791331(1-10)Online publication date: 12-May-2015
https://dl.acm.org/doi/10.1145/2791321.2791331
de Dinechin FPasca BCret OTudoran R(2008)An FPGA-specific approach to floating-point accumulation and sum-of-products2008 International Conference on Field-Programmable Technology10.1109/FPT.2008.4762363(33-40)Online publication date: Dec-2008
https://doi.org/10.1109/FPT.2008.4762363

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Pipelining of double precision floating point division and square root operations

An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division

Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Pipelining of double precision floating point division and square root operations

An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division

Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations