Testing embedded RAM modules in SRAM-based FPGAs

This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. A diagnosis scheme capable of locating the faulty RAM cell and the CLB in which it is located is also developed.Considerable research in the area of testing the LUT/RAM modules for SRAM based FPGAs has been done earlier. However, the solutions proposed are not optimal as they require N test configurations to test an N input RAM module. One such solution proposes a Pseudo Shift Register (PSR) interconnection scheme using the shifted MATS++ algorithm. It is possible to test all the RAM modules in an FPGA in one test configuration using this approach. However, although this scheme can detect the faulty cell in the RAM modules under test, it does not have the capability of locating the faulty CLB in which the RAM modules are located. In other words, the scheme assumes that the faulty CLB is known. This drawback is eliminated in the scheme presented in this paper by using a unique interconnection of CLBs in the form of a chain. In addition, the proposed interconnection scheme also reduces the testing time by approximately half as compared to the time taken by earlier schemes. The FPGA is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim.