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Dynamic binary control-flow errors detection

Published: 01 December 2005 Publication History
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  • Abstract

    Shrinking microprocessor feature size will increase the soft-error rates to unacceptable levels in the near future. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a less expensive and more flexible alternative. This paper presents a control-flow error classification and proposes new software based control-flow error detection techniques. The new techniques are better than the previous ones in the sense that they detect errors in all the branch-error categories. We also compare the performance of our new techniques with that of the previous ones using our dynamic binary translator.

    References

    [1]
    {Bau02} R. Baumann, Soft Errors in Commercial Semiconductor Technology: Overview and Scaling Trends, IEEE 2002 Reliability Physics Symp. Tutorial Notes, Reliability Fundamentals, IEEE Press, 2002, pp. 121--01. 1-121-01.14.
    [2]
    {AYI+03} H. Ando et al., A 1.3GHz Fifth Generation SPARC64 Microprocessors, Proc. IEEE International Solid-State Circuits Conference. (ISSCC 03), IEEE Press, 2003, pp. 246--247.
    [3]
    {VHM03} R. Venkatasubramanian, J. P. Hayes, and B. T. Murray. Low-cost on-line fault detection using control flow assertions. 9th IEEE On-Line Testing Symposium, pp. 137--143, July 2003.
    [4]
    {Con03} C. Constantinescu. Trends and challenges in VLSI circuit reliability. IEEE Micro, vol. 23, pp. 14--19, Jul.-Aug. 2003.
    [5]
    {SKK+02} P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the 2002 International Conference on Dependable Systems and Networks, pages 389--399, June 2002.
    [6]
    {SM90} N. R. Saxena, E. J. McCluskey. Control-flow Checking Using Watchdog Assists and Extended-Precision Checksums. IEEE Transactions on Computers, Vol. 39, No. 4, Apr. 1990, pp. 554--559.
    [7]
    {MLS91} T. Michel, R. Leveugle and G. Saucier. A New Approach to Control-flow Checking without Program Modification. Proc. FTCS-21, 1991, pp. 334--341.
    [8]
    {Nam83} M. Namjoo. CERBERUS-16: An Architecture for a General Purpose Watchdog Processor. Proc. Symposium on Fault-Tolerant Computing. 1983, pp.216--219.
    [9]
    {ORT+96} T. J. O'Gorman, J. M. Ross, A. H. Taber, J. F. Ziegler, H. P. Muhlfeld, I. C. J. Montrose, H. W. Curtis, and J. L. Walsh. Field testing for cosmic ray soft errors in semiconductor memories. In IBM Journal of Research and Development, pages 41--49, January 1996.
    [10]
    {ANKA99} Z. Alkhalifa, V. S. S. Nair, N. Krishnamurthy, and J. A. Abraham, Design and evaluation of system-level checks for on-line control-flow error detection, IEEE Trans. Parallel Distrib. Syst., vol. 10, pp. 627--641, June 1999.
    [11]
    {OSM02} N. Oh, P. P. Shirvani, and E. J. McCluskey. Control-flow checking by software signatures. IEEE Transactions on Reliability, vo. 51, No 2, pp. 111--122, March 2002.
    [12]
    {RCV+05b} G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. I. August. SWIFT: Software Implemented Fault Tolerance. Proceedings of the Third International Symposium on Code Generation and Optimization, March 2005.
    [13]
    {IA-32} IA-32 Intel@ Architecture Software Developer's Manual
    [14]
    {EM64T} Intel@ Extended Memory 64 Technology Software Developer's Guide

    Cited By

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    • (2015)Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor PipelineIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229757323:1(131-141)Online publication date: 1-Jan-2015
    • (2014)Interactive hybrid Control-flow checking method2014 International Conference on Applied Electronics10.1109/AE.2014.7011673(79-82)Online publication date: Sep-2014
    • (2013)Leveraging speculative architectures for runtime program validationACM Transactions on Embedded Computing Systems10.1145/251245613:1(1-18)Online publication date: 5-Sep-2013
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    Published In

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 33, Issue 5
    Special issue on the 2005 workshop on binary instrumentation and application
    December 2005
    93 pages
    ISSN:0163-5964
    DOI:10.1145/1127577
    Issue’s Table of Contents

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 December 2005
    Published in SIGARCH Volume 33, Issue 5

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    View all
    • (2015)Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor PipelineIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.229757323:1(131-141)Online publication date: 1-Jan-2015
    • (2014)Interactive hybrid Control-flow checking method2014 International Conference on Applied Electronics10.1109/AE.2014.7011673(79-82)Online publication date: Sep-2014
    • (2013)Leveraging speculative architectures for runtime program validationACM Transactions on Embedded Computing Systems10.1145/251245613:1(1-18)Online publication date: 5-Sep-2013
    • (2012)Low-cost control flow error protection by exploiting available redundancies in the pipeline17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164941(175-180)Online publication date: Jan-2012
    • (2011)Security in Embedded SystemsIntroduction to Hardware Security and Trust10.1007/978-1-4419-8080-9_10(231-261)Online publication date: 8-Aug-2011
    • (2010)Modeling and Evaluation of Control Flow Vulnerability in the Embedded SystemProceedings of the 2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems10.1109/MASCOTS.2010.71(430-433)Online publication date: 17-Aug-2010
    • (2009)Tolerating Radiation-Induced Transient Faults in Modern ProcessorsInternational Journal of Parallel Programming10.1007/s10766-009-0114-938:2(85-116)Online publication date: 24-Jul-2009
    • (2008)Leveraging speculative architectures for run-time program validation2008 IEEE International Conference on Computer Design10.1109/ICCD.2008.4751907(498-505)Online publication date: Oct-2008
    • (2008)Using likely program invariants to detect hardware errors2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)10.1109/DSN.2008.4630072(70-79)Online publication date: Jun-2008
    • (2008)FEDCProceedings of the 2008 Third International Conference on Availability, Reliability and Security10.1109/ARES.2008.199(33-38)Online publication date: 4-Mar-2008

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