research-article

Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Authors:

Yeong-Jar ChangAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 535 - 538

https://doi.org/10.1145/1687399.1687500

Published: 02 November 2009 Publication History

Get Access

Abstract

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.

References

[1]

C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," in Proc. of IEEE/ACM Design Automation Conference., pp. 479--484. 1999.

Digital Library

Google Scholar

[2]

J. Cong, C. Koh, and K. Leung, "Simultaneous buffer and wire sizing for performance and power optimization," in Proc. of Int. Symposium on Low Power Electron. Design, pp. 271--276, 1996.

Digital Library

Google Scholar

[3]

C. C. N. Chu and D. F. Wong, "An efficient and optimal algorithm for simultaneous buffer and wire sizing," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1297--1304, Sept. 1999.

Digital Library

Google Scholar

[4]

Shiyan Hu, Jiang Hu, "Unified adaptivity optimization of clock and logic signals," in Proc. of the IEEE/ACM international conference on Computer-aided design, November 05--08, 2007.

Digital Library

Google Scholar

[5]

N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, "A multigigahertz clocking scheme for Pentium 4 Microprocessor," IEEE J. Solid-State Circuits, vol. 36, pp. 1647--1653, Nov. 2001.

Crossref

Google Scholar

[6]

Vishal Khandelwal and Ankur Srivastava, "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation," in Proc. of Int. Symposium on Physical design, pp. 11--18, 2007.

Digital Library

Google Scholar

[7]

I.-M Liu, T.-L Chou, A. Aziz, and D. F. Wong, "Zero-skew clock tree construction by simultaneous routing, wire sizing, and buffer insertion," in Proc. of Int. Symposium on Physical Design, pp. 33--38, 2000.

Digital Library

Google Scholar

[8]

T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 44--49, 1996.

Digital Library

Google Scholar

[9]

Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen, "Zero skew clock tree optimization with buffer insertion/sizing and wire sizing," IEEE Transactions on CAD, Vol. 23, No. 4, Jun. 2004.

Digital Library

Google Scholar

[10]

J.-L. Tsai, L. Zhang, C. Chen, "Statistical timing analysis driven post-silicon-tunable clock-tree synthesis," in Proc. of Int. Conf. on Computer-Aided Design, pp. 575--581, Nov. 2005.

Digital Library

Google Scholar

[11]

E. Takahashi, Y. Kasai, M. Murakawa, and T. Higuchi, "A postsilicon clock timing adjustment using genetic algorithms," in Digest of technical papers of the symp. on VLSI circuits, pages 13--16, 2003.

Google Scholar

[12]

Kai Wang; Ran, Y.; Hailin Jiang; Marek-Sadowska, M., "General skew constrained clock network sizing based on sequential linear programming," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 5, pp. 773--782, May 2005

Digital Library

Google Scholar

Cited By

View all

Cheng WYeh ZKao HHuang S(2023)Cross-Mesh Clock Network SynthesisElectronics10.3390/electronics1216341012:16(3410)Online publication date: 11-Aug-2023
https://doi.org/10.3390/electronics12163410
Bairamkulov RJabbari TFriedman E(2022)QuCTS—Single-Flux Quantum Clock Tree SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312314141:10(3346-3358)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3123141
Bairamkulov RFriedman EBairamkulov RFriedman E(2022)QuCTS – single flux Quantum Clock Tree SynthesisGraphs in VLSI10.1007/978-3-031-11047-4_11(281-300)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_11
Show More Cited By

Index Terms

Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

Recommendations

Clock skew minimization in multi-voltage mode designs using adjustable delay buffers

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In ...
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

It is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers(ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode ...
Useful-skew clock optimization for multi-power mode designs
ICCAD '11: Proceedings of the International Conference on Computer-Aided Design

Instead of minimizing clock skew, skew can be useful to improve circuit performance. However, it is difficult to apply useful skew to a design with complicated power modes. With only one clock tree, useful skew in one power mode may be harmful in ...

Comments

Information & Contributors

Information

Published In

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ICCAD '09

Sponsor:

SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
169
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 28 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Cheng WYeh ZKao HHuang S(2023)Cross-Mesh Clock Network SynthesisElectronics10.3390/electronics1216341012:16(3410)Online publication date: 11-Aug-2023
https://doi.org/10.3390/electronics12163410
Bairamkulov RJabbari TFriedman E(2022)QuCTS—Single-Flux Quantum Clock Tree SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312314141:10(3346-3358)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3123141
Bairamkulov RFriedman EBairamkulov RFriedman E(2022)QuCTS – single flux Quantum Clock Tree SynthesisGraphs in VLSI10.1007/978-3-031-11047-4_11(281-300)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_11
Joo DKim T(2019)A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228869833:3(423-436)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2013.2288698
Ravi STrehan SJain MKittur H(2019)High Performance Clock Path elements for Clock Skew reduction2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT)10.1109/ICICICT46008.2019.8993375(1663-1670)Online publication date: Jul-2019
https://doi.org/10.1109/ICICICT46008.2019.8993375
Chang CHuang S(2018)A Mechanism for Adjustable-Delay-Buffer Selection to Dynamically Control Clock Skew2018 International Conference on System Science and Engineering (ICSSE)10.1109/ICSSE.2018.8520198(1-4)Online publication date: Jun-2018
https://doi.org/10.1109/ICSSE.2018.8520198
Kim JKim T(2017)Adjustable Delay Buffer Allocation under Useful Clock Skew SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721336:4(641-654)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597213
Lee YHuang S(2017)On-chip-variation-aware power-mode-aware buffer synthesis for clock skew minimization2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)10.1109/EDSSC.2017.8126535(1-2)Online publication date: Oct-2017
https://doi.org/10.1109/EDSSC.2017.8126535
Chou CYeh HHuang SNieh YChang SChang Y(2016)Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.243799424:3(1189-1192)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2437994
Kim JJoo DKim T(2016)Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modesIntegration, the VLSI Journal10.1016/j.vlsi.2015.08.00552:C(91-101)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.005
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Clock skew minimization in multi-voltage mode designs using adjustable delay buffers

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Useful-skew clock optimization for multi-power mode designs

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations