research-article

Distributed DVFS using rationally-related frequencies and discrete voltage levels

Authors:

Jean-Michel Chabloz,

Ahmed HemaniAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 247 - 252

https://doi.org/10.1145/1840845.1840897

Published: 18 August 2010 Publication History

Abstract

We have defined a flexible latency-insensitive design style called Globally Ratiochronous Locally Synchronous (GRLS), based on quantized voltage levels and rationally-related clock frequencies. In this paper we present the infrastructure necessary to enable Distributed DVFS in such a system and analyze its overheads, quantitatively showing how, with minimal overheads, we obtain energy benefits that are close to those of a totally ideal GALS approach. The benefits that we show, coupled with the complexity and performance benefits of GRLS, which we briefly analyze, show how this approach is a strong competitor to GALS.

References

[1]

P. Teehan et al., "A Survey and Taxonomy of GALS Design Styles," in Design & Test of Computers, 2007

Digital Library

[2]

A. P. Niranjan and P. Wiscombe, "Islands of Synchronicity, a Design Methodology for SoC Design," DATE 2004

Digital Library

[3]

A. Hemani et al., "Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style," DAC 1999

Digital Library

[4]

S. Herbert and D. Marculescu, "Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors," ISLPED 2007

Digital Library

[5]

M. R. Greenstreet, "Implementing a STARI chip," ICCD 1995

Digital Library

[6]

D. M. Chapiro, "Globally Asynchronous Locally Synchronous Systems," PhD thesis, Stanford University, Oct. 1984

Digital Library

[7]

J. M. Chabloz and A. Hemani, "A Flexible Interface for Rationally-Related Frequencies," ICCD 2009

Digital Library

[8]

V. Gutnik and A. Chandrakasan, "Embedded Power Supply for Low-Power DSP," in IEEE Trans. on VLSI Systems, 1997

Digital Library

[9]

L. F. G. Sarmenta et al., "Rational Clocking," ICCD 1995

[10]

A. W. Yin et al., "Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks," DSD 2009

Digital Library

[11]

W. H. Cheng and B. M. Baas, "Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages," ISCAS 2008

[12]

L. H. Chandrasena et al., "An Energy Efficient Rate Selection Algorithm for Voltage Quantized Dynamic Voltage Scaling," ISSS 2001

Digital Library

[13]

M. Putic et al., "Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design," ICCD 2009

Digital Library

[14]

E. Beigne et al. "Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC," NOCS 2008

Digital Library

[15]

K. Y. Yun and R. P. Donohue, "Pausible Clocking: a First Step Toward Heterogeneous Systems," ICCD 1996

Digital Library

[16]

T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. of solid-state circuits, 1990

[17]

Roy H. Liu, "How to Create Designs with Dynamic/Adaptive Voltage Scaling," ARM D. C.

Cited By

Chong AHong A(2022)A Simplified Flop MTBF Extraction Methodology2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)10.1109/ICCSS55260.2022.9802161(52-56)Online publication date: 13-May-2022
https://doi.org/10.1109/ICCSS55260.2022.9802161
Torng CPan POu YTan CBatten C(2021)Ultra-Elastic CGRAs for Irregular Loop Specialization2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00042(412-425)Online publication date: Mar-2021
https://doi.org/10.1109/HPCA51647.2021.00042
Zhuo CLuo SGan HHu JShi Z(2019)Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2917844(1-1)Online publication date: 2019
https://doi.org/10.1109/TCAD.2019.2917844
Show More Cited By

Index Terms

Distributed DVFS using rationally-related frequencies and discrete voltage levels
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

A GALS Network-on-Chip based on rationally-related frequencies
ICCD '11: Proceedings of the 2011 IEEE 29th International Conference on Computer Design

GALS Networks-on-Chip (NoCs) in which the frequency of every switch can be set independently would enable per-node DVFS without requiring asynchronous switch design. However, traditional GALS interfaces introduce high latency penalties and are therefore ...
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links
VLSID '12: Proceedings of the 2012 25th International Conference on VLSI Design

In this paper we introduce a novel interface for Globally-Asynchronous, Locally-Synchronous systems which does not use any form of handshake to cross the gap between the clock domains. In particular, links in which the Receiver runs faster than the ...
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. For power reduction, voltage and frequency scaling techniques have been applied successfully to CPUs ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISLPED'10

Sponsor:

SIGDA

ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Upcoming Conference

ISLPED '24

Sponsor:
sigda

ACM/IEEE International Symposium on Low Power Electronics and Design

August 5 - 7, 2024

Newport Beach , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

23
Total Citations
View Citations
263
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chong AHong A(2022)A Simplified Flop MTBF Extraction Methodology2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)10.1109/ICCSS55260.2022.9802161(52-56)Online publication date: 13-May-2022
https://doi.org/10.1109/ICCSS55260.2022.9802161
Torng CPan POu YTan CBatten C(2021)Ultra-Elastic CGRAs for Irregular Loop Specialization2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00042(412-425)Online publication date: Mar-2021
https://doi.org/10.1109/HPCA51647.2021.00042
Zhuo CLuo SGan HHu JShi Z(2019)Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2917844(1-1)Online publication date: 2019
https://doi.org/10.1109/TCAD.2019.2917844
Luo SZhuo CGan H(2018)Noise-aware DVFS transition sequence optimization for battery-powered IoT devicesProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196080(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196080
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_28-2(1-46)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_28-2
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_28(867-913)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_28
Hemani AFarahini NJafri SSohofi HLi SPaul K(2017)The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable FabricThe Dark Side of Silicon10.1007/978-3-319-31596-6_3(47-94)Online publication date: 1-Jan-2017
https://doi.org/10.1007/978-3-319-31596-6_3
Zhang CWang JZhang MWu X(2016)A New DVFS Algorithm Design for Multi-core Processor ChipComputer Engineering and Technology10.1007/978-981-10-3159-5_5(40-51)Online publication date: 9-Dec-2016
https://doi.org/10.1007/978-981-10-3159-5_5
Jafri SOzbag OFarahini NPaul KHemani APlosila JTenhunen H(2015)Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAsACM Journal on Emerging Technologies in Computing Systems10.1145/270025011:4(1-29)Online publication date: 27-Apr-2015
https://dl.acm.org/doi/10.1145/2700250
Mekie J(2014)Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked SystemsProceedings of the 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2014.13(37-44)Online publication date: 12-May-2014
https://dl.acm.org/doi/10.1109/ASYNC.2014.13
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents