research-article

System integration of tightly-coupled processor arrays using reconfigurable buffer structures

Authors:

Jürgen TeichAuthors Info & Claims

CF '13: Proceedings of the ACM International Conference on Computing Frontiers

Article No.: 2, Pages 1 - 4

https://doi.org/10.1145/2482767.2482770

Published: 14 May 2013 Publication History

Get Access

Abstract

As data locality is a key factor for the acceleration of loop programs on processor arrays, we propose a buffer architecture that can be configured at run-time to select between different schemes for memory access. In addition to traditional address-based memory banks, the buffer architecture can deliver data in a streaming manner to the processing elements of the array, which supports dense and sparse stencil operations. Moreover, to minimize data transfers to the buffers, the design contains an interlinked mode, which is especially targeted at 2-D kernel computations. The buffers can be used individually to achieve high data throughput by utilizing a maximum number of I/O channels to the array, or concatenated to provide higher storage capacity at a reduced amount of I/O channels.

References

[1]

V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt. PACT XPP -- a self-reconfigurable data processing architecture. The Journal of Supercomputing, 26(2):167--184, 2003.

Digital Library

Google Scholar

[2]

F. Bouwens, M. Berekovic, B. De Sutter, and G. Gaydadjiev. Architecture enhancements for the ADRES coarse-grained reconfigurable array. In Proceedings of the 3rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), pages 66--81, Gothenburg, Sweden, 2008. Springer.

Digital Library

Google Scholar

[3]

N. Goulding-Hotta, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, V. Bhatt, J. Babb, S. Swanson, and M. Taylor. The GreenDroid mobile application processor: An architecture for silicon's dark future. IEEE Micro, 31(2):86--95, March--April 2011.

Digital Library

Google Scholar

[4]

Z. Guo, B. Buyukkurt, and W. Najjar. Input data reuse in compiling window operations onto reconfigurable hardware. In Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), pages 249--256. ACM, 2004.

Digital Library

Google Scholar

[5]

F. Hannig, H. Dutta, and J. Teich. Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: Architectural parameters and methodology. International Journal of Embedded Systems, 2(1/2):114--127, 2006.

Crossref

Google Scholar

[6]

F. Hannig, H. Ruckdeschel, H. Dutta, and J. Teich. PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications. In Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), volume 4943 of Lecture Notes in Computer Science (LNCS), pages 287--293. Springer, 2008.

Digital Library

Google Scholar

[7]

D. Kissler, F. Hannig, A. Kupriyanov, and J. Teich. A highly parameterizable parallel processor array architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pages 105--112. IEEE, 2006.

Crossref

Google Scholar

[8]

D. Kissler, A. Strawetz, F. Hannig, and J. Teich. Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures. Journal of Low Power Electronics, 5(1):96--105, 2009.

Crossref

Google Scholar

[9]

V. Lari, A. Narovlyanskyy, F. Hannig, and J. Teich. Decentralized dynamic resource management support for massively parallel processor arrays. In Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pages 87--94. IEEE Computer Society, 2011.

Digital Library

Google Scholar

Cited By

View all

Brand MWitterauf MSousa ÉTanase AHannig FTeich J(2019)*‐Predictable MPSoC execution of real‐time control applications using invasive computingConcurrency and Computation: Practice and Experience10.1002/cpe.514933:14Online publication date: 3-Feb-2019
https://doi.org/10.1002/cpe.5149
(2018)Techniques for on-demand structural redundancy for massively parallel processor arraysJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.10.00461:10(615-627)Online publication date: 30-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2015.10.004
Teich JTanase AHannig F(2018)Symbolic Mapping of Loop Programs onto Processor ArraysJournal of Signal Processing Systems10.1007/s11265-014-0905-077:1-2(31-59)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-014-0905-0
Show More Cited By

Index Terms

System integration of tightly-coupled processor arrays using reconfigurable buffer structures
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
    2. Parallel architectures
      1. Systolic arrays

Recommendations

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance
ICPPW '09: Proceedings of the 2009 International Conference on Parallel Processing Workshops

This paper studies the loosely integration of application accelerators consisting of an array of tightly-coupled lightweight reconfigurable processors into a system-on-a-chip. In order to explore a multitude of design variations a C++ simulation model ...
Reconfigurable Processing With Field Programmable Gate Arrays
ASAP '96: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors

In-system-programmable, SRAM-based Field Programmable Gate Arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting ...
Compact Code Generation for Tightly-Coupled Processor Arrays

In this paper, we consider programmable tightly-coupled processor arrays consisting of interconnected small light-weight VLIW cores, which can exploit both loop-level parallelism and instruction-level parallelism. These arrays are well suited for ...

Comments

Information & Contributors

Information

Published In

CF '13: Proceedings of the ACM International Conference on Computing Frontiers

May 2013

302 pages

ISBN:9781450320535

DOI:10.1145/2482767

General Chairs:
Hubertus Franke
IBM, US
,
Alexander Heinecke
TU München, DE
,
Program Chairs:
Krishna Palem
Rice University, US and Nanyang Technological University, SG
,
Eli Upfal
Brown University

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 14 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Deutsche Forschungsgemeinschaft

Conference

CF'13

Sponsor:

SIGMICRO

CF'13: Computing Frontiers Conference

May 14 - 16, 2013

Ischia, Italy

Acceptance Rates

CF '13 Paper Acceptance Rate 26 of 49 submissions, 53%;

Overall Acceptance Rate 273 of 785 submissions, 35%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
191
Total Downloads

Downloads (Last 12 months)11
Downloads (Last 6 weeks)1

Reflects downloads up to 10 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Brand MWitterauf MSousa ÉTanase AHannig FTeich J(2019)*‐Predictable MPSoC execution of real‐time control applications using invasive computingConcurrency and Computation: Practice and Experience10.1002/cpe.514933:14Online publication date: 3-Feb-2019
https://doi.org/10.1002/cpe.5149
(2018)Techniques for on-demand structural redundancy for massively parallel processor arraysJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.10.00461:10(615-627)Online publication date: 30-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2015.10.004
Teich JTanase AHannig F(2018)Symbolic Mapping of Loop Programs onto Processor ArraysJournal of Signal Processing Systems10.1007/s11265-014-0905-077:1-2(31-59)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-014-0905-0
Sousa ÉHannig FTeich J(2018)Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable ArraysSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_18(218-229)Online publication date: 17-Apr-2018
https://doi.org/10.1007/978-3-319-90023-0_18
Tanase AHannig FTeich JTanase AHannig FTeich J(2018)On-Demand Fault-Tolerant Loop ProcessingSymbolic Parallelization of Nested Loop Programs10.1007/978-3-319-73909-0_5(123-153)Online publication date: 23-Feb-2018
https://doi.org/10.1007/978-3-319-73909-0_5
Tanase AHannig FTeich JTanase AHannig FTeich J(2018)Fundamentals and Compiler FrameworkSymbolic Parallelization of Nested Loop Programs10.1007/978-3-319-73909-0_2(9-36)Online publication date: 23-Feb-2018
https://doi.org/10.1007/978-3-319-73909-0_2
Sousa ETanase AHannig FTeich J(2017)A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2017.8279768(1-8)Online publication date: Dec-2017
https://doi.org/10.1109/RECONFIG.2017.8279768
Lari VLARI V(2016)Invasive Tightly Coupled Processor ArraysInvasive Tightly Coupled Processor Arrays10.1007/978-981-10-1058-3_2(21-81)Online publication date: 9-Jul-2016
https://doi.org/10.1007/978-981-10-1058-3_2
Glocker EBoppu SChen QSchlichtmann UTeich JSchmitt-Landsiedel D(2014)Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)Advances in Radio Science10.5194/ars-12-103-201412(103-109)Online publication date: 10-Nov-2014
https://doi.org/10.5194/ars-12-103-2014
Paul JStechele WSousa ELari VHannig FTeich JKrohnert MAsfour T(2014)Self-adaptive harris corner detector on heterogeneous many-core processorProceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing10.1109/DASIP.2014.7115616(1-8)Online publication date: Oct-2014
https://doi.org/10.1109/DASIP.2014.7115616

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance

Reconfigurable Processing With Field Programmable Gate Arrays

Compact Code Generation for Tightly-Coupled Processor Arrays