research-article

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM

Authors:

Chun Jason Xue,

Qingfeng ZhugeAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 171, Pages 1 - 6

https://doi.org/10.1145/2897937.2898106

Published: 05 June 2016 Publication History

Abstract

Spin-transfer torque random access memory (STT-RAM) is considered as a promising candidate to replace SRAM as the next generation cache memory since it has better scalability and lower leakage power. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to further increase data density. However, a key drawback for MLC STT-RAM is that the magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step problem in state transitions. Two-step state transitions would significantly impact the lifetime of MLC STT-RAM due to the wasted flips in the soft domains. To solve the problem, this paper proposes a novel two-step state transition minimization (TSTM) scheme, to improve the lifetime of MLC STT-RAM when it is employed in cache design. The basic idea is by sacrificing certain cells as auxiliary flags, the two-step state transitions in STT-RAM can be well eliminated. Experimental results show that the proposed scheme can improve the lifetime of MLC STT-RAM to 318.5%.

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Cited By

Zhao WXu JWei XWu BWang CZhu WTong WFeng DLiu J(2023)A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316945842:1(122-135)Online publication date: Jan-2023
https://doi.org/10.1109/TCAD.2022.3169458
Hsieh JHou YChang T(2022)Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311263841:8(2753-2757)Online publication date: Aug-2022
https://doi.org/10.1109/TCAD.2021.3112638
Hsieh JLiu YLee HChang T(2021)TSE: Two-Step Elimination for MLC STT-RAM Last-Level CacheIEEE Transactions on Computers10.1109/TC.2020.301436170:9(1498-1510)Online publication date: 1-Sep-2021
https://doi.org/10.1109/TC.2020.3014361
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Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

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Association for Computing Machinery

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Publication History

Published: 05 June 2016

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Research-article

Funding Sources

Chongqing Research Program
National Natural Science Foundation of China
National 863 Programs
Fundamental Research Funds for the Central Universities

Conference

DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Zhao WXu JWei XWu BWang CZhu WTong WFeng DLiu J(2023)A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316945842:1(122-135)Online publication date: Jan-2023
https://doi.org/10.1109/TCAD.2022.3169458
Hsieh JHou YChang T(2022)Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311263841:8(2753-2757)Online publication date: Aug-2022
https://doi.org/10.1109/TCAD.2021.3112638
Hsieh JLiu YLee HChang T(2021)TSE: Two-Step Elimination for MLC STT-RAM Last-Level CacheIEEE Transactions on Computers10.1109/TC.2020.301436170:9(1498-1510)Online publication date: 1-Sep-2021
https://doi.org/10.1109/TC.2020.3014361
Huang YHsieh J(2021)Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache2021 IEEE 27th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA52859.2021.00009(11-20)Online publication date: Aug-2021
https://doi.org/10.1109/RTCSA52859.2021.00009
Jang W(2020)MLC STT-MRAM-Aware Memory Subsystem for Smart Image ApplicationsIEEE Transactions on Multimedia10.1109/TMM.2019.293034222:3(717-729)Online publication date: Mar-2020
https://doi.org/10.1109/TMM.2019.2930342
Li SHuang KHuang LZhu J(2019)LiwePMSACM Journal on Emerging Technologies in Computing Systems10.1145/332796315:3(1-24)Online publication date: 10-Jun-2019
https://dl.acm.org/doi/10.1145/3327963
Qureshi MKim HKim S(2019)A Restore-Free Mode for MLC STT-RAM CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.2899894(1-5)Online publication date: 2019
https://doi.org/10.1109/TVLSI.2019.2899894
Liang YChen TChang YChen SChen PShih W(2019)Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2019.8824899(1-6)Online publication date: Jul-2019
https://doi.org/10.1109/ISLPED.2019.8824899
Shen FHe YZhang JXu C(2019)Periodic learning-based region selection for energy-efficient MLC STT-RAM cacheThe Journal of Supercomputing10.1007/s11227-019-02846-1Online publication date: 8-Apr-2019
https://doi.org/10.1007/s11227-019-02846-1
Wang CChattopadhyay S(2018)LAWNProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196066(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196066
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