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10.1145/2947357acmconferencesBook PagePublication PagesslipConference Proceedingsconference-collections
SLIP '16: Proceedings of the 18th System Level Interconnect Prediction Workshop
ACM2016 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
SLIP '16: System Level Interconnect Prediction Workshop Austin TX USA 4 June 2016
ISBN:
978-1-4503-4430-2
Published:
04 June 2016
Sponsors:
SIGDA, IEEE CS

Reflects downloads up to 03 Oct 2024Bibliometrics
Abstract

No abstract available.

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research-article
A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects
Article No.: 1, Pages 1–8https://doi.org/10.1145/2947357.2947362

Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) ...

research-article
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits
Article No.: 2, Pages 1–6https://doi.org/10.1145/2947357.2947364

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing ...

research-article
Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links
Article No.: 3, Pages 1–7https://doi.org/10.1145/2947357.2947365

Hardware neuromorphic systems are challenged to achieve biologically realistic levels of interconnectivity. When building a physical implementation of a neural net, the properties of the media immediately impose limits on the number of interconnects and ...

research-article
Buffered Interconnects in 3D IC Layout Design
Article No.: 4, Pages 1–8https://doi.org/10.1145/2947357.2947366

A very important challenge in designing through-silicon via (TSV)-based 3D ICs is to accurately estimate, through all stages of the physical design, the interconnect delay which is strongly dependent on the layout of 3D IC. The earlier in the design ...

research-article
Topologically-Geometric Routing
Article No.: 5, Pages 1–6https://doi.org/10.1145/2947357.2947367

The paper introduces foundations of the "Flexible Routing Method" that belongs to the topologically-geometric type. It develops the idea to divide the routing problem on two separate successive stages: topological and geometrical. At the first stage it ...

research-article
Revisiting 3DIC Benefit with Multiple Tiers
Article No.: 6, Pages 1–8https://doi.org/10.1145/2947357.2947363

3DICs with multiple tiers are expected to achieve large benefits (e.g., in terms of power, area) as compared to conventional planar designs. However, few if any previous works study upper bounds on power and area benefits from 3DIC integration with ...

research-article
Public Access
Spin-Hall Assisted STT-RAM Design and Discussion
Article No.: 7, Pages 1–4https://doi.org/10.1145/2947357.2947360

In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large ...

research-article
A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip
Article No.: 8, Pages 1–8https://doi.org/10.1145/2947357.2947361

Long distance data communication over multi-hop wireline paths in conventional Networks-on-Chips (NoCs) cause high energy consumption and degradation in bandwidth. Wireless interconnects in the millimeter-wave band have emerged as an energy-efficient ...

Contributors
  • Drexel University

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Acceptance Rates

Overall Acceptance Rate 6 of 8 submissions, 75%
YearSubmittedAcceptedRate
SLIP '188675%
Overall8675%