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Using FPGA implementations for evaluation of internet retransmission-time-out predictors

Published: 31 August 2017 Publication History

Abstract

The congestion control avoidance of TCP (Transport Control Protocol), the most used protocol in Internet, is based on critical RTT (Round Trip Time) forecasting process. Currently, several delay predictors are proposed in literature; but practical implementations have not been yet evaluated. In this paper, a comparison of on-line predictors is presented. We used Altera Cyclone IV GX FPGA (Field-Programmable Gate Array) for evaluation; the criteria included performance time, power, and number of logic elements. For comparison purposes, we considered the most used predictor as reference and concluded which one is more suitable for implementation in next generation devices.

References

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      cover image ACM Other conferences
      ECBS '17: Proceedings of the Fifth European Conference on the Engineering of Computer-Based Systems
      August 2017
      177 pages
      ISBN:9781450348430
      DOI:10.1145/3123779
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 31 August 2017

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      Author Tags

      1. FPGA
      2. RTO (retransmission time-out)
      3. TCP/IP
      4. heavy tail

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