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Towards Efficient SpMV on Sunway Manycore Architectures

Published: 12 June 2018 Publication History
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  • Abstract

    Sparse Matrix-Vector Multiplication (SpMV) is an essential computation kernel for many data-analytic workloads running in both supercomputers and data centers. The intrinsic irregularity in SpMV is challenging to achieve high performance, especially when porting to new architectures. In this paper, we present our work on designing and implementing efficient SpMV algorithms on Sunway, a novel architecture with many unique features. To fully exploit the Sunway architecture, we have designed a dual-side multi-level partition mechanism on both sparse matrices and hardware resources to improve locality and parallelism. On one hand, we partition sparse matrices into blocks, tiles, and slices for different granularities. On the other hand, we partition cores in a Sunway processor into fleets, and further dedicate part of cores in a fleet as computation and I/O cores. Moreover, we have optimized the communication between partitions to further improve the performance. Our scheme is generally applicable to different SpMV formats and implementations. For evaluation, we have applied our techniques atop a popular SpMV format, CSR. Experimental results on 18 datasets show that our optimization yields up to 15.5x (12.3x on average) speedups.

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    • (2023)Coupled Incomplete Cholesky and Jacobi Preconditioned Conjugate Gradient on the New Generation of Sunway Many-Core ArchitectureIEEE Transactions on Computers10.1109/TC.2023.329688472:11(3326-3339)Online publication date: 1-Nov-2023
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    cover image ACM Conferences
    ICS '18: Proceedings of the 2018 International Conference on Supercomputing
    June 2018
    407 pages
    ISBN:9781450357838
    DOI:10.1145/3205289
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Published: 12 June 2018

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    Author Tags

    1. Locality
    2. Parallelism
    3. SpMV
    4. Sparse Matrices
    5. Sunway Architecture

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    Overall Acceptance Rate 629 of 2,180 submissions, 29%

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    Cited By

    View all
    • (2023)A Survey of Accelerating Parallel Sparse Linear AlgebraACM Computing Surveys10.1145/360460656:1(1-38)Online publication date: 28-Aug-2023
    • (2023)ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear SolversProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3581784.3607077(1-15)Online publication date: 12-Nov-2023
    • (2023)Coupled Incomplete Cholesky and Jacobi Preconditioned Conjugate Gradient on the New Generation of Sunway Many-Core ArchitectureIEEE Transactions on Computers10.1109/TC.2023.329688472:11(3326-3339)Online publication date: 1-Nov-2023
    • (2023)hsSpMV: A Heterogeneous and SPM-aggregated SpMV for SW26010-Pro many-core processor2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing (CCGrid)10.1109/CCGrid57682.2023.00016(62-70)Online publication date: May-2023
    • (2023)Adapting combined tiling to stencil optimizations on sunway processorCCF Transactions on High Performance Computing10.1007/s42514-023-00147-x5:3(322-333)Online publication date: 17-May-2023
    • (2023)Towards optimized tensor code generation for deep learning on sunway many-core processorFrontiers of Computer Science10.1007/s11704-022-2440-718:2Online publication date: 13-Sep-2023
    • (2023)Building a domain-specific compiler for emerging processors with a reusable approachScience China Information Sciences10.1007/s11432-022-3727-667:1Online publication date: 27-Dec-2023
    • (2022)TaiChi: A Hybrid Compression Format for Binary Sparse Matrix-Vector Multiplication on GPUIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.317050133:12(3732-3745)Online publication date: 1-Dec-2022
    • (2022)HDagg: Hybrid Aggregation of Loop-carried Dependence Iterations in Sparse Matrix Computations2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS53621.2022.00121(1217-1227)Online publication date: May-2022
    • (2022)A scalable adaptive-matrix SPMV for heterogeneous architectures2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS53621.2022.00011(13-24)Online publication date: May-2022
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