research-article

Enhancing the Energy Efficiency of Journaling File System via Exploiting Multi-Write Modes on MLC NVRAM

Authors:

Yuan-Hao Chang,

Wei-Kuan ShihAuthors Info & Claims

ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design

Article No.: 23, Pages 1 - 6

https://doi.org/10.1145/3218603.3218632

Published: 23 July 2018 Publication History

Abstract

Non-volatile random-access memory (NVRAM) is regarded as a great alternative storage medium owing to its attractive features, including low idle energy consumption, byte addressability, and short read/write latency. In addition, multi-level-cell (MLC) NVRAM has also been proposed to provide higher bit density. However, MLC NVRAM has lower energy efficiency and longer write latency when compared with single-level-cell (SLC) NVRAM. These drawbacks could lead to higher energy consumption of MLC NVRAM-based storage systems. The energy consumption is magnified by existing journaling file systems (JFS) on MLC NVRAM-based storage devices due to the JFS's fail-safe policy of writing the same data twice. Such observations motivate us to propose a multi-write-mode journaling file systems (mwJFS) to alleviate the drawbacks of MLC NVRAM and lower the energy consumption of MLC NVRAM-based JFS. The proposed mwJFS differentiates the data retention requirement of journaled data and applies different write modes to enhance the energy efficiency with better access performance. A series of experiments was conducted to demonstrate the capability of mwJFS on a MLC NVRAM-based storage system.

References

[1]

R. H. Arpaci-Dusseau and A. C. Arpaci-Dusseau. 2015. Operating Systems: Three Easy Pieces, chapter Crash Consistency: FSCK and Journaling. Arpaci-Dusseau Books (2015).

Digital Library

[2]

JEDEC Solid State Technology Association. 2016. Solid-State Drive (SSD) Requirements and Endurance Test Method (JESD218)@ONLINE, https://www.jedec.org/system/files/docs/JESD218.pdf. (2016).

[3]

T. Y. Chen, Y. H. Chang, S. H. Chen, C. C. Kuo, M. C. Yang, H. W. Wei, and W. K. Shih. Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM. In Proceedings of the 54th Annual Design Automation Conference 2017.

Digital Library

[4]

C. C. Ho, Y. M. Chang, Y. H. Chang, H. C. Chen, and T. W. Kuo. 2017. Write-aware Memory Management for Hybrid SLC-MLC PCM Memory Systems. ACM SIGAPP Applied Computing Review (ACR) (2017).

Digital Library

[5]

IOzone. 2016. IOzone Filesystem Benchmark. http://www.iozone.org/. (2016).

[6]

A. Jog, A. K. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and C. R. Das. 2012. Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In DAC Design Automation Conference 2012.

Digital Library

[7]

Jeffrey Katcher. 1997. PostMark: a new file system benchmark. Network Appliance Tech Report TR3022. (Oct 1997).

[8]

Jawad B. Khan. 2013. Method to detect uncompressible data in mass storage device. (3 1 2013). https://www.google.com/patents/US20130007346

[9]

E. Lee, H. Bahn, and Sam H. Noh. 2013. Unioning of the Buffer Cache and Journaling Layers with Non-volatile Memory. In Proceedings of the 11th USENIX Conference on File and Storage Technologies.

Digital Library

[10]

E. Lee, S. Hoon Yoo, and H. Bahn. 2015. Design and Implementation of a Journaling File System for Phase-Change Memory. IEEE Trans. Comput. (2015).

[11]

Q. Li, L.Jiang, Y. Zhang, Y. He, and C.J. Xue. 2013. Compiler Directed Write-mode Selection for High Performance Low Power Volatile PCM. In Proceedings of the 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems.

Digital Library

[12]

R. S. Liu, D. Y. Shen, C. L. Yang, S. C. Yu, and C. Y. Michael Wang. 2014. NVM Duet: Unified Working Memory and Persistent Store Architecture. SIGPLAN Not. (2014), 455--470.

Digital Library

[13]

R. S. Liu, C. L. Yang, and W. Wu. 2012. Optimizing NAND Flash-Based SSDs via Retention Relaxation. In 10th USENIX Conference on File and Storage Technologies.

Digital Library

[14]

C. Pan, M. Xie, J. Hu, Y. Chen, and C. Yang. 2014. 3M-PCM: Exploiting Multiple Write Modes MLC Phase Change Main Memory in Embedded Systems. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis.

Digital Library

[15]

Y. Park and J. s. Kim. 2011. zFTL: power-efficient data compression support for NAND flash-based consumer electronics devices. IEEE Transactions on Consumer Electronics (2011).

[16]

A. Redaelli, A. Pirovano, A. Locatelli, and F. Pellizzer. 2008. Numerical Implementation of Low Field Resistance Drift for Phase Change Memory Simulations. In 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

[17]

U. Russo, D. Ielmini, and A. L. Lacaita. 2007. Analytical Modeling of Chalcogenide Crystallization for PCM Data-Retention Extrapolation. IEEE Transactions on Electron Devices (2007).

[18]

K. Vtt, I. Cutress, and R. Smith. 2015. Analyzing Intel-Micron 3D XPoint: The Next Generation Non-Volatile Memory @ONLINE, http://goo.gl/xhjPRr. (2015). http://goo.gl/xhjPRr

[19]

Xilinx. 2017. Xilinx Power Estimator (XPE). https://www.xilinx.com/products/technology/power/xpe.html. (2017).

[20]

C. Xu, D. Niu, N. Muralimanohar, N. P. Jouppi, and Y. Xie. 2013. Understanding the trade-offs in multi-level cell ReRAM memory design. In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Digital Library

[21]

W. Zhang and T. Li. 2011. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In 2011 IEEE/IFIP 41st International Conference on Dependable Systems Networks (DSN).

Digital Library

[22]

Z. Zhang, L. Ju, and Z. Jia. 2016. Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE).

Digital Library

Cited By

Liang YHsu YChen TChen SWei HHsu TShih W(2021)Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAM2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586164(649-654)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586164
Zhang ZShen ZJia ZShao Z(2020)UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292536639:9(1792-1805)Online publication date: Sep-2020
https://doi.org/10.1109/TCAD.2019.2925366
Chen SChen TChang YWei HShih W(2020)A Partial Page Cache Strategy for NVRAM-Based Storage DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288704539:2(373-386)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2887045
Show More Cited By

Index Terms

Enhancing the Energy Efficiency of Journaling File System via Exploiting Multi-Write Modes on MLC NVRAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory
  2. Power and energy
    1. Energy distribution
      1. Power conversion
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Secondary storage

Recommendations

Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Non-volatile random-access memory (NVRAM) becomes a mainstream storage device in embedded systems due to its favorable features, such as small size, low power consumption, and short read/write latency. On NVRAM, a write operation consumes more energy ...
Write-aware memory management for hybrid SLC-MLC PCM memory systems

In recent years, phase-change memory (PCM) has generated a great deal of interest because of its byte addressability and non-volatility properties. It is regarded as a good alternative storage medium that can reduce the performance gap between the main ...
Enabling union page cache to boost file access performance of NVRAM-based storage device
DAC '18: Proceedings of the 55th Annual Design Automation Conference

Due to the fast access performance, byte-addressability, and non-volatility of non-volatile random access memory (NVRAM), NVRAM has emerged as a popular candidate for the design of memory/storage systems on mobile computing systems. For example, the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design

July 2018

327 pages

ISBN:9781450357043

DOI:10.1145/3218603

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2018

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

ISLPED '18

Sponsor:

SIGDA

ISLPED '18: International Symposium on Low Power Electronics and Design

July 23 - 25, 2018

WA, Seattle, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
145
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Liang YHsu YChen TChen SWei HHsu TShih W(2021)Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAM2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586164(649-654)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586164
Zhang ZShen ZJia ZShao Z(2020)UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292536639:9(1792-1805)Online publication date: Sep-2020
https://doi.org/10.1109/TCAD.2019.2925366
Chen SChen TChang YWei HShih W(2020)A Partial Page Cache Strategy for NVRAM-Based Storage DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288704539:2(373-386)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2887045
Chen SChang YChang YShih W(2019)mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM StoragesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291990727:9(2060-2073)Online publication date: Sep-2019
https://doi.org/10.1109/TVLSI.2019.2919907

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents