research-article

Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge

Authors:

Tomoaki Ukezono,

Toshinori SatoAuthors Info & Claims

GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022

Pages 229 - 235

https://doi.org/10.1145/3526241.3530315

Published: 06 June 2022 Publication History

Abstract

Convolutional neural networks (CNNs) have demonstrated significant potential across a range of applications due to their superior accuracy. Edge inference, in which inference is performed locally in embedded systems with limited power resources, is researched for its energy efficiency. An approximate encoder is proposed in this study for decreasing switching activity, which minimizes power consumption in CNN accelerators at the edge. The proposed encoder performs approximate encoding based on a pattern matching of a comparison pattern and current data. Software determines the value of the comparison pattern and the availability of the recommended encoder. Experiments with a CIFAR-10 dataset utilizing LeNet5 show that using the suggested encoder, depending upon the comparison pattern, power consumption of a CNN accelerator can be reduced by 21.5% with 1.59% degradation on inference quality.

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Cited By

Omshi MFaghih Mirzaee RReza AMirzaei M(2024)Low-Power Bus Encoding by Ternary LWC and Quaternary Transition Signaling: From Initial Concept to Circuit DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333727732:4(682-694)Online publication date: Apr-2024
https://doi.org/10.1109/TVLSI.2023.3337277
Damsgaard HOmetov ANurmi J(2023)Approximation Opportunities in Edge Computing Hardware: A Systematic Literature ReviewACM Computing Surveys10.1145/357277255:12(1-49)Online publication date: 3-Mar-2023
https://dl.acm.org/doi/10.1145/3572772

Index Terms

Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
    2. Reconfigurable logic and FPGAs
      1. Hardware accelerators

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cover image ACM Conferences

GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022

June 2022

560 pages

ISBN:9781450393225

DOI:10.1145/3526241

General Chairs:
Ioannis Savidis
Drexel University, USA
,
Avesta Sasan
University of California, Davis, USA
,
Program Chairs:
Himanshu Thapliyal
University of Tennessee, Knoxville, USA
,
Ronald F. DeMara
University of Central Florida, USA

Copyright © 2022 ACM.

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New York, NY, United States

Publication History

Published: 06 June 2022

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Funding Sources

Fukuoka University Internal Research Competitive Funds
JSPS KAKENHI Grant

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GLSVLSI '22

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SIGDA

GLSVLSI '22: Great Lakes Symposium on VLSI 2022

June 6 - 8, 2022

CA, Irvine, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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GLSVLSI '25

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Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

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Cited By

Omshi MFaghih Mirzaee RReza AMirzaei M(2024)Low-Power Bus Encoding by Ternary LWC and Quaternary Transition Signaling: From Initial Concept to Circuit DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333727732:4(682-694)Online publication date: Apr-2024
https://doi.org/10.1109/TVLSI.2023.3337277
Damsgaard HOmetov ANurmi J(2023)Approximation Opportunities in Edge Computing Hardware: A Systematic Literature ReviewACM Computing Surveys10.1145/357277255:12(1-49)Online publication date: 3-Mar-2023
https://dl.acm.org/doi/10.1145/3572772

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