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PipeJSON: Parsing JSON at Line Speed on FPGAs

Published: 13 June 2022 Publication History

Abstract

JavaScript Object Notation (JSON) gained popularity as a data exchange and storage format. While recent advances on modern CPUs show an improved JSON parsing by using data parallelism with vector instructions, the rigid instruction set and limited pipelining of CPUs prevent parsing performance from reaching the practical limit of memory bandwidth.
We present PipeJSON, the first standard-compliant JSON parser to process tens of gigabytes of data per second. It utilizes FPGA hardware to make extensive use of pipelining and can parse multiple characters per clock cycle. To ensure usability in software projects, PipeJSON is written in Data Parallel C++ and achieves 7.95 × speedup over state-of-the-art JSON parsers on CPU, despite data transfer to the FPGA.

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Cited By

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  • (2024)JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00012(11-18)Online publication date: 2-Sep-2024
  • (2024)ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS60919.2024.10508904(79-85)Online publication date: 3-Apr-2024
  • (2024)On‐demand JSON: A better way to parse documents?Software: Practice and Experience10.1002/spe.331354:6(1074-1086)Online publication date: 18-Jan-2024

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Published In

cover image ACM Other conferences
DaMoN '22: Proceedings of the 18th International Workshop on Data Management on New Hardware
June 2022
83 pages
ISBN:9781450393782
DOI:10.1145/3533737
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

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Publication History

Published: 13 June 2022

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Author Tags

  1. FPGA
  2. Hardware Pipelining
  3. JSON Parsing
  4. SIMD

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  • Research-article
  • Research
  • Refereed limited

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SIGMOD/PODS '22
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DaMoN '22 Paper Acceptance Rate 12 of 18 submissions, 67%;
Overall Acceptance Rate 94 of 127 submissions, 74%

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Cited By

View all
  • (2024)JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00012(11-18)Online publication date: 2-Sep-2024
  • (2024)ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS60919.2024.10508904(79-85)Online publication date: 3-Apr-2024
  • (2024)On‐demand JSON: A better way to parse documents?Software: Practice and Experience10.1002/spe.331354:6(1074-1086)Online publication date: 18-Jan-2024
  • (2023)SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00034(189-196)Online publication date: 4-Sep-2023

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