Article

Switching activity analysis and pre-layout activity prediction for FPGAs

Authors:

Jason H. Anderson,

Farid N. NajmAuthors Info & Claims

SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction

Pages 15 - 21

https://doi.org/10.1145/639929.639934

Published: 05 April 2003 Publication History

Abstract

It is well-known that dynamic power dissipation in digital CMOS circuits depends linearly on switching activity. In this paper, we study switching activity in a commercial FPGA and propose a novel approach to pre-layout activity prediction. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). Low-power synthesis and early power estimation are typically done on the basis of zero delay activity values, with the assumption that such values correlate well with routed delay activity values. We investigate whether this assumption is valid for FPGA technologies, where critical path delay is often dominated by interconnect delay. We then present an approach for early prediction of routed delay activity values. Our approach is novel in that it estimates each net's routed delay activity using only zero or logic delay activity values along with structural and functional properties of a circuit. Results show that in comparison with zero or logic delay activity values, the predicted activity values are substantially more representative of routed delay activity values.

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Cited By

Liu JGraczyk MGuerrieri AJosipović L(2024)Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00025(118-125)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00025
Ramesh SJayaparvathy R(2017)Toggle rate estimation and glitch analysis on logic circuits2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)10.1109/IWIPP.2017.7936747(1-5)Online publication date: Apr-2017
https://doi.org/10.1109/IWIPP.2017.7936747
Adhinarayanan VPaul IGreathouse JHuang WPattnaik AFeng W(2016)Measuring and modeling on-chip interconnect power on real hardware2016 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2016.7581263(1-11)Online publication date: Sep-2016
https://doi.org/10.1109/IISWC.2016.7581263
Show More Cited By

Index Terms

Switching activity analysis and pre-layout activity prediction for FPGAs
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction

April 2003

147 pages

ISBN:1581136277

DOI:10.1145/639929

General Chair:
Dennis Sylvester
University of Michigan, Ann Arbor, MI
,
Program Chairs:
Dirk Stroobandt
Ghent University, Belgium
,
Lou Scheffer
Cadence
,
Publications Chair:
Payman Zarkesh-Ha
LSI Logic

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 April 2003

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SLIP03: International Workshop on System Level Interconnect Prediction

April 5 - 6, 2003

CA, Monterey, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Liu JGraczyk MGuerrieri AJosipović L(2024)Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00025(118-125)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00025
Ramesh SJayaparvathy R(2017)Toggle rate estimation and glitch analysis on logic circuits2017 IEEE International Workshop On Integrated Power Packaging (IWIPP)10.1109/IWIPP.2017.7936747(1-5)Online publication date: Apr-2017
https://doi.org/10.1109/IWIPP.2017.7936747
Adhinarayanan VPaul IGreathouse JHuang WPattnaik AFeng W(2016)Measuring and modeling on-chip interconnect power on real hardware2016 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2016.7581263(1-11)Online publication date: Sep-2016
https://doi.org/10.1109/IISWC.2016.7581263
Anju PRamesh S(2012)Toggle rate estimation technique for FPGA circuits considering spatial correlation2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)10.1109/ICCCNT.2012.6395937(1-7)Online publication date: Jul-2012
https://doi.org/10.1109/ICCCNT.2012.6395937
Czajkowski TBrown S(2010)Decomposition-based vectorless toggle rate computation for FPGA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206125029:11(1723-1735)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061250
Czajkowski TBrown S(2008)Fast toggle rate computation for FPGA circuits2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629909(65-70)Online publication date: Sep-2008
https://doi.org/10.1109/FPL.2008.4629909
Czajkowski TBrown SLevitan S(2007)Using negative edge triggered ffs to reduce glitching power in FPGA circuitsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278563(324-329)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278563
Cheng LChen DWong MLevitan S(2007)GlitchMapProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278562(318-323)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278562
Jia XVemuri RTang T(2005)Using GALS architecture to reduce the impact of long wire delay on FPGA performanceProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121038(1260-1263)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121038
Sidahao NConstantinides GCheung P(2005)Power and area optimization for multiple restricted multiplicationInternational Conference on Field Programmable Logic and Applications, 2005.10.1109/FPL.2005.1515708(112-117)Online publication date: 2005
https://doi.org/10.1109/FPL.2005.1515708
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