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Weirong Jiang
My research is on designing parallel algorithms and architectures for high-performance, low-power, flexible and robust networking systems.
Specifically, I worked on developing novel customized hardware engines (mainly using FPGA) to solve a wide range of network processing problems, from basic packet forwarding (e.g. IP lookup, packet classification in routers / firewalls) to advanced traffic analysis (e.g. regular expression matching, application identification in NIDS). I've participated in multiple R&D projects and published over 20 research papers in major conferences and journals. 4 of my papers have been awarded the best papers.
Supervisors: Viktor K. Prasanna
Address: 3740 McClintock Avenue, EEB-244,
Department of EE-Systems,
University of Southern California,
Los Angeles, CA 90089-2562
Specifically, I worked on developing novel customized hardware engines (mainly using FPGA) to solve a wide range of network processing problems, from basic packet forwarding (e.g. IP lookup, packet classification in routers / firewalls) to advanced traffic analysis (e.g. regular expression matching, application identification in NIDS). I've participated in multiple R&D projects and published over 20 research papers in major conferences and journals. 4 of my papers have been awarded the best papers.
Supervisors: Viktor K. Prasanna
Address: 3740 McClintock Avenue, EEB-244,
Department of EE-Systems,
University of Southern California,
Los Angeles, CA 90089-2562
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pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific techniques to reduce the dynamic power consumption in SRAM-based pipelined IP forwarding engines. First, the pipeline architecture itself is built as an inherent cache, exploiting the data locality in Internet traffic. The number of memory accesses which contribute to the majority of power consumption, is thus reduced. No external cache is needed. Second, instead of using a global clock, different pipeline stages are driven by separate clocks. The local locking scheme is carefully designed to exploit the traffic rate variation and improve the caching performance. Third, a fine-grained memory enabling scheme is developed to eliminate unnecessary memory accesses, while preserving the packet order. Simulation experiments using real-life traces show that our solutions can achieve up to 15-fold reduction in dynamic power dissipation, over the baseline pipeline architecture that does not employ the proposed schemes. FPGA implementation results show that our design sustains 40 Gbps throughput for minimum size (40 bytes)
packets while consuming a small amount of logic resources.
pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific techniques to reduce the dynamic power consumption in SRAM-based pipelined IP forwarding engines. First, the pipeline architecture itself is built as an inherent cache, exploiting the data locality in Internet traffic. The number of memory accesses which contribute to the majority of power consumption, is thus reduced. No external cache is needed. Second, instead of using a global clock, different pipeline stages are driven by separate clocks. The local locking scheme is carefully designed to exploit the traffic rate variation and improve the caching performance. Third, a fine-grained memory enabling scheme is developed to eliminate unnecessary memory accesses, while preserving the packet order. Simulation experiments using real-life traces show that our solutions can achieve up to 15-fold reduction in dynamic power dissipation, over the baseline pipeline architecture that does not employ the proposed schemes. FPGA implementation results show that our design sustains 40 Gbps throughput for minimum size (40 bytes)
packets while consuming a small amount of logic resources.