This paper describes a preliminary experiment in designing a Hidden Markov Model (HMM)-based part... more This paper describes a preliminary experiment in designing a Hidden Markov Model (HMM)-based part-of-speech tagger for the Lithuanian language. Part-of-speech tagging is the problem of assigning to each word of a text the proper tag in its context of appearance. It is accom- plished in two basic steps: morphological analysis and disambiguation. In this paper, we focus on the problem of disambiguation, i.e., on the problem of choosing the correct tag for each word in the context of a set of possible tags. We constructed a stochastic disambiguation algorithm, based on supervised learning techniques, to learn hidden Markov model's parameters from hand-annotated corpora. The Viterbi algorithm is used to assign the most probable tag to each word in the text.
For a generic flexible efficient array antenna receiver platform a hierarchical tiled architectur... more For a generic flexible efficient array antenna receiver platform a hierarchical tiled architecture has been proposed, giving a heterogeneous multi-processor system-on-chip (MPSoC), multiple chips on a board (MCoB) and multiple boards in a system (MBiS). A wide range of MPSoCs are predicted to be used in the near future but how to efficiently apply these designs remains an issue. We will advocate a model-based design approach and propose a single semantic (programming) model for representing the specification, design and implementation and allowing for verification, simulation, architecture definition and design space exploration. A single model for specification, (formal or functional) verification, simulation and programming an MPSoC has obvious as well as some less obvious advantages. It allows for model-based design down to the implementation, especially for hierarchical MPSoC architectures. Partitioning and mapping of the functionality to an architecture is commonly done manuall...
Synchronous hardware can be modelled as a mapping from input and state to output and a new state.... more Synchronous hardware can be modelled as a mapping from input and state to output and a new state. Functions in this form are referred to as transition functions. It is natural to use a functional lan-guage to implement transition functions. The CλaSH compiler is capa-ble of translating Haskell code written in this form to VHDL. Modelling hardware using multiple components is convenient. Components can be considered as instantiations of functions. To avoid packing and unpacking state when composing components, functions are lifted to arrows. By us-ing arrows the chance of making errors will decrease as it is not required to manually (un)pack the state. Furthermore, the Haskell do-syntax for arrows is a pleasant notation for describing hardware designs.
SoOSiM is a simulator developed for the purpose of exploring operating system concepts and operat... more SoOSiM is a simulator developed for the purpose of exploring operating system concepts and operating system modules. The simulator provides a highly abstracted view of a computing system, consisting of computing nodes, and components that are concurrently executed on these nodes. OS modules are subsequently modelled as components that progress as a result of reacting to two types of events:
ABSTRACT Exact temporal analyses of multi-rate synchronous dataflow (MRSDF) graphs, such as compu... more ABSTRACT Exact temporal analyses of multi-rate synchronous dataflow (MRSDF) graphs, such as computing the maximum achievable throughput, or sufficient buffer sizes required to reach a minimum throughput, require a homogeneous representation called a homogeneous synchronous dataflow (HSDF) graph. The size of such an HSDF graph may, in the worst case, be exponential in the size of the MRSDF graph. In this paper, we revisit the transformation from MRSDF to HSDF, and show how this transformation may be done either exactly or approximately. The approximate transformation gives both an optimistic and a pessimistic HSDF graph, each of which has the same size as the MRSDF graph. We furthermore show how strict lower and upper bounds on throughput, or on the buffer sizes required to reach a minimum throughput, may be obtained from these approximating graphs.
This paper describes a preliminary experiment in designing a Hidden Markov Model (HMM)-based part... more This paper describes a preliminary experiment in designing a Hidden Markov Model (HMM)-based part-of-speech tagger for the Lithuanian language. Part-of-speech tagging is the problem of assigning to each word of a text the proper tag in its context of appearance. It is accom- plished in two basic steps: morphological analysis and disambiguation. In this paper, we focus on the problem of disambiguation, i.e., on the problem of choosing the correct tag for each word in the context of a set of possible tags. We constructed a stochastic disambiguation algorithm, based on supervised learning techniques, to learn hidden Markov model's parameters from hand-annotated corpora. The Viterbi algorithm is used to assign the most probable tag to each word in the text.
For a generic flexible efficient array antenna receiver platform a hierarchical tiled architectur... more For a generic flexible efficient array antenna receiver platform a hierarchical tiled architecture has been proposed, giving a heterogeneous multi-processor system-on-chip (MPSoC), multiple chips on a board (MCoB) and multiple boards in a system (MBiS). A wide range of MPSoCs are predicted to be used in the near future but how to efficiently apply these designs remains an issue. We will advocate a model-based design approach and propose a single semantic (programming) model for representing the specification, design and implementation and allowing for verification, simulation, architecture definition and design space exploration. A single model for specification, (formal or functional) verification, simulation and programming an MPSoC has obvious as well as some less obvious advantages. It allows for model-based design down to the implementation, especially for hierarchical MPSoC architectures. Partitioning and mapping of the functionality to an architecture is commonly done manuall...
Synchronous hardware can be modelled as a mapping from input and state to output and a new state.... more Synchronous hardware can be modelled as a mapping from input and state to output and a new state. Functions in this form are referred to as transition functions. It is natural to use a functional lan-guage to implement transition functions. The CλaSH compiler is capa-ble of translating Haskell code written in this form to VHDL. Modelling hardware using multiple components is convenient. Components can be considered as instantiations of functions. To avoid packing and unpacking state when composing components, functions are lifted to arrows. By us-ing arrows the chance of making errors will decrease as it is not required to manually (un)pack the state. Furthermore, the Haskell do-syntax for arrows is a pleasant notation for describing hardware designs.
SoOSiM is a simulator developed for the purpose of exploring operating system concepts and operat... more SoOSiM is a simulator developed for the purpose of exploring operating system concepts and operating system modules. The simulator provides a highly abstracted view of a computing system, consisting of computing nodes, and components that are concurrently executed on these nodes. OS modules are subsequently modelled as components that progress as a result of reacting to two types of events:
ABSTRACT Exact temporal analyses of multi-rate synchronous dataflow (MRSDF) graphs, such as compu... more ABSTRACT Exact temporal analyses of multi-rate synchronous dataflow (MRSDF) graphs, such as computing the maximum achievable throughput, or sufficient buffer sizes required to reach a minimum throughput, require a homogeneous representation called a homogeneous synchronous dataflow (HSDF) graph. The size of such an HSDF graph may, in the worst case, be exponential in the size of the MRSDF graph. In this paper, we revisit the transformation from MRSDF to HSDF, and show how this transformation may be done either exactly or approximately. The approximate transformation gives both an optimistic and a pessimistic HSDF graph, each of which has the same size as the MRSDF graph. We furthermore show how strict lower and upper bounds on throughput, or on the buffer sizes required to reach a minimum throughput, may be obtained from these approximating graphs.
Uploads