Abstract– Mapping of tasks on the cores of a Network-on-Chip (NoC) has direct impact on the effic... more Abstract– Mapping of tasks on the cores of a Network-on-Chip (NoC) has direct impact on the efficiency of the network. This paper provides a comprehensive study regarding application mapping for NoCs to clarify their pros and cons. The study considers different aspects including performance, power consumption, and reliability of mappings. Four mappings named NMAP, RMAP, Random, and Adhoc are used in this study by the means of a cycle accurate NoC simulator. Our study shows that the RMAP provides the maximum reliability for NoC with a low performance overhead. On the other hand, Random mapping requires the lowest time to complete mapping of the task on the chip. The power estimation patch of Orion is used in the simulation to explore the power consumption of a typical NoC using any of the mentioned mappings. Simulations are done for three different benchmarks i.e., MPEG, VOPD, and OPD application graphs.
Abstract–Switches and communication links of Network on Chips (NoCs) are highly vulnerable to tra... more Abstract–Switches and communication links of Network on Chips (NoCs) are highly vulnerable to transient faults due to the use of nano-scale VLSI technologies in fabrication of NoCs. This paper proposes a reconfigurable switch architecture which is capable of operating in four configurations with different levels of reliability. This is done by the use of a local configuration controller logic which is fully protected against transient faults. When a controller detects a high error rate situation, it configures the switch to a high reliability mode and vice versa. Reconfiguration policy is designed in a way which minimizes the imposed performance and power overheads to the switch. Evaluations are done by a cycle accurate NoC simulator with Orion patch for power estimation. Simulation results show a noticeable reliability improvement with a negligible performance overhead. In addition, power saving of at least 20% is achieved by the proposed architecture.
Abstract– Mapping of tasks on the cores of a Network-on-Chip (NoC) has direct impact on the effic... more Abstract– Mapping of tasks on the cores of a Network-on-Chip (NoC) has direct impact on the efficiency of the network. This paper provides a comprehensive study regarding application mapping for NoCs to clarify their pros and cons. The study considers different aspects including performance, power consumption, and reliability of mappings. Four mappings named NMAP, RMAP, Random, and Adhoc are used in this study by the means of a cycle accurate NoC simulator. Our study shows that the RMAP provides the maximum reliability for NoC with a low performance overhead. On the other hand, Random mapping requires the lowest time to complete mapping of the task on the chip. The power estimation patch of Orion is used in the simulation to explore the power consumption of a typical NoC using any of the mentioned mappings. Simulations are done for three different benchmarks i.e., MPEG, VOPD, and OPD application graphs.
Abstract–Switches and communication links of Network on Chips (NoCs) are highly vulnerable to tra... more Abstract–Switches and communication links of Network on Chips (NoCs) are highly vulnerable to transient faults due to the use of nano-scale VLSI technologies in fabrication of NoCs. This paper proposes a reconfigurable switch architecture which is capable of operating in four configurations with different levels of reliability. This is done by the use of a local configuration controller logic which is fully protected against transient faults. When a controller detects a high error rate situation, it configures the switch to a high reliability mode and vice versa. Reconfiguration policy is designed in a way which minimizes the imposed performance and power overheads to the switch. Evaluations are done by a cycle accurate NoC simulator with Orion patch for power estimation. Simulation results show a noticeable reliability improvement with a negligible performance overhead. In addition, power saving of at least 20% is achieved by the proposed architecture.
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