The calls for accountability in higher education have made outcome-based assessment a key accredi... more The calls for accountability in higher education have made outcome-based assessment a key accreditation component. Accreditation remains a well-regarded seal of approval on college quality, and requires the programme to set clear, appropriate, and measurable goals and courses to attain them. Furthermore, programmes must demonstrate that responsibilities associated with the goals are being carried out. Assessment leaders face various challenges including process design and implementation, faculty buy-in, and resources availability. This paper presents an outcome-based assessment approach that facilitates faculty participation while simplifying the assessment and reporting processes through effective and meaningful visualisation. The proposed approach has been implemented and used for the successful ABET accreditation of a computer science programme, and can be easily adapted to any higher education programme.
The increasing trend in the number of cores on a single chip has led to scalability and bandwidth... more The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.
Assessing learning in the Computer Science program at the Lebanese American University implies de... more Assessing learning in the Computer Science program at the Lebanese American University implies developing systematic and sustainable processes that 1) determine whether students learning outcomes at the program level as well as at course level are being achieved, and 2) determine program and course delivery improvement that will enhance student learning. This paper describes the design and implementation of the learning assessment process for the Computer Science Program at the Lebanese American University, Lebanon. The process includes a comprehensive plan to collect and analyze information on student performance in order to assess student learning and the effectiveness of the curriculum while planning to meet the ABET accreditation requirements. Assessment results from 2008-2009 are presented, and program adjustment is proposed.
The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made ... more The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions (1) were not optimal;(2) did not incorporate testing at the system level. In this Work, we propose a prototype high-level synthesis system with self-testability, SYNTEST, that alleviates the above problems. SYNTEST is based on a model that treats testing as a structural design property during ...
IEEE Canadian Journal of Electrical and Computer Engineering, 2000
This paper presents a new approach for redesign for testability at the Register-Transfer Level (R... more This paper presents a new approach for redesign for testability at the Register-Transfer Level (RTL). The method identifies hard to test parts in RTL designs that were synthesized, either manually or automatically using a high-level synthesis tool. The design is modified by inserting additional registers that are active during test mode. The insertion process is followed by a test selection process that uses functional test metrics in order to minimize test overhead. Finally, test scheduling is performed in order to minimize the ...
Parallel genetic algorithms techniques have been used in a variety of computer engineering and sc... more Parallel genetic algorithms techniques have been used in a variety of computer engineering and science areas. This paper presents a parallel genetic algorithm to solve the geometrically constrained site layout problem that involves coordinating the use of limited space to accommodate temporary facilities subject to geometric constraints. The algorithm is parallelized based on a message passing architecture using parallel search and chromosomes migration. The algorithm is tested on a variety of layout problems to ...
A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The me... more A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The ...
This paper investigates the use of parallel genetic algorithms in order to solve the open-shop sc... more This paper investigates the use of parallel genetic algorithms in order to solve the open-shop scheduling problem. The method is based on an interesting implementation of genetic operators that combines the use of deterministic and random moves. The method is implemented using MPI on a Beowulf cluster. Favorable results comparisons using the Taillard benchmarks are reported.
Computing in Civil and Building Engineering (2000), 2000
Construction site layout has been recognized as an important activity in construction site planni... more Construction site layout has been recognized as an important activity in construction site planning by field practitioners and researchers alike. This problem involves coordinating the use of limited space to accommodate temporary facilities (such as fabrication shops, trailers, materials or equipment) so that transportation costs of resources are minimized. The layout problem considered in this paper is a static layout problem characterized by affinity weights used to model transportation costs between facilities and by geometric constraints ...
Abstract—A new method of redesign at the registertransfer level using a transformational process ... more Abstract—A new method of redesign at the registertransfer level using a transformational process is proposed. The redesign approach takes into consideration ALU and interconnect cost in ad<ion to layout area estimation. The idea is to start with a design, possibly generated by a synthesis system, and iteratively improve it by means of a reallocation process. The method is based on a set of reallocation trartsformations along with systematic strategies as to how to apply them together with a layout estimation model.
This paper presents an evolutionary approach to solve the data path allocation problem in high-le... more This paper presents an evolutionary approach to solve the data path allocation problem in high-level synthesis. From a behavioral description and a set of constraints, the method generates a VHDL RTL data path and a controller structure with a minimal cost. The proposed method was implemented using the C language on a Linux workstation. We tested our method on various high-level synthesis benchmarks, all yielding good solutions in a short time. Designs were validated using Altera Max+ Plus II
Test time minimization for core-based designs is tightly integrated with wrapper design and TAM c... more Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based on simulated annealing. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results using the ITC 2002 benchmarks.
Physica A: Statistical Mechanics and its Applications, Jul 1, 2007
This paper presents a model for option pricing in markets that experience financial crashes. The ... more This paper presents a model for option pricing in markets that experience financial crashes. The stochastic differential equation (SDE) of stock price dynamics is coupled to a post-crash market index. The resultant SDE is shown to have stock price and time dependent volatility. The partial differential equation (PDE) for call prices is derived using risk-neutral pricing. European call prices are then estimated using Monte Carlo and finite difference methods. Results of the model show that call option prices after the crash are systematically less ...
The calls for accountability in higher education have made outcome-based assessment a key accredi... more The calls for accountability in higher education have made outcome-based assessment a key accreditation component. Accreditation remains a well-regarded seal of approval on college quality, and requires the programme to set clear, appropriate, and measurable goals and courses to attain them. Furthermore, programmes must demonstrate that responsibilities associated with the goals are being carried out. Assessment leaders face various challenges including process design and implementation, faculty buy-in, and resources availability. This paper presents an outcome-based assessment approach that facilitates faculty participation while simplifying the assessment and reporting processes through effective and meaningful visualisation. The proposed approach has been implemented and used for the successful ABET accreditation of a computer science programme, and can be easily adapted to any higher education programme.
The increasing trend in the number of cores on a single chip has led to scalability and bandwidth... more The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.
Assessing learning in the Computer Science program at the Lebanese American University implies de... more Assessing learning in the Computer Science program at the Lebanese American University implies developing systematic and sustainable processes that 1) determine whether students learning outcomes at the program level as well as at course level are being achieved, and 2) determine program and course delivery improvement that will enhance student learning. This paper describes the design and implementation of the learning assessment process for the Computer Science Program at the Lebanese American University, Lebanon. The process includes a comprehensive plan to collect and analyze information on student performance in order to assess student learning and the effectiveness of the curriculum while planning to meet the ABET accreditation requirements. Assessment results from 2008-2009 are presented, and program adjustment is proposed.
The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made ... more The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions (1) were not optimal;(2) did not incorporate testing at the system level. In this Work, we propose a prototype high-level synthesis system with self-testability, SYNTEST, that alleviates the above problems. SYNTEST is based on a model that treats testing as a structural design property during ...
IEEE Canadian Journal of Electrical and Computer Engineering, 2000
This paper presents a new approach for redesign for testability at the Register-Transfer Level (R... more This paper presents a new approach for redesign for testability at the Register-Transfer Level (RTL). The method identifies hard to test parts in RTL designs that were synthesized, either manually or automatically using a high-level synthesis tool. The design is modified by inserting additional registers that are active during test mode. The insertion process is followed by a test selection process that uses functional test metrics in order to minimize test overhead. Finally, test scheduling is performed in order to minimize the ...
Parallel genetic algorithms techniques have been used in a variety of computer engineering and sc... more Parallel genetic algorithms techniques have been used in a variety of computer engineering and science areas. This paper presents a parallel genetic algorithm to solve the geometrically constrained site layout problem that involves coordinating the use of limited space to accommodate temporary facilities subject to geometric constraints. The algorithm is parallelized based on a message passing architecture using parallel search and chromosomes migration. The algorithm is tested on a variety of layout problems to ...
A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The me... more A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The ...
This paper investigates the use of parallel genetic algorithms in order to solve the open-shop sc... more This paper investigates the use of parallel genetic algorithms in order to solve the open-shop scheduling problem. The method is based on an interesting implementation of genetic operators that combines the use of deterministic and random moves. The method is implemented using MPI on a Beowulf cluster. Favorable results comparisons using the Taillard benchmarks are reported.
Computing in Civil and Building Engineering (2000), 2000
Construction site layout has been recognized as an important activity in construction site planni... more Construction site layout has been recognized as an important activity in construction site planning by field practitioners and researchers alike. This problem involves coordinating the use of limited space to accommodate temporary facilities (such as fabrication shops, trailers, materials or equipment) so that transportation costs of resources are minimized. The layout problem considered in this paper is a static layout problem characterized by affinity weights used to model transportation costs between facilities and by geometric constraints ...
Abstract—A new method of redesign at the registertransfer level using a transformational process ... more Abstract—A new method of redesign at the registertransfer level using a transformational process is proposed. The redesign approach takes into consideration ALU and interconnect cost in ad<ion to layout area estimation. The idea is to start with a design, possibly generated by a synthesis system, and iteratively improve it by means of a reallocation process. The method is based on a set of reallocation trartsformations along with systematic strategies as to how to apply them together with a layout estimation model.
This paper presents an evolutionary approach to solve the data path allocation problem in high-le... more This paper presents an evolutionary approach to solve the data path allocation problem in high-level synthesis. From a behavioral description and a set of constraints, the method generates a VHDL RTL data path and a controller structure with a minimal cost. The proposed method was implemented using the C language on a Linux workstation. We tested our method on various high-level synthesis benchmarks, all yielding good solutions in a short time. Designs were validated using Altera Max+ Plus II
Test time minimization for core-based designs is tightly integrated with wrapper design and TAM c... more Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based on simulated annealing. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results using the ITC 2002 benchmarks.
Physica A: Statistical Mechanics and its Applications, Jul 1, 2007
This paper presents a model for option pricing in markets that experience financial crashes. The ... more This paper presents a model for option pricing in markets that experience financial crashes. The stochastic differential equation (SDE) of stock price dynamics is coupled to a post-crash market index. The resultant SDE is shown to have stock price and time dependent volatility. The partial differential equation (PDE) for call prices is derived using risk-neutral pricing. European call prices are then estimated using Monte Carlo and finite difference methods. Results of the model show that call option prices after the crash are systematically less ...
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Papers by Haidar Harmanani