Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model

Microsystem Technologies https://doi.org/10.1007/s00542-019-04595-w (0123456789().,-volV)(0123456789().,-volV) TECHNICAL PAPER Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model Arpan Deyasi1 • Angsuman Sarkar2 • Krishnendu Roy3 • Anal Roy Chowdhury3 Received: 16 March 2019 / Accepted: 14 August 2019 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2019 Abstract Differential conductance and transconductance of double-gate MOSFET are analytically computed in presence of high-K dielectric following Ortiz-Conde model. Poisson’s equation and carrier continuity equation are simultaneously solved incorporating the effect of back-gate, and independent-gate model is considered for electrical characterization. Percentage change of conductance and transconductance are calculated, and results are compared with published literature. Effect of high-K dielectric is analyzed with that obtained for conventional SiO2 materials where comparison is taking place with identical bias and structural parameters. Saturation of transconductance is obtained for high-K dielectrics for higher VGS and lower VDS, indicating the subthreshold condition. Pinch-off condition is also evaluated from the plot of differential conductance. Results are extremely useful for utilizing the device for analog and digital circuits with nano-device. 1 Introduction Owing to the miniaturization of semiconductor devices due to the continuous demand of lower power consumption, higher speed and less area as per the roadmap predicted by ITRS (http://www.itrs2.net), short-channel effect becomes integral part of device design (Tsai et al. 2018; Zareiee 2017). Several researches are published with shrinking dimension of MOSFET in the last decade indicating degradation of performance (Bangsaruntip et al. 2010; Rezaei et al. 2018; Liu et al. 2012) and as a remedy of this serious problem, several gate control mechanisms and corresponding novel structures are proposed (Suhag and & Arpan Deyasi deyasi_arpan@yahoo.co.in Angsuman Sarkar angsumansarkar@ieee.org Krishnendu Roy krishnendu.physics94@gmail.com Anal Roy Chowdhury analroychowdhury084@gmail.com 1 Department of Electronics and Communication Engineering, RCC Institute of Information Technology, Kolkata, India 2 Department of Electronics and Communication Engineering, Kalyani Govt Engineering College, Kalyani, India 3 Department of Electronic Science, Acharya Prafulla Chandra College, New Barrackpore, India Sharma 2017; Jaiswal and Kranti 2019; Yang 2019; Ye et al. 2018; Colinge 2007) to incorporate these devices in integrated circuits. This concept leads to the perception of multiple gate control (Kushwah et al. 2014; Gupta et al. 2019), a novel mechanism with reduced short-channel interference, precisely for devices in sub 50 nm range. Among the various published architectures, a few has successfully realized into the device level, thanks to the development on nanoelectronic fabrication processes with accurate precision (Pott et al. 2008; Park 2008). Doublegate MOSFET is the first candidate of this series, extensively researched in last few years (Ghouli et al. 2019; Dhiman et al. 2018; Yu et al. 2018); followed by triple-gate architecture (Nandi and Sarkar 2013), all-around-gate MOSFET (Deyasi and Sarkar 2018), nanowire MOSFET (Kim and Kim 2018), CNT-based MOSFET (Bendre et al. 2018), junctionless device (Xie et al. 2017) etc. DG MOSFET is preferred due to its unique capability of exempting from short-channel effect with reduced subthreshold slope and DIBL compared with single-gate conventional one (Vadthiya et al. 2018; Ramezani and Orouji 2018). That’s why DG MOSFET becomes the choice of candidate in integrated circuit design for analog (Keane et al. 2008) or digital (Jandhyala et al. 2012) applications. Two different topologies of DG MOSFET are proposed by various workers, based on the requirement of either higher current density or from the point of lower power 123 Microsystem Technologies dissipation. Independent-gate is such type of architecture where power dissipation can be reduced as less no. of transistors are used for design (Thakur and Mahapatra 2011); which effectively leads to lower threshold voltage and higher back-gate control. On the other hand, tied-gate architecture provides higher current density (Woo et al. 2008) owing to compact floorplanning. A vis-à-vis comparative study between TG and ID devices speaks for the later one for the low power application. The sole aim of reduction of leakage power is further boosted with the incorporation of high-K dielectric material (Narendar and Girdhardas 2018; Salmani-Jelodar et al. 2016), which restricts the drain current flow inside channel under same biasing condition. Among several dielectric materials, HfO2 and TiO2 are investigated a lot, due to their superior performance (Mohapatra et al. 2012; Roy et al. 2019) over the other candidates for identical purpose. Also the dimension of the vertical layer can be narrowed down to sub 10 nm region, which directs to the transistors with subthreshold slope close to the ideal 60 mV/decade. Thus investigation of ID-DG MOSFET in presence of high-K dielectric becomes the subject of research. Analysis of DG MOSFET starts with solution of Poisson’s equation for determination of surface potential and electric field (Taur et al. 2004) by Taur, and he lately introduced the concept of volume inversion in that architecture at subthreshold region. Their theoretical work results the computation of drain current with the optimizing solution of Poisson’s and continuity equations (Taur 2001) after due convergence for symmetrical structure. Concept of asymmetry is lately introduced (Lu and Taur 2006) for determination of junction capacitance and charge density. The work is extended for 2D device (Lime et al. 2008) to compute DIBL and subthreshold swing. Research outputs for DG MOSFET are recently compared with TFET (Zhang et al. 2010), and interesting observations are reported. Caughey-Thomas model is included for calculation (Hariharan et al. 2008) in order to add velocity saturation effect. Localization of surface potential is one of the major constraints for theoretical calculation, and that limitation is intelligently utilized for CS amplifier design (Cobianu et al. 2006). Jacobian elliptic functions and Legendre’s elliptic integral (Hariharan et al. 2008) are the two major mathematical functions used to solve the ID-DG architecture, and quantum–mechanical effect is later added (Abraham et al. 2013). Work on sub 50 nm region is first demonstrated by Ortiz-Conde et al. (2007) after the initial works of lightly doped double-gate devices for long channel length (OrtizConde et al. 2005) incorporating both type of carrier transport mechanisms. Though his model is not applicable for ultra short-channel device, but suitable introduction of F–N tunneling gives proximity of simulated findings with 123 published data. Henceforth, a comparative analysis with Taur’s model along with Ortiz-Conde model is very much required to compute the transconductance of the device, along with differential conductance. In the present work, both types of conductance are computed analytically for short-channel device in nanometric range in presence of high-K dielectrics, where ultrathin dielectric layer is considered in order to incorporate the F–N tunneling factor. We have considered the special symmetric structure from structural point-of-view, as both the dielectric thickness is considered equal. However, when front and back gate biases are considered different, then it can be seen as electrically asymmetric in the otherwise symmetric structure. Pinch-off voltage is also estimated, and percentage change of conductance with structural parameters and applied biases are measured. Results play significant role in put into operation of the device for amplifier design in analog VLSI circuit, which can be realized from the characteristics of the amplification factor; computed for different dielectric materials, and compared with the conventional one. 2 Mathematical formulation For the present work, we start the computation with Poisson’s equation involving the quasi-fermi level for conduction electrons (uc) as   d2 u q u uc ¼ n exp ð1Þ i dz2 es ut Here es represents dielectric constant of the substrate. Since independent gate approximation is considered, so for double-gate architecture, potential difference is given by  es du VGf VGb ¼ þujz¼t=2 ð2Þ Cox dz z¼t=2 where the suffix ‘f’ and ‘b’ represent front-gate and backgate respectively. For carrier transport, we have considered both types of carrier transport, i.e., drift and diffusion; and drain current therefore, can be obtained from the double integral IDS W ¼ 2ln L ZVDS Zus 0 qn dudV n ð3Þ u0 as current is function of both horizontal bias as well as surface potential. Here the electric field f may be expressed in the form Microsystem Technologies sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   2kB Tni / Vc n¼ w exp es /t ð4Þ where the function w denotes coupling factor between front and back gates, uc represents channel voltage. Differentiating field w.r.t channel voltage, we get   on 1 dw 1 qni / Vc exp ¼ ð5Þ oVc 2n dVc n es /t I1 ¼ ts ðw 4 S wD Þ I2 ¼ ZVDS Zu0s dw dudV dVc 0 IDS ZVDS Zus  0 u0 IDS ¼ ln 1 dw 2n dVc  on dudV oVc ð6Þ ZVDS Zu0 0 u0s dw dudV dVc ð8Þ where um \ u0s. After some numerical calculations, we finally get Substituting Eq. (5) in Eq. (3), we get W ¼ 2ln es L um ð7Þ 2 6 2Cox W6 6 L6 4 " 3 4kB TCox ðusD usS Þ 7 þ 7 q 0:5ðusD usS Þ2 7     7  5 u0D VDS u0S þ tkB ni exp exp ut ut VGS ðusD usS Þ # ð9Þ Denoting the two integrals separately as I1 and I2, respectively, we finally obtain Fig. 1 a Differential conductance with VDS for three different VGS for 1 nm SiO2 thickness. b Differential conductance with VDS for three different VGS for 5 nm SiO2 thickness Fig. 2 a Differential conductance with VDS for three different VGS for 1 nm HfO2 thickness. b Differential conductance with VDS for three different VGS for 1 nm HfO2 thickness 123 Microsystem Technologies 3 Results and discussion Using Eq. (4), we have computed and plotted both differential conductance and transconductance of ID-DG MOSFET. Different dielectric materials and their effective thickness are considered at lower nanometric dimension for a pre-specified range of biases where already possible operations are noted in various literatures. Here we have considered three values of gate voltage from 0.8 to 1 V, as below that value, drain current will give leakage current. The device is considered symmetric from structural pointof-view, whereas when back-gate effect is considered and set as different as the front-gate voltage, then the structure is behaved as electrically asymmetric. Also VDS is kept within 1 V as higher drain voltage causes large DIBL after saturation, which may initiate breakdown sooner. With this parametric set-up, simulation is carried out for high-K dielectrics, and compared results with that obtained conventional SiO2 material. Figure 1 shows the variation of differential conductance with drain-to-source voltage (VDS) for three different gate voltages (VGS). From the plot, it is found out that conductance decreases rapidly with horizontal bias, and becomes almost zero at pinch-off, which is achieved at 0.6 V. It is also observed in this case that lowering the gate Table 1 Percentage change of differential conductance for different thickness of HfO2 123 VDS (V) voltage decreases conductance, as less gate voltage drives the device towards subthreshold region. A comparative study between Fig. 1a, b reveal that increasing the dielectric thickness lowers the conductance. This is expected as higher dielectric barrier reduces the gate effect on control, which, in turn, decreases drain current at active condition. But for a given gate voltage, rate of reduction of drain current is different for equal change in dielectric thickness. Figures 2a, b represent the same for high-K materials (HfO2 and TiO2). A comparative analysis reveals that higher electric permittivity enhances the conductance in absence of VDS, or at very low value of it; when applied biases and thickness are kept identical. But differential conductance falls very rapidly with VDS which speaks for early pinch-off condition. This percentage change of ‘gd’ is represented in Tables 1 and 2. Figure 3 shows the variation of transconductance with VGS for different dielectrics, and computation is also carried out for different horizontal bias also. Figure 3a shows the transconductance for HfO2, whereas data for TiO2 is plotted in Fig. 3b. Result for conventional dielectric (SiO2) is plotted in Fig. 3c. From the plot, it is seen that higher drain voltage causes a rapid increase in transconductance, whereas lower drain bias leads to the saturated value. A VGS = 0.8 V % change for 1–3 nm % change for 3–5 nm 1 nm 3 nm 5 nm 0.05 0.00757 0.00398 0.00283 0.4741969 0.2877791 0.1 0.00448 0.00265 0.00196 0.4089497 0.2604318 0.2 0.3 0.00098 6.8E-05 0.00074 5.9E-05 0.00059 5.1E-05 0.2445362 0.1305917 0.1989346 0.1311257 0.4 1.7E-06 1.6E-06 1.5E-06 0.0372072 0.0481845 VDS (V) VGS = 0.9 V % change for 1–3 nm % change for 3–5 nm 1 nm 3 nm 5 nm 0.05 0.01581 0.00711 0.0048 0.5504602 0.3246989 0.1 0.0114 0.00548 0.00378 0.5198847 0.3095474 0.2 0.00448 0.00264 0.00195 0.4095957 0.2610687 0.3 0.00098 0.00075 0.0006 0.2399865 0.1951623 0.4 6.9E-05 6E-05 5.3E-05 0.1192906 0.1222915 VDS (V) VGS = 1.0 V % change for 1–3 nm % change for 3–5 nm 0.5874175 0.3452412 1 nm 3 nm 5 nm 0.05 0.02574 0.01062 0.00695 0.1 0.02062 0.00882 0.00585 0.5721205 0.3367194 0.2 0.0114 0.00547 0.00377 0.5203096 0.3102726 0.3 0.00448 0.00264 0.00195 0.4097157 0.2608929 0.4 0.00099 0.00076 0.00061 0.2336544 0.1894848 Microsystem Technologies Table 2 Differential conductance for different materials having effective thickness 1 nm VGS 0.8 0.9 1 Dielectric VDS 0.05 V 0.1 V 0.2 V 0.3 V SiO2 0.00389113 0.00308079 0.001613167 0.000499025 HfO2 0.00756961 0.00447921 0.00097916 6.80295E-05 TiO2 0.01430593 0.0074071 0.001320094 9.64E-05 SiO2 0.00561107 0.00473788 0.003082118 0.001614583 HfO2 0.01581014 0.01140484 0.004478247 0.000982837 TiO2 0.03634323 0.02410342 0.007406588 0.001325923 SiO2 0.00741917 0.00650678 0.004738845 0.003083703 HfO2 0.02573809 0.02061968 0.011401129 0.004480672 TiO2 0.0657776 0.05038726 0.024096217 0.007413728 Fig. 3 a Transconductance with VGS for three different VDS for 1 nm HfO2 thickness. b Transconductance with VGS for three different VDS for 1 nm TiO2 thickness. c Transconductance with VGS for three different VDS for 1 nm SiO2 thickness 123 Microsystem Technologies Table 3 Percentage change of transconductance for different dielectric thickness Table 4 Transconductance for different materials at 1 nm effective thickness VGS (V) VDS = 0.1 V % change for 3–5 nm 1 nm 3 nm 5 nm 0.6 0.00358 0.000317 0.000258 0.91128683 0.187385377 0.7 0.01652 0.001357 0.00102 0.91788547 0.247746918 0.8 0.0333 0.002452 0.001645 0.92636941 0.32912764 VGS (V) VDS = 0.2 V % change for 1–3 nm % change for 3–5 nm 1 nm 3 nm 5 nm 0.6 0.00378 0.000336 0.000274 0.91101998 0.183630294 0.7 0.02009 0.001673 0.001277 0.9167292 0.236683621 0.8 0.0498 0.001812 0.001268 0.96360871 0.300524044 VGS (V) VDS = 0.4 V % change for 1–3 nm % change for 3–5 nm 0.183429351 1 nm 3 nm 5 nm 0.6 0.00378 0.000337 0.000275 0.91100792 0.7 0.0203 0.001692 0.001294 0.91662054 0.235309654 0.8 0.0536 0.004144 0.002939 0.9226803 0.290905976 VDS Dielectric VGS 0.1 0.2 0.4 0.6 V 0.7 V 0.8 V 0.9 V 1V SiO2 0.00217 0.00545 0.00732 0.00829 0.00884 HfO2 0.003577 0.016521 0.033303 0.04519 0.051778 TiO2 0.00398 0.024867 0.072997 0.123459 0.154321 SiO2 0.00235 0.00761 0.01276 0.01561 0.01713 HfO2 0.003777 0.020092 0.049799 0.07846 0.096957 TiO2 0.004181 0.028839 0.097826 0.196371 0.277716 SiO2 0.00236 0.00781 0.01512 0.02321 0.0299 HfO2 0.003782 0.020298 0.053597 0.098583 0.146673 TiO2 0.004186 0.029046 0.102033 0.2252 0.374346 comparative study also reflects that the saturation of transconductance is vivid for SiO2, whereas it is less for high-K materials. This comparative analysis is represented in tabular form also in Tables 3 and 4. In Fig. 4, we have calculated the effect of various dielectrics on transconductance for VDS = 0.4 V. At higher value of gate voltage, the effect becomes significant, whereas below 0.6 V, dielectric variation is immaterial. Comparative analysis is also given in Table 3, and compared with published data, as shown in Table 4. It is found from Table 4 that our simulated findings are in very close agreement with the available literature (Pradhan et al. 2014; Prasher et al. 2013), and we have found out the percentage variation for change in both material thicknesses, applied bias as well as calculated w.r.t conventional materials. Here for our proposed structure, the substrate is silicon having lattice constant 5.431 Å and the layer of TiO2 123 % change for 1–3 nm Fig. 4 Comparison of transconductance for various dielectrics, results are compared with SiO2 Microsystem Technologies Table 5 Comparative analysis for differential conductance A Reference VDS VGS (V) Pradhan et al. (2014) 0.1 0.5 gd (mho/m) 1 9 10-2 -3 gd from our work 1.63 9 102 0.2 2 9 10 3.57 0.4 5 9 10-4 1.64 9 10-3 0.1 -7 2 9 10 3.51 9 10-5 0.2 1.2 9 10-7 7.50 9 10-7 0.4 -8 0.1 9 9 10 2.80 9 10-10 B Reference EOT gd (mho/m) gd from our work Prasher et al. (2013) 5 10-9 1.116 9 10-11 -8 1.117 9 10-11 -7 1.118 9 10-11 -5 1.119 9 10-11 3.5 10 2 10 0.5 Table 6 Comparative analysis for transconductance 10 A Reference VGS VDS (V) Pradhan et al. (2014) 0.1 0.5 gm (mho/m) 5 9 10-4 3.5 9 10-4 2 9 10 -3 1.6 9 10-2 3 9 10 -3 3.45 9 10-1 8 9 10-4 3.42 9 10-4 1.5 9 10 -3 1.57 9 10-2 9 9 10 -4 3.37 9 10-1 0.2 0.4 0.1 0.1 0.2 gm from our work 0.4 B Reference Prasher et al. (2013) EOT gm from our work 5 2500 1800 3.5 3800 2500 2 0.5 having lattice constant 3.78 Å and 9.42 Å (growth direction) has to be grown on this substrate. Since the lattice constants of substrate and grown layer have significant differences, so this will lead to lattice mismatch (42.346%) related defect states. To counter with this problem, use of buffer layer based epitaxial growth is a very good solution. Here the most suitable buffer layer is strontium titanate (SrTiO3) which has a very low lattice mismatch (1.68%) with silicon (100) substrate and also the lattice mismatch between anatase TiO2 and strontium titanate is low (- 3.06%) (McDaniel et al. 2012). Now by the application of strained layer epitaxy the effective mismatch between titanium oxide and buffered silicon (100) will be smaller (- 1.42%). By this growth process, several nanometer of gm (mho/m) 8700 4100 32,500 13,900 TiO2 can be grown on top of buffered silicon which will remain ordered. An important point to be noted that the effect of SrTiO3 on device parameters can be neglected since the thickness of SrTiO3 is extremely small. The dielectric constants considered in this paper, is the effective dielectric constant for all high-K materials (Tables 5 and 6). Next we have plotted voltage gain (l) of DG-MOSFET having different dielectrics with VDS in Fig. 5. From the plot, it is seen that voltage gain (l) is almost linearly increasing with increasing VDS and it is highest for TiO2 owing to the fact that TiO2 provides higher transconductance (gm) than SiO2 and HfO2. Point to be noted in this context that while calculating Voltage gain (l) we have 123 Microsystem Technologies bias requirement. Results are critical for implementing the device for analog or digital applications. References Fig. 5 Voltage gain with drain-to-source voltage (VDS) for different dielectrics Table 7 Differential resistance, amplification factor and transconductance for different VDS l VDS ID (mA) rd (KX) gm (mho) 0.1 0.916 0.109 0.0291 0.2 1.08 0.185 0.0435 0.3 1.09 0.276 0.0509 14.1 0.4 1.09 0.368 0.0564 20.8 3.18 8.03 kept insulating oxide thickness constant at 1 nm and Vgs constant at 0.8 V. The result is also summarized (Table 7) to understand the mutual dependence between drain resistance, transconductance and voltage gain. 4 Conclusion Differential conductance and transconductance of doublegate MOSFET are analytically computed and plotted as a combination of optimized applied bias conditions, where nanometric dielectric thickness is considered. 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