Generalized Constraint Generation for Analog Circuit Design Edoardo Charbon, Enrico Malavasiy and Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of California, Berkeley y Dip. di Elettronica e Informatica, Universit a di Padova, Italy Abstract A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from highlevel performance speci cations by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information. 1 Introduction The design of analog circuits is often a dicult task compared with a digital one of similar complexity because of the higher number of speci cations and the importance of second order e ects. In addition, the continuously growing complexity of analog integrated circuits has required a better control over the design quality and the rede nition of tasks like module generation and oorplanning. The performances of analog circuits can be extremely sensitive to parasitic e ects. In particular, due to continuous reduction of the size of circuit devices, layout induced parasitics increasingly in uence the circuit behavior. The performance degradation of a circuit due to layout parasitics can be modeled using performance sensitivities [1]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [2]. Techniques [3, 4, 5, 6, 7] have been proposed for a constraint-basedapproach to the layout of analog integrated circuits. In these approaches a constraint generator is used to map a set of high-level performance speci cations onto a set of bounds, which are then used during the layout synthesis to control parasitics. The constraint generation problem has been rst formally stated in [2]. In this formulation, performance sensitivities are used to map directly performance speci cations onto a set of constraints on critical parasitics. Although important, interconnect induced parasitics are not the only source of degradation of circuit performance. Another class of parasitics, namely those induced by the topology of the circuit, is a relevant, and often dominant source of non-ideal circuit behavior. Generally, constraints on the layout topology are imposed by the designer based on experience. However in complex designs, such as mixed-signal circuits, this task may become dicult if not impossible, due to the interactions between circuit components and parasitics. During the synthesis of complex mixed-signal systems [8] it is often required to map high-level performance speci cations onto several distinct sets of layout constraints. The constraint generation process should therefore be exible. In this paper a generalization of the constraint generation problem for the layout synthesis of analog integrated circuits is presented. A uni ed de nitionstrategy is also de nedto express and manipulate performance speci cations, so as to maximize the exibility of the constraint-based tools used during the synthesis phase. The set of layout constraints, in its most general form, includes two types of constraints: topological and parasitic constraints. Topological constraints relate to the relative position and orientation of the circuit components. Parasitic constraints are referred to as a bound to the value or to the mismatch of parasitic components. We show how to manipulate performance sensitivities to model the performance degradation due to parasitic mismatch. The sensitivity information, along with estimates on the minimum and maximum possible parasitics, is then used to determine critical parasitic mismatches. Topological constraints are generated by modeling device mismatch as a parasitic mismatch, thus allowing us to identify all critical matching constraints in the circuit. Symmetry constraints, a subset of all matching constraints, are identi ed by mapping the circuit onto a weighted undirected graph. The nodes of the graph represent the circuit devices, the edges the connectivity and the degree of matching. The sources of the graph are the inputs, the virtual and real grounds being the sinks. The symmetry constraints are obtained by traversing the graph on two paths simultaneously from sources to sinks, the search direction being determined by device matching considerations and connectivity. The ow diagram of the constraint generation process is shown in gure 1. From hardware and performance description a sensitivity analysis of the circuit is performed using mixed symbolic / numerical techniques [9, 10]. Using performance sensitivity information and a priori estimates of minimum and maximum parasitic values, the subset of critical parasitics is detected. A quadratic programming approach is then used to compute bounds on critical parasitics and to locate matching constraints, so that the total performance degradation collectively induced by all interconnect parasitics does not exceed the speci cations. The circuit is then mapped onto a weighted graph and solved to obtain all symmetry constraints. Finally, all constraints undergo a technology mapping step to compute detailed geometrical bounds on all layout components. Thus all speci cations on the yield properties of the nal circuit can be satis ed. The paper is structured as follows. The foundations of the constraint generation problem and the principles of the computation of performance sensitivities are reviewed in section 2. The algorithms for the generation of parasitic and topological constraints are outlined in sections 3 and 4. Benchmark ex- De ne ji + = ji for positive values of the sensitivity. Alternatively ji ? = ? ji for the negative ones. The positive and negative components of the performance degradation 4 i+ and 4 i? with respect to all parasitics belonging to the set f j g are, in rst approximation X i+ X i? 4 i+ = 4 i? = (4) j j j j S S Hardware description Symbolic performance representation S S W Sensitivity computation p W Critical parasitics and matchings detection Virtual / real grounds detection W p S ; W Generation of bounds on parasitics and matchings Graph resolution Generation of symmetry constraints Technology mapping Complete set of constraints p S j j The distinction between positive and negative components of the degradation must be considered throughout the performance generation process to obtain constraints which re ect a worst-case analysis. For simplicity of notation the sign is dropped hereafter, although it is implicitly assumed that all operations are carried out. In addition, technology-related process variations can induce deviations of the performance functions. These e ects can be taken into account by simply replacing nominal values of sensitivities with worst-case values as suggested in [2]. The parasitic constraint generation is based on this approximation as shown in section 3. Let us now consider the degradation of performance i due to parasitic mismatch. Let 1 2 be two matched parasitics. Although they are nominally equal, they actually di er by a small mismatch 4 . We introduce the following notation: n = ( 1 + 2) 2 (5) 4 = ( 1 ? 2) so that 1 and 2 can be expressed in terms of their average value and their mismatch 4 as: 1 = + 42p 2 = ? 42p The sensitivities of performance i with respect to and 4 are respectively W Figure 1: Flow diagram of the constraint generation process. p ;p p amples showing the suitability of our approach are discussed in section 5. ; j ; :::; N ; :::; N p pj  p (bound) ; j = l 6= (1) To guarantee the ful llment of performance constraints, equation (2) must be satis ed 8 (2) 4 i4 i 4 i represents the total and 4 i the maximum allowed degradation of performance i with respect to all parasitics and mismatches. In this formulation all the parameters which can be in uenced during the layout synthesis are considered. Interconnect parasitics, cross-coupling induced by interconnections, parasitic as well as device mismatches in any of their parameters must ultimately satisfy equation (1). pk W p ; k W l: ; W 2.2 Use of Sensitivities to Model Performance Constraints Assuming that performancefunctions are close to their nominal values, then linear approximations of their dependence on parasitics can be obtained using sensitivities. Let us consider a parasitic element j , with nominal zero value. The sensitivity of performance i with respect to j is de ned as   i i (3) = j p W S @W @pj p p 8 < : i Sp = : pj =0 p ; p p p p @Wi @p = + @Wi @p1 @p1 @p : p @Wi @p2 @p2 @p = + i S1 p i S2 i ? i @Wi @Wi @p1 @Wi @p2 i 1 2 4 = @ 4 p = @p1 @ 4 p + @p2 @ 4 p = 2 When matching constraints involve simultaneously more than two parasitics, a more general de nition of the average value and mismatch (5) is adopted. For a group of parasitics p1 ; p2 ;


; pn , their average value p and their mutual mismatches 4pjk are de ned as follows: S S 8 n < = 1X j : i: W W = p W For a set of performances f i g = 1 w and a set of parasitics f j g = 1 p , parasitic constraint generation is de ned as the process of creating a suitable set of constraints on f j g: p p p p 2.1 General Problem Formulation ; i p p p 2 Constraint Generation W p p n (6) pj =1 4 jk = j ? k = 1


Consequently, the sensitivities of performance to and 4 jk are p p p j; k ; ; n: Wi p 8 > < > > : p = i Sp S @Wi = n  X @Wi @pj @pj with respect  X n = i Sj j =1 (7) ( ji ? ki ) 4jk = 4 jk = 2 Given two parasitics 1 and 2 , their contribution 4 i to the degradation of performance i is, in rst approximation 4 i = 1i 1 + 2i 2 Consequently, i i 4 i = pi ( 1 + 2 ) + 24 ( 1 ? 2 ) = 2 pi + 24 4 (8) It is evident that if i i (9) p  4 @p j =1 S @Wi i S @ @p S p p p W W W S p S p : S S W S p p p S p S ; S p p: the contribution of p1 ; p2 to the degradation of Wi can be signi cantly reduced by increasing the correlation between the two parasitics, i.e. by enforcing the matching between them. Therefore matching constraints can be automatically determined on the ground of the relative importance of sensitivity on the average value and sensitivity on mismatch in the expression of performance degradation (8). The inequality (9) can be used to distinguish between the cases when mismatches yield signi cant degradations and the cases when parasitic correlation has little or no in uence on the performance whatsoever. Matching constraints are often expressed as a di erence between parameter ratios rather than of simple parameters. This is often the case when trying to establish speci c geometric constraints from topological constraints during the technology mapping process. Given two independent variables x and y and a performance W (x=y) then y2 @W = (S W + SyW ); (10) @ (x=y) y ? x x and thus, the sensitivity of performance W with respect to the mismatch 4 xy = xy11 ? xy22 can be written as W W y12 W x = ( Sx1 =y1 ? Sx2 =y2 ) = W W S4 y 2 2 (y1 ? x1 ) (Sx1 + Sy1 ) S(Wx=y) = ? 2 (y y2? x ) (SxW2 + SyW2 ): 2 (11) Throughout this analysis it was assumed that xi and yi are independent variables. This is usually the case in layout since orthogonal geometries, such as channel width and length in MOS transistors, are generally in uenced by independent sources. 2 2 2.3 Canonical Representation of Performance A generalized expression for the computation of sensitivities from a set of arbitrary performances has been derived in [11, 12]. This formulation has been used by us to represent all performances analyzed in a compact and rigorous way, thus ensuring exibility of our design tools. For completeness the formulation has been reviewed hereafter. Let us consider an arbitrary performance W , let x be a vector of design parameters (e.g. capacitances, MOS channel length, etc.), y a vector of circuit variables (e.g. voltages, charges, etc.), and ! an independent variable (e.g. frequency, time). Then the equation g(x; y(x; !); !) (12) fully describes the performance W . De ne now the characteristic function of performance W as h(x; y(x; !); !) = 0 (13) The characteristic function h represents implicitly the operating point at which the sensitivity computations have to be performed. The performance sensitivity of the performance W with respect to a set of design parameters x is y ? x y @g @ T @g +@ @ SW = @ x x y y y y ( @g @g T @ )   @h @ T @h @! + @ @! + @h @h T @ @ @ @ @! + @ @! x The expression @@fy has the same meaning of f : Rn ! R. y x x (14) rf (y), if 3 Generating Parasitic Constraints 3.1 Bounding Constraints At an early stage of the design, generally no precise information is available on the exact values of the parasitics. However very reasonable assumptions can be made on their range. A bound on the value of a parasitic, or bounding constraint should be therefore within this range, thus ensuring realizability of the circuit. In symbols pj(min)  pj(bound)  p(jmax) ; 8j: (15) pj(min) and pj(max) are determined by technology considerations and pj(bound) is the bounding constraint to be computed. From this information, using expression (4), one can obtain the minimum and maximum performance degradation induced by all parasitics. Furthermore, we discard those parasitics whose cumulative e ect on performancedegradationis negligible, compared to the maximumallowed performancedegradation[1]. For the remaining critical parasitics, bounds can be automatically generated as a result of a constrained optimization, the objective being a model of the tool exibility. 3.2 Matching Constraints The general methodology to extract matching constraints can be de ned as follows. Let M be a matching cluster, i.e. a group of circuit components constrained by matching requirements. Performance sensitivities with respect toP parasitic mismatch 4pij = pi ? pj and average p(M ) = n1 j2M pj , are computed using the techniques outlined in section 2.2. The range of variation of the average and mismatch is computed as 1 X p(min)  p(M )  1 X p(max) ; j j n n j2M j2M (mismatch) pi(min) ? pj(max)  4pij  pi(max) ? pj(min) ; 8j: (16) One can recognize that the constraint generation problem for the parasitic average and for a simple parasitic component are identical. The constraint generation for parasitic mismatch on the other hand is handled in a slightly di erent manner. Suppose a solution for 4pij has a negative value, then this term could possibly generate cancellation in the approximation formula for performance degradation 4Wi in (4), thus creating false results. To eliminate this problem, the variable 4pij is split into two, 4pij + and 4pij ? , which are consequently added as a contributionto the approximate negative and positive components of the performance degradation. 4pij ? and 4pij + represent the lower- and upper-bound of the allowed mismatch. This approach is often expensive computationally, since it involves the generation of a large number of mismatches, and the constraint generation problem has to be solved on a large set of parameters. A more ecient approach is to use the matching requirement expressed in (9). For every couple of parasitics, their mismatch and average sensitivities are computed and compared against each other. If relation (9) holds, the original parasitics are discarded and substitutedby their averagevalue and the mismatch. Otherwise they are kept and mismatches between them are not considered. With this approach, the computational cost of the constraintgenerationproblem is a ected slightly, only one being the parameter added for each group of three or more matched parasitics. 4 Generating Topological Constraints 4.1 Device Matching The importance of device matching in integrated circuits has been shown not only for active but also for passive elements [13, 14]. Designers generally impose matching constraints on circuit devices to ensure that voltage and current mismatches in these devices be bounded. These constraints can be mapped directly onto constraints on the geometry of the physical implementations [14]. For this reason device matching constraints are usually of qualitative nature, mostly dictated by the expertise of the designer. We propose a quantitative approach to the generation of device matching constraints based on the principles introduced in section 2.2. Assume for simplicity but without loss of generality that all active devices can be represented by a two-port. Furthermore, assume that a model relating the output to the input port is available and that only one performance W is considered. Let VDi and IDi be the quantities characterizing respectively input and output of device Di . Let IDi = f (P0 + P;VDI ), where P is the vector of all deviationsfrom a nominalvalue P0, of all technologicalparameters a ecting the device. Suppose the set of sensitivities fSPik g of performance W with respect to all vector elements of P is available. Then, in rst approximation, the degradation 4WDi of performance W with respect to the technological deviations for device Di can be expressed as 4 WDi = XS k Pik Pk : (17) For reasons that will be clear later (equation 19), the sign of sensitivities has been dropped. Consider now a pair of devices Di and Dj , then the degradation due to the parameter mismatch of the devices can be computed as 4 WDij = S4Pk 4Pk : (18) X k The S4Pk are computed using (7) and 4Pk is the kth component of the vector di erence P(Di) ? P(Dj) . Assume that the 4Pk 's are independent random variables with zero mean. The variance of the degradation of performance W with respect to the variances of the mismatches of all technological parameters relevant to the pair of devices Di and Dj , is computed as 2 (4WDij ) = X jS4 k Pk j2 2 (4Pk ): (19) Consider for instance a pair of matched MOS transistors. The variance of the degradationdue to technologicalmismatchescan be expressed as 2 (4Wm12 ) = S4W 2 2 (4W ) + S4L 2 2 (4L)+ +S4Cox 2 2 (4Cox ) + S4n 2 2 (4n ) + S4VT O 2 2 (4VTO ): W , L, Cox , n and VTO are respectivelychannel width, channel length, gate oxide capacitance, mobility and threshold voltage of the transistors. In [14] a direct relation has been shown between these variances and the relative orientation and distance between device pairs. This information can be used to translate the maximum allowed performance degradation into the physical separation and relative orientation between pairs of devices. In order to do this, estimates of the minimum and maximum attainable variances for a particular process are needed, so that an upper- and lower-bound of the performance degradation for each pair of devices can be determined. The sum of all degradations due to each pair of devices in the circuit should be added to equation (4). The constrained optimization is solved to nd the actual variances of each parameter. Consequently numerical values for distances and orientations. Notice that, for consistency, the standard deviation should be added to (4), thus making the optimization harder and more time consuming. In order to avoid this additional complexity, the expression for the standard deviation is linearized after substituting the single parameter variances with analytical models in the geometric quantities of interest. Thus a linear expression for the standard deviation of the degradation referred to the pair is obtained as (20) 2 (4Wmij ) ' Aij dij + Bij rij : A and B are quantities which depend upon the performance sensitivity of W with respect to the pair's technology parameters. dij and rij represent respectively the distance and relative rotation of devices mi and mj . Also in this case a simpli cation mechanism similar to the one proposed in [2] is used for computing the criticality of the mimatches. p 4.2 Device and Interconnect Symmetry Symmetry is used in the layout of analog integrated circuits to minimize the e ects of mismatched parasitics on circuit performance. With symmetric placement and routing di erential signal paths can be matched optimally. The detection of topological symmetry constraints in an automatic fashion has been traditionally associated with pattern recognition or expert system based techniques. We propose a novel method based on our quantitative approach for the computation of parasitic and device matching constraints combined with information on the electrical properties of the circuit nets. The goal of topological symmetry is to facilitate the respect of matching constraints on parasitics and / or devices. Hence priority to undergo a symmetrization process should be given to those entities (devices or interconnect) on which matching constraints have been imposed. A second requirement is that these entities belong to distinct differential signal paths in order to maximally balance the signals circulating in the circuit. A third requirement is that symmetric signal paths ultimately converge to a virtual or real signal ground. These three basic requirements have been used to drive a graph-based search algorithm described as follows 1. 2. 3. 4. 5. map_onto_graph; add_edges; create_sink_nodes; set_starting_nodes; until (all_nodes_visited) { if (termination_condition) { find_new_starting_node; continue; } else { search_matched_nodes; run_through_reconvergent_path; if (not_degenerate) continue; if (semi-degenerate && super_virtual) continue; invalidate_path; } } 6. exit M7 M1 M8 M2 1 1 4 4 match M6 M5 3 3 match M2 Figure 3: Semi-degenerate path. 2 2 Starting point 2 match M1 Inputs Degenerate path M4 M3 Starting point 1 match B A Start 1 1 match Figure 2: Degenerate path. In the rst step the circuit description is converted into an undirected graph, whose nodes represent the (active and passive) device and edges connectivity. In the second step the matching constraints are introduced into the graph by adding constraint edges to it. In the third step edges associated with real and virtual grounds are found and are set to be the graph sinks. This operation is automatically performed in all nets by comparing common and di erential mode gains with respect to the input. After initializing the search, all nodes are searched until the maximum number of symmetric paths has been found, the termination condition for each path being the presence of a virtual or a real ground. In the rst case the symmetry path is called reconvergent. In order to be completely satis ed, the symmetric search paths must merge and proceed on the graph until a real ground is found. In the second case the symmetry constraints for the current search path(s) are completely satis ed. Thus the search ends and a new one begins from another couple of non-terminal nodes satisfying matching constraints. If a degenerate path is detected the search path is invalidated, thus nulling the symmetry constraints found associated with it. A degenerate con guration occurs whenever a device on a search path has other devices matched to it on an incompatible search path (M5 and M6 in gure 2). Thus separate symmetry constraints interfere with each other. If a semi-degenerate path is detected, i.e. a node is found to be at both sides of the symmetry axis (M1 and M2 in gure 3), a pair of edges associated with a super-virtual ground is searched. The symmetry constraint associated with the current search path is invalidated when no such edges are found. A supervirtual ground is de ned as a pair of signal nets such that, if connected by a series of two identical resistors, the middle point becomes a virtual ground. The nal steps are used to map all search paths onto actual topological symmetry constraints. Figure 2 shows a simple circuit and the graph associated with it, when a degeneratepath exists. Nodes \1" are visited rst. Since a terminal condition occurs (real ground), the search continues in the opposite direction. After one iteration at nodes \2", the search proceeds towards the nodes \3", however since neither nodes are in a contiguous path a degenerate situation occurs. The last section of the path is therefore invalidated and the search continues from nodes \4", ending at the top, when a terminal condition occurs. Thus the search is complete resulting in the symmetry constraints M1-M2; M3-M4 and M7-M8. Figure 3 illustrates a semi-degenerate situation. In this case electrical nets A and B clearly form a super-virtual ground. Thus, the constraint cycle in the symmetry constraint dependence is eliminated and the symmetry constraint is accepted. 5 Results The algorithms outlined in this paper have been tested on a wide range of circuits, selected from a set of commonly used industrial applications. Because of limited space, we will discuss in detail two particularly signi cant circuits to highlight the features of the proposed algorithms. For the computation of voltage sensitivities, standard analysis methods available in SPICE3 [15] have been used. Performance sensitivities are computed from circuit variable sensitivities using the principles presented in section 2.3. The sensitivity information required for matching and symmetry constraints computations is obtained from performance sensitivities using the manipulations outlined in section 2.2. Presently available are dc, ac and transient analysis. The set of design parameters currently supported are resistances, substrate capacitances, capacitive coupling, inductances, mutual inductances, base-emitter junction area, MOS channel length and width. Class AB ampli er Consider the power ampli er \ab", depicted in gure 4. The Vdd M12 7 M13 6 M14 8 M15 Out 9 In+ 3 11 2 M3 I1 M7 5 In− 4 M5 M1 M6 M2 10 12 M4 M8 13 14 M11 M10 M9 Vss Figure 4: Class AB ampli er \ab". performances analyzed are o set voltage, unity gain bandwidth, phase margin and low frequency gain. Table 1 reports nominal values, positive and negative constraints on the degradation of each performance. Table 1 shows some of the most critical parasitics and the bounds on the mismatch for capacitive and resistive parasitics. The CPU time for the computation of all constraints was 7.4 seconds on a DECstation 5000/125. Notice that parasitic capacitances are de ned by the nets they are connected to. Resistances on the other hand, refer to the branches in which they are introduced. Table 2 illustrates each net type as evaluated by the program. Notice in particular the evaluation of nets 10 and 11, correctly assigned to the type \virtual ground". In this case the knowledge of the nature Clocked comparator Consider now the comparator \fastcomp", depicted in gure 5. This circuit is of particular interest because of clk Vdd MP1 MP3 MP4 MP2 MP14 11 MP6 performance constraints Performance Nominal value 4W + 4W ? O set Voltage 14 mV -2 mV 8 mV U.G. bandwidth 500 MHz -3 MHz 3 MHz Phase margin 106 deg -3deg 3deg L.F. gain 28 dB -3 dB 1 capacitive mismatch Net pair 1 Net pair 2 bound limits 3-9 4-6 62.41fF  100fF 11 - gnd 10 - gnd 80.97fF  100fF resistive mismatch branch 1 branch 2 bound limits Vdd-m12.s Vdd-m14.s .100  10 Vss-m9.s Vss-m10.s .100  10 10-m7.s 11-m8.s 4.201  10 10-m6.s 11-m5.s 4.201  10 12-m4.s 2-m3.s 25.563  50 12-m2.s 2-m1.s 25.563  50 Table 1: \ab": Bounds on the resistive and capacitive mismatch. Note: \.s" indicates the source of a transistor. net 0 2 3 4 5 6 7 8 type G S I I S S S S net 9 10 11 12 13 14 Vdd Vss type O V V S S G G G Table 2: \ab": Automatic net type assignment (S = Signal, G = Supply/Gnd, V = Virtual Gnd, I = Input, O = Output). Device matching constraints rel. rotation devices no m12 - m14 no m9 - m10 no m5 - m6 no m7 - m8 yes m1 - m2 yes m3 - m4 Symmetry constraints axis Symmetric devices 0 m1 - m2; m3 - m4; m7 - m8; m9 - m10 1 m12 - m14; m13 - m15; m5 - m6 Table 3: \ab": Topological constraints. distance 200  200  200  200  200  200  of these nets was crucial to correctly recognize symmetry constraints, otherwise dicult to individuate due to the irregular topology of the circuit. In conclusion, table 3 shows a summary of the topological constraints obtained using the techniques described throughout the paper. For each matching constraint the corresponding values for d and r are given based on the a standard scmos 2m technology. The CPU time for the topological symmetry computation was 0.1 seconds on a DECstation 5000/125. Notice the distinct symmetries found by our program, one for each sub-circuit of the ampli er. Generally the axes of these symmetries are superimposed to achieve more compact layouts. MP7 8 7 MN11 MP5 MP10 MP8 3 4 MN1 MN2 1 2 5 MP9 In+ MN3 6 In− MP11 MN4 MP12 MP13 9 Vo+ 10 12 10 MN9 Gnd MN5 13 Vo− 9 MN7 MN6 MN8 MN10 11 Figure 5: Clocked comparator \fastcomp". the presence of several irregular structures creating semidegenerate paths. Another point of interest is the fact that the analog circuit is switched. Thus the topological generation mechanism is to be tested in a circuit which operates in a strongly non-linear region. In addition, there are no virtual grounds in the circuit, thus making the symmetry constraint generation more dicult. Table 4 lists the performances of interest for this circuit and the used constraints. The calculated mismatches are shown in table 4. The CPU time required was 33.1 seconds on a DECstation 5000/125. Notice that major contribution to the o set is given by parasitic resistances degenerating the input stage devices. As expected, the input source followers (MP10-11 and MP8-9) are less critical than the high-gain pairs (MN3-4 and MP2-3). Table 6 shows the results of the topological constraint generation. The required CPU time was 0.5 seconds on a DECstation 5000/125. Notice how all semi-degenerate con gurations have been resolved, yielding three groups of symmetric devices, which have to be placed necessarily on the same axis in order to minimize the o set. 6 Conclusion and Future Work A generalized approach to the automatic generation of parasitic and topological constraints for designing analog integrated circuits has been presented. The method uses a symbolic representation of the performance as sucient information for the computation of numerical values for the sensitivities, which are then used for the generation of bounding and matching constraints. Topological constraints are computed using the matching information on devices as well as graph-based techniques for identifying symmetries. Constraint-based layout synthesis tools can exploit this information to drive the layout optimization to a con g- performance constraints Nominal value 4W + 4W ? 20mV -3 mV 3 mV 2.58ns 1 ns 2.92ns 1 ns capacitive mismatch Net pair 1 Net pair 2 bound limits 7 - gnd 8 - gnd 27.15fF  100fF 7 - vdd 8 - vdd 27.15fF  100fF 1-5 2-6 68.32fF  100fF resistive mismatch branch 1 branch 2 bound limits MN3.s-gnd MN4.s-gnd .100 1 MP2.s-vdd MP3.s-vdd 7.708  50 MP8.s-Vdd MP10.s-Vdd 42.90  50 Table 4: \fastcomp": Bounds on capacitive and resistive mismatch. Note: \.s" indicates the source of a transistor. net 0 1 2 3 4 5 6 7 8 type G I I S S S S S S net 9 10 11 12 13 clk Vdd Gnd type S S S O O S G G Table 5: \fastcomp": Automatic net type assignment (S = Signal, G = Supply/Gnd, V = Virtual Gnd, I = Input, O = Output). Performance O set Voltage Delay (LH) Delay (HL) Device matching constraints rel. rotation devices no MN3 MN4 no MP2 MP3 yes MP8 MP10 Symmetry constraints axis Symmetric devices 0 MN9 - MN10; MN6 - MN7 1 MP6 - MP7; MP1 - MP4; MP2 - MP3 2 MP9 - MP11; MP8 - MP10; MN1 - MN2; MN3 - MN4 Table 6: \fastcomp": Topological constraints. distance 100  100  100  uration in which high-level performance speci cations can be met. Future work includes the expansion of the numerical sensitivity computation tool to account for new parameters and analyses and its integration into the new topdown, constraint-driven circuit synthesis framework currently under development. 7 Acknowledgements This research has been partially supported by DARPA and SRC. The rst author has been supported by a grant of Asea Brown Boveri, inc. Baden, Switzerland. The authors would like to thank Umakanta Choudhury who rst formalized the approach and whose suggestions were extremely useful. The authors would also like to thank Prof. R. Meyer of UC-Berkeley and Dr. A. Gandini of CSELT, Torino, Italy for providing the examples presented in this work. References [1] U. Choudhury and A. Sangiovanni-Vincentelli, \Use of Performance Sensitivities in Routing of Analog Circuits", in Proc. IEEE Int. Symposium on Circuits and Systems, pp. 348{351, May 1990. [2] U. Choudhury and A. Sangiovanni-Vincentelli, \Constraint Generation for Routing Analog Circuits", in Proc. Design Automation Conference, pp. 561{566, June 1990. [3] E. Malavasi, D. Pandini and V. Liberali, \Optimum Stacked Layout for Analog CMOS ICs", in Proc. IEEE Custom Integrated Circuits Conference, pp. 1711{1714, May 1993. [4] U. Choudhury and A. Sangiovanni-Vincentelli, \Constraint-Based Channel Routing for Analog and Mixed-Analog Digital Circuits", in Proc. IEEE ICCAD, pp. 198{201, November 1990. [5] E. Malavasi, U. Choudhury and A. SangiovanniVincentelli, \A Routing Methodology for Analog Integrated Circuits", in Proc. IEEE ICCAD, pp. 202{205, November 1990. [6] E. Charbon, E. Malavasi, U. Choudhury, A. Casotto and A. Sangiovanni-Vincentelli, \A ConstraintDriven Placement Methodology for Analog Integrated Circuits", in Proc. IEEE Custom Integrated Circuits Conference, pp. 2821{2824, May 1992. [7] E. Felt, E. Malavasi, E. Charbon, R. Totaro and A. Sangiovanni-Vincentelli, \Performance-Driven Compaction for Analog Integrated Circuits", in Proc. IEEE Custom Integrated Circuits Conference, pp. 1731{1735, May 1993. [8] H. Chang, A. Sangiovanni-Vincentelli, F. Balarin, E. Charbon, U. Choudhury, G. Jusuf, E. Liu, E. Malavasi, R. Ne and P. Gray, \A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits", in Proc. IEEE Custom Integrated Circuits Conference, pp. 841{846, May 1992. [9] S. W. Director and R. A. Rohrer, \The generalized adjoint network and network sensitivities", IEEE Trans. on Circuit Theory, vol. 16, pp. 318{323, Aug 1969. [10] D. A. Hocevar, P. Yang, T. N. Trick and B. D. Epler, \Transient sensitivity computation for MOSFET circuits", IEEE Trans. on CAD, vol. 4, pp. 609{620, Oct 1985. [11] W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli and A. L. Tits, \DELIGHT-SPICE: An OptimizationBased System for the Design of Integrated Circuits", IEEE Trans. on CAD, vol. 7, n. 4, pp. 501{519, April 1988. [12] J.-M. Shyu, \Performance Optimization of Integrated Circuits", Memorandum UCB/ERL M88/74, University of California at Berkeley, Nov 1988. [13] D. J. Allstot and Jr. W. .C. Black, \Technological Considerations for Monolithic MOS SwitchedCapacitor Filtering Systems", in Proc. of the IEEE, pp. 967{986, 1983. [14] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, \Matching Properties of MOS Transistors", IEEE Journal of Solid State Circuits, vol. 24, pp. 1433{1440, Oct 1989. [15] U. Choudhury, \Sensitivity Computation in SPICE3", M.s. thesis, University of California at Berkeley, 1988.