386 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 4, NOVEMBER 1999 Constraint Transformation for IC Physical Design Enrico Malavasi, Member, IEEE, and Edoardo Charbon, Member, IEEE Abstract— In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications. Index Terms— Constraints, nondeterministic transformations, tolerance-aware models, top-down design, sensitivity. I. INTRODUCTION T HE progressive consumerization of the integrated circuit (IC) market leaves less and less time to develop reliable components and systems to implement the growing demand for functionality. To sustain time-to-market pressure, it is necessary to stress design methodology and to facilitate correct-by-construction paradigms. In a top-down design methodology [1], the design flow proceeds through levels of abstraction. At each level, design tasks are divided into independent subtasks for which constraints are generated. If all subtasks are executed correctly and their constraints are met, the original task will also be satisfactorily completed. Given a set of constraints for a design task, optimal generation of constraints for all subtasks is a complex problem, usually referred to as “constraint transformation.” By repeatedly solving task partitioning and constraint transformation at each level of abstraction, the problem of designing a complex circuit is transformed into a set of independent simpler tasks with well defined specifications. Such a constraint-driven design environment is robust, since it allows to identify constraint violations as early as possible in the design process [2], [3]. In the IC fabrication process, all design parameters are subject to deviations from their nominal values. Both absolute values and mismatch of parasitics play a role in the deviation of performance functions from their nominal behavior. The objective of constraint transformation is to generate bounds on the variations of all physical design parameters such that performance degradation is maintained within specifications. Constraint transformation is solved with a two-step procedure. Manuscript received August 31, 1998; revised July 28, 1999. The authors are with Cadence Design Systems, Inc., San Jose, CA 95134 USA. Publisher Item Identifier S 0894-6507(99)09247-7. i) Model generation: a model is created relating performance measures to the design parameters. ii) Constraint generation: actual bounds are generated on all design parameters. As a simple example, consider a delay constraint on a net. During model generation, we model , where and are the lumped resistance and capacitance of the net. During the constraint generation phase, we determine max such that . bounds for and Another example is the use of performance sensitivities, which provide a powerful model generation technique whenever a circuit behavior can be linearized around a nominal point. Constraint generation then can be obtained through the solution of a linear system, usually aimed at some optimization objective [2]. In this paper, we will describe the constraint transformation problem as it has been formulated for the specific case of physical design for IC’s. In this field, research has focused on: 1) linearized models built using sensitivity analysis [4], [5]; 2) optimization techniques for bound generation, based on some model of the “flexibility” [2], [5] of the layout tools, i.e., a measure of how easy it would be for a design tool to enforce a given set of bounds. Then, constraint-driven design tools [2], [3] enforce bounds on low-level design parameters, ignoring the original performance constraints used to generate those bounds [6]. In this formulation, the criticality of parasitics is quantified based on the cumulative effect to performance, and it is used to drastically reduce the number of specifications on each interconnect realization. The deterministic nature of parasitics is postulated in these approaches as a necessary condition to yield meaningful bounds. Nondeterministic effects are due mainly to mask misalignment, technology gradients in the fabrication process, and substrate noise. Both deterministic and stochastic design parameters must be taken into account in this approach. Their models can be constructed in a similar fashion, using appropriate statistical modeling for the nondeterministic parameters. The paper is organized as follows. The constraint-driven physical design paradigm is outlined in Section II. The generalized constraint generation problem is formalized in Sections III and IV for deterministic and nondeterministic design parameters, respectively. Nondeterministic substraterelated effects are covered in Section V, where constraint generation strategies are also provided. The constraint generation engine is described in Section VI. Several examples illustrating the approach are presented in Section VII. 0894–6507/99$10.00  1999 IEEE MALAVASI AND CHARBON: CONSTRAINT TRANSFORMATION FOR IC PHYSICAL DESIGN 387 Fig. 1. Constraint-driven physical design flow. II. THE CONSTRAINT-DRIVEN DESIGN PARADIGM In a general semiautomated constraint-driven physical design flow, three main components can be recognized: a translation engine, a set of constraint-driven physical assembly tools, and an extraction or verification utility. Fig. 1 shows a general constraint-driven physical design flow. The following are the operations needed to support such a flow. 1) Define performance specifications. They can be either determined by the user or propagated from a higher level of hierarchy. 2) Translate specifications onto a set of constraints for physical design. The semantic of these constraints is compatible with and can be successfully implemented by the physical layout tool set. 3) Detect overconstraints. 4) Manually edit constraints, if needed. 5) Enforce constraints in every physical design phase. This step, indicated by the bold arrow in Fig. 1, can be manually bypassed or guided when appropriate. Additional geometric constraints can be programmed to enhance the chances of meeting high-level specifications. 6) Verify original specifications. This step corresponds to the thin arrow in Fig. 1. If constraints are not met, iterate. The constraint translation and enforcement phases may be applied incrementally while the design unfolds or could be obtained from previously designed systems undergoing redesign or technology migration. Editing and local interactive rebudgeting are also allowed. denoted by . All design parameters are subject to variations with respect to their nominal (simulated or expected) values . With no loss of generality, we can assume that all design parameters are normalized, so that their deviations are always . Performance measures are functions of nonnegative: all design parameters where . The constraints on maximum performance degradation can be upper or lower bounds. The following notation will be used: (1) The problem of constraint transformation can be formulated on which as follows. Determine a feasible set of bounds allow all performance constraints (1) to be met. In general, more than one solution exists for this problem. Therefore, constraint transformation is formulated as an optimization of how problem, the objective function being a model costly it would be to meet the given set of bounds minimize: subject to: (2) is denoted as flexibility function [4]. Function Often a linearized model is used to represent the dependency of performance measures on design parameters. This model can be obtained by first order Taylor expansion of (3) III. THE CONSTRAINT GENERATION PROBLEM In a circuit with performance characteristics, let be the vector of the nominal (simulated or expected) values for all performance measures. Because of process variations and parasitics in the actual circuit, the performance measures . The array of all performance deviations will are . Performance measures are be denoted as functions of the design parameters and parasitics, which will be where is the matrix of the performance sensitivities relative to , defined as the following: Each entry in the matrix represents the sensitivity of the th measure of with respect to the th component in . 388 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 4, NOVEMBER 1999 Sensitivities can be computed using standard circuit simulators such as SPICE, using the adjoint technique [7] or perturbation methods [8]. The entries of can be either positive or negative; hence, cancellations may occur within the model. However, since the exact value of the parasitics is not known a priori, the global effect on performance may be underestimated. Deviations of performance measures in the positive and negative directions must be decoupled. By substituting the linearized expression (3) in inequalities (1), the general problem is rewritten as representation. Constraints cannot be defined on these parameters because a nonzero probability exists that they will not be met. Instead, constraints must be set on the moments of a parasitic component rather than on its actual value. Let array of size define a set of known nondeterbe the array of ministic parasitic components, and let . Assume all statistical distributions associated with now that the first moments exist and are bounded for all components of . Moreover, assume that all components of be statistically independent. Then, the first moments of degradation can be computed as (6) (4) denotes the th moment and a matrix whose entries equal the th power of the corresponding entry of . Formulation (2) of the constraint generation problem is used to derive bounds on the first moments of , replacing the constraint formulations with the following constraints: where is the matrix of the worst-case positive sensitivities where is the matrix of the absolute values of the worst-case and negative sensitivities In the remainder of this paper, the “ ” and “ ” signs will be omitted. The linearized model (4) will be expressed as (5) IV. HANDLING NONDETERMINISTIC CONSTRAINTS Let us assume that a joint probability distribution function is known for all nondeterministic parasitics in the circuit; then, a moment-generating function can be derived and a multidimensional tensor can be built for all combinations of th order moments for each pair of parasitics. Generally, designers assume nondeterministic parasitics to be jointly Gaussian and hence uniquely characterized in terms of mean vector and variance-covariance matrix. For every performance measure, a compact stochastic model can be built if such a representation is used. Next, high-level specifications on performance variance can be mapped onto constraints on the maximum degradation allowed on nondeterministic parasitic components. Moreover, given a relationship between parasitic tolerance and layout geometry [9], physical constraints can be generated on the relative distances and orientations of all layout components. The fundamental assumption of this method is that the statistical properties of all parasitics be known a priori and that a bounded cross correlation matrix exist. Sensitivities are used in a constrained optimization loop to obtain constraints on the statistical parameters of parasitics. The optimization objective is a continuous bounded flexibility function, which represents an estimate of how realistic the constraint will be in the actual design. Technology-dependent models of all known parasitic dependencies from physical realization guide the constraintdriven tools to meet all performance specifications. Compact models are available to model interconnect lines and integrated devices with reasonable accuracy over a wide range of operating frequencies. However model parameters are technology dependent and are characterized using a statistical where denotes a constraint on the maximum accept. able value of the th moment of The fact that in most designs the entries of are not statistically independent makes the method inadequate to compute meaningful constraints. To solve this problem, (6) must be modified, while the optimization problem remains fundamenbe the variance-covariance matrix of tally unchanged. Let defined as (7) indicates the expected value. By conwhere operator is a symmetric positive-definite square struction, matrix. Consequently, it can be decomposed as following: (8) nonsingular mapping and a diagonal where is a is positive definite matrix. One can easily show that if mapped onto vector , the new parameters in are is uncorrelated, i.e., the variance-covariance matrix diagonal. The original vector can be obtained as (9) is due to the positive definite and where relation . symmetric characteristics of are jointly Gaussian random variIf the parameters in ables, then the entries of are statistically independent. This technique has been used in the past in analog test generation and yield analysis to efficiently characterize all correlations of Gaussian random parameters. A model based on can then be constructed and used directly in (6) where is substituted . Consequently problem (2) can be solved in terms of with vector , i.e., the bound on the intermediate parameters . Finally, a bound on the moments of can be obtained by MALAVASI AND CHARBON: CONSTRAINT TRANSFORMATION FOR IC PHYSICAL DESIGN 389 where vector is expressed in terms of all sensitivities with respect to the above parameters as Suppose now that the exact waveform felt at is not known, and only an estimate can be derived. Moreover, suppose that a range can be set for (12) Fig. 2. The principle and modeling of local generators. applying the mapping of (9) to the resulting bounds. Consider ; then the transformation translates onto the case (10) V. NONDETERMINISTIC SUBSTRATE CONSTRAINTS Constraint generation requires parasitics to be associated with one or more physical structures in the layout. In the case of switching noise, i.e., noise produced by high-frequency digital circuits, the physical location and transmissions paths through the substrate may not be known before the general floorplan is performed on the chip. For this reason, the constraint generation process cannot take place before layout is generated. To address this issue we introduce the concept of local noise generators. A local noise generator is defined as a voltage or current source producing the equivalent cumulative noise generated by the real noise sources located in the substrate. The generator should simulate as closely as possible the waveform felt at a location , including distortions, attenuations, and group delays which transformed the original noise signal. Call the sensing node (see Fig. 2). such a waveform, where is the time Let us call and is a vector of all the parameters relevant to it. as a local noise generator producing waveLet us define form . Due to the diverse nature of its parameters, can be . split into its basic components represents process-dependent and layout-related parameters, is the temperature and the local substrate potential. One as can also define vector from nominal. the variation of , its degradation from Consider performance measure nominal is given by the product of the th row of the sensitivity with vector matrix (11) and are known vectors. Assuming that where the sensitivity of performance with respect to has been computed, bounds on all parameter variations can be calculated using constrained optimization as shown in Section III. Hence, constraints are generated to bound the amount of noise at the sensing nodes a priori, without a precise knowledge of the structure of the layout being built. During the physical assembly of the circuit, all precomputed constraints will be enforced separately on each component of the layout. Let us now generalize the problem to a large number of sensing nodes. From a theoretical standpoint, at each receptor a different waveform could be felt. However, since the size of the analog section of a mixed-signal circuit is small compared to the distance to the noise sources, we can safely assume that all substrate nodes are reached by an identical waveform at different times. sensing nodes exist, each of them connected to a Suppose , with , where local generator is the propagation delay between nodes. Due to the highly nonlinear dependence of performance on phase, an additive linearization around a nominal value could inaccurately model the parasitic effects of the substrate. The problem can be addressed by deriving a set of worstthe array of case sensitivities as described in [10]. Call all design parameters for which is not strongly nonlinear. , Hence, a conservative estimate of the total variation of is derived as due to node (13) Using the same formalism of (11) and considering all the in the circuit, we can define the following sensing nodes matrices: .. . and .. . Thus, the degradation of performance trace (14) is expressed as (15) Equation (15) models the contributions of all sensing nodes . Bounds on the parameters associated onto performance 390 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 4, NOVEMBER 1999 sensitivity analysis is performed on the circuit by means of standard symbolic, numerical, or mixed techniques [7], [8]. A linearized performance model is built accounting for both deterministic and nondeterministic parasitics (16) Fig. 3. Constraint check. is the mean of . Using the variance-covariance where information associated with all nondeterministic parasitics, is derived by means of singular value decomposition. The new performance model becomes (17) where the new sensitivity matrix is derived as (18) The mean value is computed as follows: (19) and . Without loss of generality, assume that Using a priori estimates of upper-bounds on parasitics , critical parasitics is detected by eliminating the subset of all parasitics for which (20) Fig. 4. The constraint generation flow. can be computed using with each sensing node constrained optimization provided that conservative upper- and are also available for lower-bounds on the realization of each sensing node . The use of worst-case sensitivity matrix has the advantage of reducing the parameter space of . Due to the mechanism of noise modeling obtained using local generators, constraints on noise parameters can be derived independently of a particular IC process. Hence, the constraint generation is required only once for a given circuit. During physical assembly, process-dependent substrate extraction, in combination with estimates of the sources of switching noise, are used to enforce the bounds. Once the substrate has been extracted, a transfer function can be computed relating each noise source to receptor . Assuming that approximations or exact waveforms are known for each noise source, waveform and the can be easily evaluated for each corresponding parameter node . Thus, a simple check can be performed to verify that , and hence the original specifications constraints have been met (see Fig. 3). VI. CONSTRAINT GENERATION ENGINE Fig. 4 shows the constraint generation process in detail. From hardware description and performance specifications, is chosen so as to not excessively is satisfied. The term reduce the range in which the critical parasitics will be . The allowed to vary, while at the same time maximizing value of does not seem to critically affect the constraint generation process. In our experiments, we have observed that an acceptable number of critical parasitics can be obtained if . For deterministic parasitics, the condition for finding critical parasitics is the following: (21) The final bounds on critical parasitics and on the first moments of the intermediate parameters are computed using a standard quadratic programming approach. All intermediate parameter bounds are then reconverted into bounds on the original parameters using (9). The generalized constraint generation process is the core of Cadence’s new constraint-driven physical design environment, presently under development. The translation from high-level specifications onto parasitic constraints can be completely automated or driven by human interactions. The extent of the user’s control in the constraint computation process is not limited by any of the physical assembly tools. All the constraint generation phases are fired by a constraint manager, which is intended to serve all the existing and future physical assembly tools within our constraint-driven design environment. The constraint manager will also supervise the translation of constraints at higher level, namely the budgeting process used to MALAVASI AND CHARBON: CONSTRAINT TRANSFORMATION FOR IC PHYSICAL DESIGN 391 A. Clocked Comparator Consider the clocked comparator COMPL, depicted in Fig. 6. This comparator has been used as a benchmark in several works on analog CAD [3], [11], [12], due to its high performance sensitivity to layout details. Assume a specification of 7 ns is imposed to switching delay and of 1 mV to systematic offset . Then, vectors , , are defined as and ns ns mV mV Let us consider the interconnect capacitances and stray resistances at all the nodes represented in the schematic of Fig. 6. The initial number of parasitics is 19 for capacitances, (19 18/2) for capacitive cross-coupling, 28 for stray resistances, 27/2) for resistive coupling. Using conservative and (28 values for the minimum and maximum parasitic estimates, as Fig. 5. Constraint-driven physical layout design flow. fF propagate global specifications through the hierarchical levels of complex mixed-signal designs as outlined in [1]. The constraint manager and its interactions with physical assembly tools in the constraint-driven design environment is shown in Fig. 5. Constraints are generated on demand in every phase of the layout design. The set of all constraints is partitioned into subsets with all the constraints needed by a particular layout phase. The constraint generator operates on the subsets incrementally, i.e., calculating all subset constraints while using extracted values for parasitics of previous phases and estimates for parasitics of future phases. This is equivalent to modifying problem (2) as (22) maximize: fF and the specifications on performance and the sensitivity matrix obtained from SPICE, the number of parasitics for which we need to compute a bound is reduced from to , namely fF fF fF fF subject to: (23) (24) (25) represent extracted parwhere the terms asitics associated with layout structures which have already relates to been generated. On the contrary, term the budgeted performance degradation due to layout structures which still need be generated. This flow accommodates both comprehensive and partial constraint enforcement, where the reproducibility of a design is ensured by a constraint status trace. VII. RESULTS The constraint generation techniques outlined in this paper have been tested on a wide range of fully analog and switched circuits, selected from a set of commonly used industrial applications. We will discuss here a few circuits to highlight the proposed features. For the computation of all sensitivities, standard analysis options available in SPICE or perturbation based methods have been used in dc, ac, and transient domains. where symbols , denote capacitive cross couplings and stray resistance mismatches, respectively. Here the relation between sensitivity and tightness of bounds is evident. Only a few parameters critically affect the performance of this circuit and therefore need be bounded tightly. In practice, only the mismatch between the source resistances in the differen) tial pair and between the two current mirrors ( ) are responsible for the offset. The entire and ( constraint generation procedure was performed in less than 1 s, while the sensitivity analysis required 9 s on a DEC AlphaServer 2100 5/250 . The nondeterministic constraint analysis, omitted here, was performed in 5 s on a DEC 45 varianceAlphaServer 2100 5/250 resulting in a 45 covariance matrix. B. Low Power Amplifier Consider the low power amplifier MPH, depicted in Fig. 7. This circuit is of interest because of the presence of several feedback and forward paths, provided to ensure stability. The feedback paths may cause an increased susceptibility to cross coupling parasitics, which mimic the intended stabilizing 392 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 4, NOVEMBER 1999 Fig. 6. Clocked comparator COMPL. Fig. 7. Low power amplifier MPH. (Courtesy of R. G. H. Eschauzier and J. H. Huijsing, TU Delft, The Netherlands.) TABLE I MPH: NOMINAL PERFORMANCE AND SPECIFICATIONS TABLE II MPH: CONSTRAINTS ON CRITICAL DETERMINISTIC PARASITICS behavior of shunt capacitances. Another point of interest is the low supply required by the circuit, making it particularly sensitive to all device threshold voltages. Table I lists all the performance specifications for this circuit. A summary of all calculated constraints on deterministic parasitics is shown in Table II. 153 constraint Table III shows a section of the 153 variance-covariance matrix. MALAVASI AND CHARBON: CONSTRAINT TRANSFORMATION FOR IC PHYSICAL DESIGN MPH: BOUNDS ( 1006 ) 2 ON THE 393 TABLE III ACCEPTABLE VARIANCE–COVARIANCE MATRIX TABLE IV MPH: CPU TIMES FOR THE COMPUTATION OF ALL CONSTRAINTS (a) Fig. 8. PLL schematic. TABLE V PLL SPECIFICATIONS (b) The CPU times required for all constraint derivations is reported in Table IV for a DEC AlphaServer 2100 5/250. C. Phase Locked Loop The architecture of the phase locked loop (PLL), similar to the one proposed in [13], is shown in Fig. 8. Schematic design and sizing were performed using topdown, constraint-driven design [14]. The specifications for the PLL are summarized in Table V. The jitter is defined as the ratio between the variation of an oscillation period and the period. Due to its time variance, it is measured in terms of peak-to-peak or RMS value. The PLL is composed of a digital section, i.e., three divideby- modules and a phase-frequency detector (PFD), and several purely analog circuits, namely a low-pass filter (LPF) and a charge pump (CP). The voltage-controlled oscillator (VCO) serves as the interface between analog and digital sections. The VCO consists of a ring of eight basic delay cells and two replica bias blocks, depicted in Fig. 9(a)–(c), respectively. The dependency of the PLL’s frequency-to-voltage signal path from process, temperature variations, and layout parasitics was contained by careful sizing, optimized to keep the sensitivity (c) Fig. 9. (a) VCO block diagram. (b) Bias. (c) Delay cell. of the design with respect to these nonidealities within userdefined constraints [14]. The VCO, on the contrary, is sensitive to both interconnect parasitics and substrate noise. To account for these effects, we proceeded as follows. First, a worst-case sensitivity analysis was performed on the delay element of Fig. 9 and the entire ring oscillator, modified to account for resistive/capacitive parasitics as shown in Fig. 10. A sensitivity-based model of the VCO was constructed, relating the jitter performance to all the known deterministic interconnect-induced parasitics. Then, using the techniques outlined in Section III, a set of constraints on critical interconnect lines was derived. The results are listed in Table VI, along with the values extracted at the completion of the physical assembly phase. Second, using the concept of local noise oscillators, constraints on the noise amplitude sensed at each critical node in the circuit were derived in such a way that the jitter be within specifications. The results are presented in Table VI. The nondeterministic parasitic effects are represented, in this case, by the noise currents injected through the substrate into 394 Fig. 10. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 4, NOVEMBER 1999 VCO architecture with interconnect models. TABLE VI CONSTRAINTS OBTAINED BY THE SENSITIVITY ANALYSIS NOISE INJECTOR AND TABLE VII RECEPTOR STATISTICS IN THE COMPONENTS OF THE PLL the VCO. Using (6), a relatively accurate model of the jitter degradation from nominal could be built as a function of the substrate injection currents at the sources. All the potential sources of switching noise are localized in the dividers. Injection occurs by impact ionization through the active areas of NMOS devices (in a N-well process) and by capacitive coupling through junctions and interconnect. Substrate noise is received in all the active areas of both doping types. Table VII lists the sources and the receivers of substrate noise in the various components of the design. These constraints were enforced directly by module generator VCOGEN [14] and by Simulated Annealing based placer PUPPY-A [15], via an internal cost function. The entire circuit was subsequently verified using the substrate extraction package SUBRES [16] and the digital noise injection analyzer SUBWAVE [17]. The CPU times for sensitivity calculation, constraint generation, and VCO layout synthesis are listed in Table VIII. Table IX shows the estimated jitter levels for the PLL after completion of the physical assembly. VIII. CONCLUSIONS A comprehensive methodology has been presented for the generation of constraints in physical design flows. The central TABLE VIII CPU TIMES ON A DEC ALPHASERVER 2100 5/250 TABLE IX PLACEMENT STATISTICS OBTAINED ON A DEC ALPHASERVER 2100 5/250 idea of the methodology consists in translating a set of specifications on high-level performance onto a set of constraints which can be handled by a constraint-driven physical assembly environment. The translation techniques, applied to a wide range of design parameters, are based on constrained optimization and parasitic modeling. The method requires a reasonable degree of circuit linearity, a well-defined set of parasitic components, and known statistical properties for all nondeterministic parasitics. REFERENCES [1] H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits. Boston, MA: Kluwer, 1996. [2] U. Choudhury and A. Sangiovanni-Vincentelli, “Constraint generation for routing analog circuits,” in Proc. IEEE/ACM DAC, June 1990, pp. 561–566. [3] E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli, “Automation of IC layout with analog constraints,” IEEE Trans. ComputerAided Design, vol. 15, pp. 923–942, Aug. 1996. [4] U. Choudhury and A. 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Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440, Oct. 1989. [10] E. Charbon, E. Malavasi, P. Miliozzi, and A. Sangiovanni-Vincentelli, “Nondeterministic constraint generation for analog and mixed-signal layout,” IEICE Trans. Inform. Systems, vol. E80-D, Oct. 1997. [11] E. Felt, E. Malavasi, E. Charbon, R. Totaro, and A. SangiovanniVincentelli, “Performance-driven compaction for analog integrated circuits,” in Proc. IEEE CICC, May 1993, pp. 1731–1735. [12] B. Basaran, R. A. Rutenbar, and L. R. Carley, “Latchup-aware placement and parasitic-bounded routing of custom analog cells,” in Proc. IEEE ICCAD, Nov. 1993, pp. 415–421. [13] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5–110 MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, pp. 1599–1607, Nov. 1992. [14] I. Vassiliou, H. Chang, A. Demir, E. Charbon, P. Miliozzi, and A. L. Sangiovanni-Vincentelli, “A video driver system designed using a top-down, constraint-driven methodology,” in Proc. IEEE ICCAD, Nov. 1996, pp. 463–468. [15] E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, and A. Sangiovanni-Vincentelli, “A constraint-driven placement methodology for analog integrated circuits,” in Proc. IEEE CICC, May 1992, pp. 2821–2824. [16] R. Gharpurey and R. G. Meyer, “Analysis and simulation of substrate coupling in integrated circuits,” Int. J. Circuit Theory Applicat., vol. 23, pp. 381–394, July–Aug. 1995. [17] E. Charbon, P. Miliozzi, L. P. Carloni, A. Ferrari, and A. L. Sangiovanni-Vincentelli, “Modeling digital substrate noise injection in mixed-signal IC’s,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 301–310, Mar. 1999. Enrico Malavasi (M’97) received the B.S. degree from the University of Bologna, Bologna, Italy, in 1984 and the M.S. degree from the University of California, Berkeley, in 1993, both in electrical engineering. Between 1986 and 1989, he was with the Department of Electrical Engineering and Computer Science (DEIS), University of Bologna, on research topics related to CAD for analog circuits. In 1989, he joined the Dipartimento di Elettronica ed Informatica at the University of Padova, Italy, as Assistant Professor. Between 1990 and 1995, he collaborated with the CAD group of the Department of Electrical Engineering and Computer Science at the University of California, Berkeley, where he has carried out research on performance-driven CAD methodologies for analog design. In July 1995, he joined Cadence Design Systems, San Jose, CA, as an Architect for physical design, and he is currently responsible for the development of advanced tools for the automation and acceleration of constraint-driven mixed-signal IC layout design. He has authored or coauthored more than 40 articles for international journals, conferences, and books, and he holds one U.S. patent. His research interests include several areas of design automation: layout, design methodologies, optimization, extraction, and circuit analysis. 395 Edoardo Charbon (S’90–M’92) received the Diploma in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, in 1988, the M.S. degree in electrical and computer engineering from the University of California, San Diego, in 1991, and the Ph.D. degree in electrical engineering and computer sciences at the University of California, Berkeley, in 1995. Between 1988 and 1989, he worked at the Department of Electrical Engineering, ETH, where he designed CMOS A/D converters for integrated sensor applications. In 1989, he visited the Department of Electrical Engineering of the University of Waterloo, Canada where he was involved in the design and fabrication of ultra low-noise nano-Tesla magnetic sensors. At the University of California, Berkeley, he worked on performance-directed constraint-based analog and mixed-signal physical design automation and accelerated substrate extraction techniques. Since 1995, he has been with Cadence Design Systems, San Jose, CA, where he is leading the development effort on constraint management in the physical design group. He is also the Project Leader of Cadence’s first methodology for intellectual property protection. He has published over 40 articles in technical journals and conference proceedings, a book, and he has been consulting with Texas Instruments and Hewlett-Packard. His research interests include CAD for radio-frequency IC’s, methodologies for intellectual property protection, substrate modeling and characterization, superconducting parasitic analysis, and micromachined sensor design. Dr. Charbon is a Guest Editor of the IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.