Abstract A tool named SPARCS-A for compaction of integrated circuits with analogue constraints is presented. the approach is structured in two steps. First a robust and efficient constraint graph compaction algorithm produces a compacted layout quickly, where parasitics are controlled so as to guarantee that the performance constraints are met. Next the layout produced by the first step is fed into a linear programming (LP) solver which enforces symmetries and performs global interconnect length minimization. the ...
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