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Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011
Abstract
Fine-grained control through the use of a wide control word can lead to high instruction-level parallelism, but unless compressed the words require a large memory footprint. A reconfigurable fixed-length decoding scheme can be created by taking advantage of the fact that an application only uses a subset of the datapath for its execution. We present the first complete implementation of
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