digital logic design

1 `COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University Chapter 5: Synchronous Sequential Logic NOTE: For more examples and detailed description of the material in the lecture notes, please refer to the main textbook: Digital Design 3rd Edition, By Morris Mano, Publisher Prentice Hall, 4th Edition All examples used in the lecture notes are from the above reference. Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in the circuit. Inputs Combinational Circuit Outputs Memory Element - Sequential circuits can be categorized as being synchronous or asynchronous. - A synchronous sequential circuit usually has a clock pulse (clocked sequential circuits). - Flip-flops are storage elements which are used in clocked sequential circuits. - Each flip-flop can store one bit. - A synchronous clocked sequential circuit is shown below: Inputs Combinational Circuit Clock Pulse Outputs Memory Element Clock Pulse Latches - Latches are the basic types of flip-flops. - The SR latch is a latch with two inputs S (set) and R (reset), and an output Q. - Q = 1 (Q’ = 0) represents the set state and Q = 0 (Q’ = 1) represents the reset state. Lecture Notes Prepared by Amir G. Aghdam 2 - The SR latch can be implemented by NOR gates or NAND gates. 1 0 R Q 1 0 - S Q’ S R Q Q’ 1 0 1 0 (Set state) 0 0 1 0 (After S=1, R=0) 0 1 0 1 (Reset state) 0 0 0 1 (After S=0, R=1) 1 1 0 0 (Undefined) Assume S=1 and R=0 in the above circuit. Then the output of the bottom gate (Q’) is definitely 0 (note that the output of a NOR gate is zero if at least one of its inputs is 1). This means that the output of the top gate (Q) is 1, as both of its inputs are 0. This is called the set state. - Assume now that right after the above state, S becomes 0. Since from the previous state we have Q=1, hence the output of the bottom gate stays at 0 and consequently the output of the top gate also stays at 1, as both of its inputs are equal to 0. - Similarly, if S=0 and R=1, then we will have Q=0 and Q’=1, which is the reset state (this can be concluded from the symmetrical configuration of the circuit as well). Again, if R becomes 0 right after the reset state, the outputs will remain unchanged (Q=0 and Q’=1). - After any change in the input, it has to go to zero so that the circuit becomes ready for the next state. - In undefined state the next output is not predictable when both inputs go back to zero (it depends whether the S or R input goes to zero first). - NAND gate implementation: Lecture Notes Prepared by Amir G. Aghdam 3 S R - Q Q’ S R Q Q’ 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 (After S=0, R=1) 0 0 1 1 (Undefined) (After S=1, R=0) Assume S=0 and R=1 in the above circuit. Then the output of the top gate (Q) is definitely 1 (note that the output of a NAND gate is 1 if at least one of its inputs is 0). This means that the output of the bottom gate (Q’) is 0, as both of its inputs are 1. - Assume now that right after the above state, S becomes 1. Since from the previous state we have Q=1, hence the output of the bottom gate stays at 0 and consequently the output of the top gate also stays at 1, as one of its inputs is equal to 0. - One should make sure that both inputs are not connected to zero simultaneously. - SR latch with control input is shown below: S Q C (Control input) Q’ R - C S R Next state of Q 0 x x No change 1 0 0 No change 1 0 1 Q=0 (Reset state) 1 1 0 Q=1 (Set state) 1 1 1 Undefined D latch (data latch) is an element which holds data in its internal storage and the output becomes equal to D each time C enables the circuit (by changing to 1). Lecture Notes Prepared by Amir G. Aghdam 4 D C D Next State of Q 0 x No change 1 0 Q=0 (Reset state) Q’ 1 1 Q=1 (Set state) Q C - D latch is also called a transparent latch. - Block diagram of latches are shown below. S S D R R C SR latch (NOR gate implementation) SR latch (NAND gate implementation) D latch Flip-Flops - The problem with the latch is that it responds to a change during a positive level (or a negative level) of a clock pulse but in a sequential circuit we need to trigger the element only at a signal transition instant. Positive-edge response - Negative-edge response Two different ways to construct a D flip-flop from latches are shown below. Lecture Notes Prepared by Amir G. Aghdam 5 1. X Y D C D latch (master) Q D C D latch (slave) CLK - The value of D is being transferred to Y during CLK = 1 but it is being transferred to Q only when CLK changes from 1 to 0. - One can change the position of the inverter to make the circuit a positive-edge triggered D flip-flop. CLK X Y Q 2. More efficient construction (using three SR latches) Y S Q CLK Q’ R D Z Lecture Notes Prepared by Amir G. Aghdam 6 - S and R are equal to 1 while CLK = 0 (which causes no change in the output). - If D = 0 when CLK becomes 1, R changes to 0 (Since S = 1, Z = 1, CLK = 1) and this resets the flip-flop, making Q = 0. - Now if D changes its value (while CLK = 1), since R = 0, we will still have Z = 1 and it will not change the value of R. - When clock goes to 0, R goes to 1 which is a normal condition (as S is still 1), causing no change in the output. - Now if D = 1 when CLK goes to 1, it makes Z = 0 (D = 1, R = 1) and it causes Y = 1 and since CLK = 1, Y = 1, so S becomes 0, and this sets the output (S = 0, R = 1) - Any change in D while CLK = 1 does not affect the output. - Setup time is the minimum time the D input is required to stay at a constant value prior to the next clock change. - Hold time is the minimum time the D input is required to stay unchanged after the clock change. - Propagation delay is the interval between the trigger edge and the stabilization of the output to a new state. - The symbols for D flip-flop are shown in the following figures. D C Positive-edge triggered D flip-flop - D C Negative-edge triggered D flip-flop There are three operations that can be performed with a flip-flop: set, reset, or complement the output. JK Flip-Flop: - The JK flip-flop can be derived from the D flip-flop using the Boolean function D = J .Q ′ + K ′.Q as follows: Lecture Notes Prepared by Amir G. Aghdam 7 J D K - Q C CLK Q’ The symbol for JK flip flop is shown in the following figure. J C K - All three operations set, reset, and complement can be performed by a JK flip-flop. - When J=0 and K=0, then D=Q, which implies that the output remains unchanged (after the next clock edge). - When J=0 and K=1, then D=0, which implies that the output is reset (after the next clock edge). - When J=1 and K=0, then D=1, which implies that the output is set (after the next clock edge). - When J=1 and K=1, then D=Q’, which implies that the output is complemented (after the next clock edge). - The characteristic table and the characteristic equation describe the operation of a flip-flop through a table and an algebraic equation, respectively. - The characteristic table of the D flip-flop and the JK flip-flop are as follows: Next state (one clock later) D Q(t+1) J K Q(t+1) 0 0 0 0 Q(t) 1 1 0 1 0 Reset 1 0 1 Set 1 1 Q’(t) Lecture Notes Prepared by Amir G. Aghdam No change Compliment 8 - The characteristic equation of the D flip-flop and the JK flip-flop are as follows: Q(t+1)=D , Q(t+1)=J.Q’(t)+K’.Q(t) T Flip-Flop - The T (toggle) flip-flop can be derived from the D flip-flop using the Boolean function D = T ⊕ Q = T .Q ′ + T ′.Q as follows. D T Q C - It can also be derived from a JK flip-flop as follows. T - Q’ J Q C K Q’ When T=0, then D is equal to Q, which means that the output remains unchanged after the next clock edge. - When T=1, then D becomes equal to Q’, which implies that the output is complemented after the next clock edge. - The characteristic equation of the T flip-flop can be obtained as follows. - The characteristic table of the T flip-flop is given below. - D = T ⊕ Q = T .Q'+T '.Q ⇒ Q(t + 1) = T .Q'+T '.Q T Q(t+1) 0 Q(t) No change 1 Q’(t) Compliment The graphic symbol of the T flip-flop is as follows. T C Lecture Notes Prepared by Amir G. Aghdam 9 - Direct inputs: Sometimes asynchronous inputs are used to change the state of a flipflop to a preset (direct set) or clear (direct reset) state at any desired time (regardless of clock pulses). Preset y S Q CLK R D Q’ x Clear - Start with S = R = 1 (normal condition). Assume that Clear = 0. Then Q’ = 1, and since S = 1 and Preset = 1, it resets the flip-flop (Q = 0). - Start again with S = R = 1 (normal condition). Assume now that Preset = 0. Then Q will be equal to 1, and since R = 1 and Clear = 1, thus Q’ goes to zero, which sets the flip-flop (Q = 1). - Thus, if Clear is zero, the flip-flop will be cleared to zero, i.e. Q = 0, and if Preset is equal to 0, it forces the flip-flop into Q = 1. - In general case, we will have the following representation of the D flip-flop with direct reset (↑ represents the positive edge of the CLK). Data CLK Reset Q D C R Q’ Reset C D Q Q’ 0 X X 0 1 1 ↑ 0 0 1 1 ↑ 1 1 0 Lecture Notes Prepared by Amir G. Aghdam 10 Analysis of Clocked Sequential Circuits - A clocked sequential circuit can be analyzed by using: (i) The state equation obtained by replacing flip-flop input equations in its characteristic equation, or (ii) a state table. - Analysis with D flip-flops: Write the Boolean expression for each flip-flop input, which is, in fact, the flip-flop output right after the next active clock edge. - Example: x D A C A’ B D CLK B’ C y - State equation can be written as: - or simply: - The output is given by: - or simply: - State table or transition table lists all possible binary combinations of present state A(t + 1) = A(t ).x(t ) + B(t ).x(t ) B (t + 1) = A′(t ).x(t ) A(t + 1) = A.x + B.x B (t + 1) = A′.x y (t ) = [ A(t ) + B(t )].x ′(t ) y = [ A + B].x ′ and inputs. Lecture Notes Prepared by Amir G. Aghdam 11 m flip-flops n inputs Present state Input 2 m+ n rows - A.x+B.x A’.x A.x’+B.x’ Next state Output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 For some applications (like state reduction) we may use the following form of the state table: Next state Present state - Output x=0 x=1 x=0 x=1 A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 State diagram: Present state Next state AB AB Input/output - The state diagram follows directly from the state table. - For the previous example: Lecture Notes Prepared by Amir G. Aghdam 12 0/0 1/0 0/1 00 1/0 0/1 01 10 0/1 1/0 11 1/0 Fig. 5.1 - Flip-flop input equations or excitation equations (for a circuit with D flip-flops, it is the same as the state equation): - D A = A.x + B.x DB = A′.x Each interconnection with the corresponding initial and final states can be built by using a combinational circuit. - Example (analysis with D flip-flop): In the circuit below, we have D A = A ⊕ x ⊕ y x D y A C CLK inputs Present state Next state A x y A 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Lecture Notes Prepared by Amir G. Aghdam 13 - When the output is not specified, we assume that the output is the output of the flipflop. 01,10 00,11 0 1 00,11 01,10 - Analysis with JK flip-flops: It is desired to find the state table (or transition table), from which one can easily obtain the state diagram. To this end, one can find the flipflop input equations (from the combination circuit which generates the input signals) and replace them in the characteristic equation to find state equation (or transition equation). Then, next state and also output(s) can be obtained for different values of the input. Alternatively, one can add some additional columns to the transition table (one for each flip-flop input) and find the elements of these added columns for different values of the input (and present state). The values of the next state can then be obtained directly from the flip-flop inputs. - Example: J x A C K B J C K CLK JA = B J B = x′ K A = B.x ′ K B = A ⊕ x = A′.x + A.x ′ Lecture Notes Prepared by Amir G. Aghdam (5.1) 14 Present state Input Next State Flip-Flop inputs A B x A B JA KA JB KB 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 These are obtained from the boolean expressions (just like ordinary truth table) based on the present states. Note that this is not part of the table. - One can also find the next state from the state equations by substituting the input equations into the flip-flop characteristic equations, as pointed out earlier. - Characteristic equation for the JK flip-flop is: - Substituting the flip-flop input equations given in (5.1) into the above equations: - Next states in the table can now be obtained directly (no need for the flip-flop inputs). ⎧⎪ A(t + 1) = J A . A′ + K A' . A ⎨ ⎪⎩ B(t + 1) = J B .B ′ + K B' .B ⎧ A(t + 1) = B. A′ + ( B.x ′)′. A = A′.B + A.B ′ + A.x ⇒ state equations : ⎨ ⎩ B (t + 1) = x ′.B ′ + ( A ⊕ x)′.B = B ′.x ′ + A.B.x + A′.B.x ′ 1 00 1 0 0 01 11 0 1 10 1 Fig. 5.2 Lecture Notes Prepared by Amir G. Aghdam 15 - Analysis with T flip-flops: Similar to the analysis with JK flip-flops, the state table can be obtained by using state equation, or by adding flip-flop input columns to the table. - Example: A x T C R T C T A = B.x y 0 B R CLK reset TB = x y = A.B - Characteristic equations: A(t + 1) = T A ⊕ A B (t + 1) = TB ⊕ B - Substituting the input equations into the characteristic equations: A(t + 1) = ( B.x)′. A + ( B.x). A′ = A.B ′ + A.x ′ + A′.B.x B (t + 1) = x ⊕ B Present state Input Next State Output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 Lecture Notes Prepared by Amir G. Aghdam 16 - The state diagram will be: 0 0 1 00/0 1 01/0 1 11/1 1 0 10/0 0 Fig. 5.3 - The output is only a function of current state, not the input, and that is why the output is written inside state circles. - Mealy model: A Mealy model is the one that the output is a function of both input x and current states. For example Figure 5.1. - Moore model: A Moore model is the one that the output is a function of the present state only, For example, Figures 5.2 and 5.3. - If the output(s) are not shown in the circuits, the flip-flop states are the outputs. - Note that since in a Moore model the outputs are functions of only flip-flop states, the outputs are synchronized with the clock. - However, in a Mealy model, the outputs may change asynchronously. This can occur when the inputs change during the constant value of the clock cycle. - In a Mealy model momentary false values may occur in the output as a result of the flip-flop delays. State Reduction and Assignment - The number of states reduces by reducing the number of flip-flops. - Example: Lecture Notes Prepared by Amir G. Aghdam 17 0/0 a 1/0 0/0 0/0 b c 0/0 1/0 g 0/0 1/0 d 1/1 0/0 1/1 e 1/1 0/0 f 1/1 - In Particular, for the input sequence 01010110100 and assuming that the initial state is a, we will have: - State a a b c d e f f g f g Input 0 1 0 1 0 1 1 0 1 0 0 Output 0 0 0 0 0 1 1 0 1 0 0 State reduction means to reduce the number of states in a sequential circuit with an identical input-output relationship. - a The easiest way of state reduction is through state table as follows: Lecture Notes Prepared by Amir G. Aghdam 18 Present - Next state Output state x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 Two states are equivalent if for identical inputs they give exactly the same output and result in a transition to the same state (or an equivalent state). - If two states are equivalent, one of them can be removed without changing the inputoutput operation of the circuit. - We have to find a pair of equivalent states and delete one. - States g and e are equivalent and we can delete g and replace it with e. Present Next state Output state x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 - Now we can see that d and f also have similar rows associated with them. - Reduced table: Lecture Notes Prepared by Amir G. Aghdam 19 Next state Present Output state x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 0/0 a 0/0 1/0 e 0/0 b 1/0 c 0/0 1/0 1/0 0/0 d 1/1 - Reducing the number of states does not necessarily mean a circuit with fewer gates and/or flip-flops. - For the above reduced diagram and the input sequence that was given before, we will have: - a a b c d e d d e d e 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 a Note that state reduction in general may lead to a circuit with more gates than the original system (for the combinational circuit which provides inputs to the flip-flops). Lecture Notes Prepared by Amir G. Aghdam 20 - State assignment using coded binary values is required for designing a sequential circuit. - The number of bits (n) in the code must be such that 2 n ≥ m , where m is the number of states. Assignement 1 Assignement 2 Assignement 3 Binary Gray code One-hot state - a 0 0 0 0 0 0 0 0 0 0 1 b 0 0 1 0 0 1 0 0 0 1 0 c 0 1 0 0 1 1 0 0 1 0 0 d 0 1 1 0 1 0 0 1 0 0 0 e 1 0 0 1 1 0 1 0 0 0 0 Using binary assignment 1, the previous simplified state table will be: Next state Present state x=0 Output x=1 x=0 x=1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 1 Design Procedure 1. Translating the design specifications to the state diagram 2. State reduction 3. Assigning binary values to the states 4. Obtaining binary coded state table 5. Choosing the type of flip-flop 6. Deriving the simplified flip-flop input equations and output equations 7. Drawing the logic diagram Lecture Notes Prepared by Amir G. Aghdam 21 - Example: Design a circuit that detects three or more consecutive 1’s in a string of bits coming through an input line. 0 0 S0/0 S1/0 1 0 0 S3/1 1 S2/0 1 1 - Note that this is a Moore model as the output only depends on the states. Synthesis using D Flip-Flops - We have to find the state table first. Present state - Input Next State Output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 A(t + 1) = D A ( A, B, x) = ∑ (3,5,7) Find the flip-flop input equations: B (t + 1) = DB ( A, B, x) = ∑ (1,5,7) y ( A, B, x) = ∑ (6,7) Lecture Notes Prepared by Amir G. Aghdam 22 - Simplify using K-map: B B’ Bx A 00 01 11 10 A’ 0 0 0 1 0 A 1 0 1 1 0 x x’ x’ D A = A.x + B.x B B’ Bx A 00 01 11 10 A’ 0 0 1 0 0 A 1 0 1 1 0 x’ x D B = A.x + B ′.x Lecture Notes Prepared by Amir G. Aghdam x’ 23 B B’ A Bx 00 01 11 10 A’ 0 0 0 0 0 A 1 0 0 1 1 x’ y = A.B x x’ D A C x B D CLK B’ C y - Design with other types of flip-flops is not straightforward as the next state cannot directly be related to the input equations. - In such cases we should use excitation tables, which list the required input for a given change of state. Lecture Notes Prepared by Amir G. Aghdam 24 Q(t) Q(t+1) J K Q(t) Q(t+1) T 0 0 0 x 0 0 0 0 1 1 x 0 1 1 1 0 x 1 1 0 1 1 1 x 0 1 1 0 Excitation table of a Excitation table of a JK flip-flop T flip-flop Synthesis using JK Flip-Flops - Example: Consider the sequential circuit given by the following table: Present state Input Next State A B x A B 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 - Assume that it is desired to design this sequential circuit using JK flip-flops. - Using the excitation table of JK flip-flops, we will have: Lecture Notes Prepared by Amir G. Aghdam 25 Input Present state Bx Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 0 x 0 x 0 0 1 0 1 0 x 1 x 0 1 0 1 0 1 x x 1 0 1 1 0 1 0 x x 0 1 0 0 1 0 x 0 0 x 1 0 1 1 1 x 0 1 x 1 1 0 1 1 x 0 x 0 1 1 1 0 0 x 1 x 1 B’ A Next State J A = B.x ′ B K A = B.x B’ 00 01 11 10 Bx A B 00 01 11 10 A’ 0 0 0 0 1 A’ 0 x x x x A 1 x x x x A 1 0 0 1 0 x x’ x’ B B’ Bx A x x’ x’ B B’ 00 01 11 10 Bx A 00 01 11 10 A’ 0 0 1 x x A’ 0 x x 0 1 A 1 0 1 x x A 1 x x 1 0 K B = ( A ⊕ x)′ x’ x’ x JB = x x’ x’ Lecture Notes Prepared by Amir G. Aghdam x 26 - The logic diagram can be obtained from the input equations given above: x J A C K A’ J B C K B’ CLK Synthesis using T Flip-Flops: - Example: Consider a 3-bit binary counter shown in the following diagram: 000 001 111 010 110 011 101 100 - In fact the only input to the circuit is the clock and the output is the present state of the flip-flops. - The state table for this example is as follows: Lecture Notes Prepared by Amir G. Aghdam 27 From Excitation table Present State Next State Flip-Flop Inputs - A2 A1 A0 A2 A1 A0 T A2 TA1 TA0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 The most efficient way to construct a binary counter is by using T flip-flops, because of their complement property. A1’ A2 A1A0 00 A1 01 11 10 A2’ 0 0 0 1 0 A2 1 0 0 1 0 A0’ A0 A0’ T A2 = A1 . A0 Lecture Notes Prepared by Amir G. Aghdam 28 A1’ A2 A1A0 00 A1 01 11 10 A2’ 0 0 1 1 0 A2 1 0 1 1 0 A0’ A0’ A0 T A1 = A0 A1’ A2 A1A0 00 01 11 10 A2’ 0 1 1 1 1 A2 1 1 1 1 1 A0’ - A1 T A0 = 1 A0’ A0 Logic diagram of the counter: A1 A2 C T C T A0 C T CLK 1 Lecture Notes Prepared by Amir G. Aghdam 29 Reference: [1] Digital Design 3rd Edition, By Morris Mano, Publisher Prentice Hall, 4th Edition. Lecture Notes Prepared by Amir G. Aghdam 

Combinational Logic Circuits Overview
Boolean Algebra





Boolean Function and Representations Truth Table Canonical and Standard Forms





Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems
Minterms and Maxterms Canonical Sum-Of-Products and Product-Of-Sums forms Standard Sum-Of-Products and Product-Of-Sums forms Conversions Combinational Logic Circuits




Digital Systems are made out of digital circuits. Digital circuits are hardware components that manipulate binary information. Certain well defined basic (small) digital circuits are called Logic Gates. Gates have inputs and outputs and perform specific mathematical logic operations. Outputs of gates are connected to inputs of other gates to form a digital combinational logic circuit. Boolean Algebra





In order to analyze and design digital combinational logic circuits we need a mathematical system. Binary logic system called Boolean Algebra is used. George Boole (1815-1864): “An investigation of the laws of thought” – a book published in 1854 introducing the mathematical theory of logic. Boolean Algebra deals with binary variables that take 2 discrete values (0 and 1), and with logic operations. Binary/logic variables are typically represented as letters: A,B,C,…,X,Y,Z or a,b,c,…,x,y,z. Three basic logic operations:
AND, OR, NOT (complementation). Basic Logic Operations
AND operation is represented by operators “•” of an operator.



OR operation is represented by operators “+” or .



Z = X•Y , or Z = XY is read “Z is equal to X AND Y” meaning that: Z = 1 if and only if X = 1 and Y = 1; otherwise Z = 0. AND resembles binary multiplication: 0 • 0 = 0, 0 • 1 = 0, 1 • 0 = 0, 1•1 =1 Z = X+Y is read “Z is equal to X OR Y” meaning that: Z = 1 if X = 1 or Y = 1, or if both X = 1 and Y = 1. Z = 0 if and only if X = 0 and Y = 0. OR resembles binary addition, except in one case: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 1 (≠ 102) NOT operation is represented by operator “ ’ ” or by a bar over a variable.


Z = X’ or Z = X is read “Z is equal to NOT X” meaning that: Z = 1 if X = 0; but Z = 0 if X = 1 NOT operation is also referred to as complement operation. Basic Identities of Boolean Algebra Let X be a boolean variable and 0,1 constants 1. 2. 3. 4. X+0=X X•1 =X X+1 =1 X•0 =0 5. X + X = X 6. X • X = X 7. X + X’ = 1 8. X • X’ = 0 9. (X’)’ = X -- Zero Axiom -- Unit Axiom -- Unit Property -- Zero Property -- Idepotence -- Idepotence -- Complement -- Complement -- Involution Boolean Algebra Properties Let X,Y, and Z be boolean variables
Commutative 10. X + Y = Y + X 11. X • Y = Y • X Associative
12. X + (Y+Z) = (X+Y) + Z 13. X•(Y•Z) = (X•Y)•Z Distributive
14. X•(Y+Z) = X•Y + X•Z 15. X+(Y•Z) = (X+Y) • (X+Z) DeMorgan’s Theorem
16. (X + Y)’ = X’ • Y’ 17. (X • Y)’ = X’ + Y’ In general for DeMorgan,


( X1 + X2 + … + Xn )’ = X1’ • X2’ • … • Xn’, ( X1 • X2 • … • Xn )’ = X1’ + X2’ + … + Xn’ The Duality Principle


The dual of an expression is obtained by exchanging (• and +), and (1 and 0) in it, provided that the precedence of operations is not changed. Cannot exchange x with x’. Example:



Find the dual of expression: x’yz’ + x’y’z Answer: (x’ + y + z ’) • (x ’ + y’ + z) Dual expression does not always equal the original expression. If a Boolean equation/equality is valid, its dual is also valid. The Duality Principle (cont.) With respect to duality, Identities 1 – 8 and Properties 10 – 17 have the following relationship: 1. X + 0 = X 3. X + 1 = 1 5. X + X = X 7. X + X’ = 1 10. X + Y = Y + X 12. X + (Y+Z) = (X+Y) + Z 14. X•(Y+Z) = X•Y + X•Z 16. (X + Y)’ = X’ • Y’ 2. X • 1 = X 4. X • 0 = 0 6. X • X = X 8. X • X’ = 0 (dual of 1) (dual of 3) (dual of 5) (dual of 7) 11. X • Y = Y • X 13. X•(Y•Z) = (X•Y)•Z 15. X+(Y•Z) = (X+Y) • (X+Z) 17. (X • Y)’ = X’ + Y’ (dual of 10) (dual of 12) (dual of14) (dual of16) Absorption Property (Covering)



X + X•Y = X -- (absorption property) X•(X+Y) = X -- (dual absorption property) Proof: X + X•Y = X•1 + X•Y = X • (1 + Y) =X•1 =X Can you prove the dual absorption property? Consensus Theorem



XY + X’Z + YZ = XY + X’Z -- (theorem) (X+Y)•(X’+Z)•(Y+Z) = (X+Y)•(X’+Z) -- (dual theorem) Proof: XY + X’Z + YZ = XY + X’Z + (X+X’)YZ = XY + X’Z + XYZ + X’YZ = (XY + XYZ) + (X’Z + X’ZY) = XY + X’Z Can you prove the dual consensus theorem? Boolean Function
F(vars) = Boolean expression Operators ( +, •, ’ )
Variables
Constants ( 0, 1 )
Groupings (parenthesis)
set of binary variables
Example: F(a,b) = a’• b + b’ G(x,y,z) = x • (y + z’)
Terminology:


Literal: A variable or its complement (Example: x or b’ ). Product term: literals connected by “•” (Example: a’• b ). Sum term: literals connected by “+” (Example y + z’). Boolean Function Representations

Truth Table (unique representation) Boolean Equation





Canonical Sum-Of-Products (CSOP) form (unique) Canonical Product-Of-Sums (CPOS) form (unique) Standard Forms (NOT unique representations) Maps (unique representation) We can convert one representation of a Boolean function into another in a systematic way. Why do we need all this representations? Truth Table


Definition: tabular form that uniquely represents the relationship between the input variables of a Boolean function and its output. Enumerates all possible combinations of 1’s and 0’s that can be assigned to the binary variables and shows the binary value of the function for each possible binary combination. Truth table for an arbitrary Boolean function of three variables is shown to the right. F(x,y,z) x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 1 0 0 1 1 1 0 0 Truth Table (cont.)




Assume a Boolean function F(x1,x2,…,xN-1,xN) that depends on N variables. Question1: How many columns are there in the truth table of F(x1,x2,…,xN-1,xN) ? Question2: How many rows are there in the truth table of F(x1,x2,…,xN-1,xN) ? Answer Q1: columns = N + 1, since a column is needed for each variable and one column is needed for the values of the function. Answer Q2: rows = 2N, since there are 2N possible binary patterns/combinations for the N variables. Truth Table (cont.)


Truth table: a unique representation of a Boolean function If two functions have identical truth tables, the functions are equivalent (and vice-versa). Truth tables can be used to prove equality theorems.
Proof of the DeMorgan’s Theorem: (X + Y)’ = X’ • Y’ X Y X + Y F1 = (X + Y)’
X Y X’ Y’ F2 = X’ • Y’ 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 0 0 Observe: F1 and F2 have identical truth tables => F1 = F2, i.e., the theorem is proved However, the size of a truth table grows exponentially with the number of variables involved, hence unwieldy. This motivates the use of other representations. Canonical and Standard Forms





The Canonical and Standard forms of a Boolean functions are boolean equation representations. To introduce them we need the following definitions: Literal: A variable or its complement. Product term: literals connected by “•”. Sum term: literals connected by “+”. Minterm: a product term in which all the variables appear exactly once, either complemented or uncomplemented. Maxterm: a sum term in which all the variables appear exactly once, either complemented or uncomplemented. Minterm: Characteristic Property




A minterm of N variables defines a boolean function that represents exactly one combination (bj) of the binary variables in the truth table. The function has value 1 for that combination and value 0 for all others. There are 2N distinct minterms for N variables. A minterm is denoted by mj, where j is the decimal equivalent of the minterm’s corresponding binary combination (bj). A variable in mj is complemented if its value in bj is 0, otherwise is uncomplemented. Minterms for Three Variables

For three variables X, Y, and Z there are 23 minterms (products of 3 literals): m0 = X’•Y’•Z’ m1 = X’•Y’•Z m2 = X’•Y•Z’ m3 = X’•Y•Z m4 = X•Y’•Z’ m5 = X•Y’•Z m6 = X•Y•Z’ m7 = X•Y•Z Example: consider minterm m5:
m5 defines a boolean function that represents exactly one combination (b5=101) in the truth table, i.e., the function has value 1 for that combination and value 0 for all others. Variable Y in m5 is complemented because its value in b5 is 0. X Y Z m0 m1 m2 m3 m4 m5 m6 m7 b0 0 0 0 1 0 0 0 0 0 0 0 b1 0 0 1 0 1 0 0 0 0 0 0 b2 0 1 0 0 0 1 0 0 0 0 0 b3 0 1 1 0 0 0 1 0 0 0 0 b4 1 0 0 0 0 0 0 1 0 0 0 b5 1 0 1 0 0 0 0 0 1 0 0 b6 1 1 0 0 0 0 0 0 0 1 0 b7 1 1 1 0 0 0 0 0 0 0 1 Maxterm: Characteristic Property




A maxterm of N variables defines a boolean function that represents exactly one combination (bj) of the binary variables in the truth table. The function has value 0 for that combination and value 1 for all others. There are 2N distinct maxterms for N variables. A maxterm is denoted by Mj, where j is the decimal equivalent of the maxterm’s corresponding binary combination (bj). A variable in Mj is complemented if its value in bj is 1, otherwise is uncomplemented. Maxterms for Three Variables

For three variables X, Y, and Z there are 23 maxterms (sums of 3 literals): M0 = X+Y+Z M1 = X+Y+Z’ M2 = X+Y’+Z M3 = X+Y’+Z’ M4 = X’+Y+Z M5 = X’+Y+Z’ M6 = X’+Y’+Z M7 = X’+Y’+Z’ Example: consider maxterm M5:
M5 defines a boolean function that represents exactly one combination (b5=101) in the truth table, i.e., the function has value 0 for that combination and value 1 for all others. Variables X and Y in M5 are complemented because their values in b5 are 1. X Y Z m0 m1 m2 m3 m4 m5 m6 m7 b0 0 0 0 0 1 1 1 1 1 1 1 b1 0 0 1 1 0 1 1 1 1 1 1 b2 0 1 0 1 1 0 1 1 1 1 1 b3 0 1 1 1 1 1 0 1 1 1 1 b4 1 0 0 1 1 1 1 0 1 1 1 b5 1 0 1 1 1 1 1 1 0 1 1 b6 1 1 0 1 1 1 1 1 1 0 1 b7 1 1 1 1 1 1 1 1 1 1 0 Canonical Forms (Unique)

Any Boolean function F( ) can be expressed as a unique sum of minterms and a unique product of maxterms (under a fixed variable ordering). In other words, every function F() has two canonical forms:


Canonical Sum-Of-Products (CSOP) (sum of minterms) Canonical Product-Of-Sums (CPOS) (product of maxterms) You must realize that the words product and sum do not imply arithmetic operations in Boolean algebra; instead they specify the logical operations AND and OR, respectively. Canonical Sum-Of-Products


It is a sum of minterms. The minterms included are those mj such that F( ) = 1 in row j of the truth table for F( ). Example:
Truth table for F(X,Y,Z) at right.
The canonical sum-of-products form for F is: F(X,Y,Z) = m1 + m2 + m4 + m6 = = X’Y’Z + X’YZ’ + XY’Z’ + XYZ’. X 0 0 0 0 Y 0 0 1 1 Z 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 F 0 1 m1 =X’Y’Z 1 m2 =X’YZ’ 0 1 m4 =XY’Z’ 0 1 m6 =XYZ’ 0 Canonical Product-Of-Sums


It is a product of maxterms. The maxterms included are those Mj such that F( ) = 0 in row j of the truth table for F( ). Example:
Truth table for F(X,Y,Z) at right. X 0 0 0 0 Y 0 0 1 1 Z 0 1 0 1 The canonical product-of-sums form for F is: F(X,Y,Z) = M0 • M3 • M5 • M7 = = (X+Y+Z) • (X+Y’+Z’) • (X’+Y+Z’) • (X’+Y’+Z’). 1 1 1 1 0 0 1 1 0 1 0 1
F 0 M0 =X+Y+Z 1 1 0 M3 =X+Y’+Z’ 1 0 M5 =X’+Y+Z’ 1 0 M7 =X’+Y’+Z’ Shorthand: ∑ and ∏


F(X,Y,Z) = m1 + m2 + m4 + m6 = = X’Y’Z + X’YZ’ + XY’Z’ + XYZ’ = = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6) indicates that the minterms to be included are m1, m2, m4, and m6. F(X,Y,Z) = M0 • M3 • M5 • M7 = = (X+Y+Z) • (X+Y’+Z’) • (X’+Y+Z’) • (X’+Y’+Z’) = = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7) indicates that the maxterms to be included are M0, M3, M5, and M7. ∑ m(1,2,4,6) = ∏ M(0,3,5,7) = F(X,Y,Z) Conversion Between Canonical Forms

Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with those that do not. Example: F(X,Y,Z) = X’Y’Z + X’YZ’ + XY’Z’ + XYZ’ = m1 + m2 + m4 + m6 = ∑m(1,2,4,6) = ∏M(0,3,5,7) = (X+Y+Z)•(X+Y’+Z’)•(X’+Y+Z’)•(X’+Y’+Z’) Standard Forms (NOT Unique)
There are two types of standard forms:
Sum-of-Products (SOP) forms (NOT unique)

Product-of-Sums (POS) form (NOT unique)



A Boolean function may have more than one SOP representation. A Boolean function may have more than one POS representation. Standard forms of a Boolean function are “like” canonical forms, except that not all variables need appear in the individual product (SOP) or sum (POS) terms. X Y Z Example1: 0 0 0 F(X,Y,Z) = X’Y’Z + X’YZ’ + XZ’ 0 0 1 F(X,Y,Z) = X’Y’Z + YZ’ + XZ’ 0 1 0 are two standard sum-of-products forms 0 1 1 Example2: 1 0 0 F(X,Y,Z) = (X+Y+Z) • (X+Y’+Z’) • (X’+ Z’) 1 0 1 F(X,Y,Z) = (X+Y+Z) • (Y’+Z’) • (X’+ Z’) are tow standard product-of-sums form. 1 1 0 1 1 1 F 0 1 1 0 1 0 1 0 Conversion of SOP from Standard to Canonical form



Expand non-canonical terms by inserting equivalent of 1 in each missing variable V: (V + V’) = 1 Remove duplicate minterms. Example: X Y Z F F(X,Y,Z) = X’Y’Z + YZ’ + XZ’ = 0 0 0 0 = X’Y’Z + (X+X’)YZ’ + X(Y+Y’)Z’ 0 0 1 1 1 = X’Y’Z + XYZ’ + X’YZ’ + XYZ’ + XY’Z’ 0 1 0 0 1 1 0 = X’Y’Z + XYZ’ + X’YZ’ + XY’Z’ 1 0 0 1 1 0 1 0 Can you do it: 1 1 0 1 F(X,Y,Z) = X’Y’Z + X’YZ’ + XZ’ 1 1 1 0 Conversion of POS from Standard to Canonical form



Expand non-canonical terms by adding 0 in terms of missing variables (e.g., V•V’ = 0) and using the distributive law. Remove duplicate maxterms. Example: F(X,Y,Z) = (X+Y+Z)•(Y’+Z’)•(X’+Z’) = X Y Z F = (X+Y+Z)•(XX’+Y’+Z’)•(X’+YY’+Z’) 0 0 0 0 0 0 1 1 = (X+Y+Z)•(X+Y’+Z’)•(X’+Y’+Z’)• 0 1 0 1 (X’+Y+Z’)•(X’+Y’+Z’) 0 1 1 0 = (X+Y+Z)•(X+Y’+Z’)•(X’+Y’+Z’)• 1 0 0 1 (X’+Y+Z’) 1 0 1 0 Can you do it for: 1 1 0 1 0 F(X,Y,Z) = (X+Y+Z)•(X+Y’+Z’)•(X’+ Z’) 1 1 1 Complementation: Example Consider function F(X,Y,Z) = X’YZ + XY’Z’
Table method
X Y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
Z 0 1 0 1 0 1 0 1 F 0 0 0 1 1 0 0 0 F’ 1 1 1 0 0 1 1 1 DeMorgan method: F’ = ( X’YZ + XY’Z’ )’ -- apply DeMorgan = (X’YZ)’ • (XY’Z’)’ -- DeMorgan again = (X+Y’+Z’) • (X’+Y+Z) Dual method: F = (X’YZ) + (XY’Z’) -- interchange “•”
 “+” to find the dual of F G = (X’+Y+Z)•(X+Y’+Z’) G is the dual of F -- complement each literal to find F’ F’ = (X+Y’+Z’) • (X’+Y+Z) Inverter (NOT Gate)
The NOT gate implements the basic Boolean function inversion (F2). Graphical Symbol X
Algebraic Equation F F = X’ Operation of the NOT gate:

Output F is 1 if input X = 0; Output F is 0 if input X = 1; Truth Table X F 0 1 1 0 AND Gate
The AND gate implements the basic Boolean function AND (G9). Graphical Symbol X Y
F F=X•Y Operation of the AND gate:

Algebraic Equation Truth Table X Y F 0 0 0 0 1 0 1 0 0 1 1 1 Output F is 1 if and only if input X=1 and input Y=1; There are AND gates with more than two inputs.

F = X1 • X2 • … • Xn Output F is 1 if and only if all inputs Xj are 1 OR Gate
The OR gate implements the basic Boolean function OR (G15). Graphical Symbol X Y
F F=X+Y Operation of the OR gate:

Algebraic Equation Truth Table X Y F 0 0 0 0 1 1 1 0 1 1 1 1 Output F is 0 if and only if input X=0 and input Y=0; There are OR gates with more than two inputs.

F = X1 + X2 + … + Xn Output F is 0 if and only if all inputs Xj are 0 NAND Gate
The NAND gate implements the basic Boolean function NOT-AND (G8). Graphical Symbol X Y
F F = (X • Y)’ Operation of the NAND gate:

Algebraic Equation Truth Table X Y F 0 0 1 0 1 1 1 0 1 1 1 0 Output F is 0 if and only if input X=1 and input Y=1; There are AND gates with more than two inputs.

F = (X1 • X2 • … • Xn)’ Output F is 0 if and only if all inputs Xj are 1 NOR Gate
The NOR gate implements the basic Boolean function NOT-OR (G2). Graphical Symbol X Y
F F = (X + Y)’ Operation of the NOR gate:

Algebraic Equation Truth Table X Y F 0 0 1 0 1 0 1 0 0 1 1 0 Output F is 1 if and only if input X=0 and input Y=0; There are NOR gates with more than two inputs.

F = (X1 + X2 + … + Xn) Output F is 1 if and only if all inputs Xj are 0 XOR Gate
The XOR gate implements the basic Boolean function Exclusive-OR (G7). Graphical Symbol X Y
F F = XY’ + X’Y = X⊕Y Operation of the XOR gate:

Algebraic Equation Truth Table X Y F 0 0 0 0 1 1 1 0 1 1 1 0 Output F is 1 if and only if input X is not equal to input Y There are XOR gates with more than two inputs.

F = (X1 ⊕ X2 … ⊕ Xn) (it is called odd function) Output F is 1 if and only if odd number of inputs Xj are 1 XNOR Gate
The XNOR gate implements the basic Boolean function Exclusive-NOR (G10). Graphical Symbol X Y
F F = XY + X’Y’ = (X⊕Y)’ Operation of the XNOR gate:

Algebraic Equation Truth Table X Y F 0 0 1 0 1 0 1 0 0 1 1 1 Output F is 1 if and only if input X is equal to input Y There are XNOR gates with more than two inputs.

F = (X1 ⊕ X2 … ⊕ Xn)’ (it is called even function) Output F is 1 if and only if even number of inputs Xj are 1 Combinational Logic Circuits from Boolean Functions




Logic Gates implement basic Boolean functions. Using a set of basic Boolean functions called a Logic Basis, we can represent any Boolean function. Thus, the Logic Gates that implement the functions in a Logic Basis can be used to implement any Boolean function. Outputs of Logic Gates are connected to inputs of other gates to form a Combinational Logic Circuit. Combinational Logic Circuits implement Boolean functions. Combinational Logic Circuits from Boolean Functions in basis AND-OR-NOT


Any Boolean function can be implemented using only AND, OR and NOT gates. Consider Boolean function F = A’ + B•C’ + A’•B’ A combinational logic circuit can be constructed to implement F, by appropriately connecting input signals and logic gates :


Circuit input signals
from function variables (A, B, C) Circuit output signal
function output (F) Logic gates
from logic operations A B C F Combinational Logic Circuits from Boolean Functions (cont.) C F = A’ + B•C’ + A’•B’ A F B C G = A’ + B•C’ B A G Digital Logic Circuits Physical Implementation Basics Overview
Integrated Circuits


CMOS Circuits



Propagation Delay of Gates and Logic Circuits Size of Gates and Logic Circuits Design Trade-Offs


MOS Transistors as Switches Basic Gates as CMOS circuits Basic Technology Parameters

Level of Integration Integrated Circuit Technologies Two-Level Circuit Optimization Multiple-Level Circuit Optimization Basic Assumption for Logic Gates Integrated Circuits (ICs)




Digital Systems are made out of digital circuits. Certain well defined basic (small) digital circuits are called Logic Gates. Gates have inputs and outputs and perform specific mathematical logic operations. Outputs of gates are connected to inputs of other gates to form a digital logic circuit. Digital logic circuits are physically implemented using transistors and interconnections in complex semiconductor devices called integrated circuits. Integrated Circuits - Level of Integration




An IC is a silicon semiconductor crystal (chip) that contains a network of transistors. The number of transistors determines the Level of Integration: Small-scale Integration (SSI) Several transistors (<40) per chip. Medium-scale Integration (MSI) Between 40-400 transistors per chip. Perform basic digital functions, e.g., 4-bit addition, multiplication, etc. Large-scale Integration (LSI) Between 400 and a few thousands of transistors per chip. Implement digital systems, e.g. small processors and memories. Very Large-scale Integration (VLSI) Several thousands to over 1 billion transistors per chip. Implements complex digital systems, e.g., complex microprocessors, multi-processor systems on-chip, etc. 

Digital Design Digital Systems: General Remarks

A Digital System manipulates discrete elements/quantities of information Discrete quantities of information emerge from:



Early computer systems were used mostly for numeric computations: the discrete elements used were the digits, hence the term digital computer/system emerged. In general, any system uses an alphabet (set of symbols) to represent information


the nature of the data being processed the data may be purposely quantized from continues values The English language system uses an alphabet of 26 symbols (letters) The decimal number system uses an alphabet of 10 symbols (digits) What about the alphabet of the Digital Systems? The Digital Systems’ Alphabet is Binary
Digital Systems use only one alphabet with two symbols (digits) ‘0’ and ‘1’ (hence binary ).


A binary digit is called a bit Information is represented by groups of bits Why is a binary alphabet used?


Digital systems have a basic building block called a switch, that can only be “on” or “off”, i.e., two discrete values ‘0’ and ‘1’ can be distinguished. An electric device, called a transistor, physically implements the switch. The two discrete values are physically represented by ranges of voltage values called HIGH and LOW.


“on” (closed) switch corresponds to bit value ‘0’ and is represented by LOW voltage value (between 0.0 and 1.0 Volt). “off” (open) switch corresponds to bit value ‘1’ and is represented by HIGH voltage value (between 4.0 and 5.0 Volts). Basic Digital System Structure

Storage
cpu control unit data path
Input/Output
CPU: Central Processing Unit Data Path: arithmetic and logic operations Control Unit: make sure that the sequence of data path operations is correct Storage: no memory = no system Input/Output: allow the system to interact with the outside world Information Representation



All information in Digital Systems is represented in binary form. All information that is not binary is converted to binary before processed by a Digital Systems. Decimal numbers are expressed in the binary number system or by means of a binary code. How is this done?

That is not too difficult, once we understand how all number systems, not only the decimal one (0-9), have a similar formal representation and how a number in one number system can be converted into another. Number Systems Number Systems are employed in arithmetic to represent numbers by strings of digits. There are two types of number systems:
Positional number systems

The meaning of each digit depends on its position in the number. Example:


Decimal number system (we know it very well and use it in everyday arithmetic). 585.5 is a decimal number in positional code – “5 hundreds plus 8 tens plus 5 units plus 5 tenths”. The hundreds, tens, units, and tenths are powers of 10 implied by the position of the digits. Decimal number system is said to be of base or radix 10 because it uses 10 distinct digits (0 – 9) and the digits are multiplied by power of 10: 585.5 = 5x102 + 8x101 + 5x100 + 5x10-1
Non-positional number systems
Old Roman numbers: for example, XIX equals to 19 Positional Number Systems We can represent numbers in any number system with base r
Number in positional code
(An-1An-2…A1A0.A-1A-2…A-m+1A-m)r
r is the base (radix) of the system, r ∈ {2, 3, …, I}.
every digit Ai ∈ {0, 1, 2, …, r-1}, where {0, 1, 2, …, r-1} is the digit set.
“.” is called the radix point.


Number in base r expressed as power series of r

An-1 is referred to as the most significant digit. A-m is referred to as the least significant digit. An-1 r n-1 + An-2 r n-2 +…+ A1 r 1 + A0 r 0 + A-1 r -1 + A-2 r -2 +…+ A-m+1 r –m+1 + A-m r -m Example: a number in number systems with base 5
(132.4)5 = 1x52 + 3x51 + 2x50 + 4x5-1 = 25 + 15 + 2 + 0.8 = (42.8)10 Binary Number System This is the system used for arithmetic in all digital computers
Number in positional code
(bn-1bn-2…b1b0.b-1b-2…b-m+1b-m)r
r = 2 is the base of the binary system.




Number in base 2 expressed as power series of 2

every digit bi ∈ {0, 1} the digits bi in a binary number are called bits bn-1 is referred to as the most significant bit (MSB). b-m is referred to as the least significant bit (LSB). bn-1 2 n-1 + bn-2 2 n-2 +…+ b1 2 1 + b0 2 0 + b-1 2 -1 + b-2 2 -2 +…+ b-m+1 2 –m+1+ b-m 2 -m Example: a number in the binary number system
(1011.01)2 = 1x23 + 0x22 + 1x21 + 1x20 + 0x2-1 + 1x2-2 = 8 + 2 + 1 + 0.25 = (11.25)10 Burn this table into your memory Power of Two n 2 0 n n 2 1 5 1 2 2 n n n 2 32 10 1024 6 64 11 2048 4 7 128 12 4096 3 8 8 256 13 8192 4 16 9 512 14 16384 210 = 1,024 is 1 K (k ilo) 2 20 is 1 M (m e ga ) 230 is 1 G (giga ) Other Useful Number System Apart from the ordinary binary number system, the octal (base-8) and the hexadecimal (base-16) number systems are useful for representing binary quantities indirectly because their bases are powers of two. These systems have a more compact representation of binary quantities.
Octal number system




(on-1on-2…o1o0.o-1o-2…o-m+1o-m)8 every digit oi ∈ {0, 1, 2, 3, 4, 5, 6, 7}. on-1 8 n-1 + on-2 8 n-2 +…+ o1 8 1 + o0 8 0 + o-1 8 -1 + o-2 8 -2 +…+ o-m+1 8 –m+1 +o-m 8 -m (127.4)8 = 1x82 + 2x81 + 7x80 + 4x8-1 = (87.5)10 = (001 010 111.100)2 Hexadecimal number system



(hn-1hn-2…h1h0.h-1h-2…h-m+1h-m)16 every digit hi ∈ {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}. hn-1 16 n-1 + hn-2 16 n-2 +…+ h1 16 1 + h0 16 0 + h-1 16 -1 + h-2 16 -2 +…+ h-m+1 16 –m+1 + h-m 16 –m (B6F.4)16 = 11x162 + 6x161 + 15x160 + 4x16-1 = (2927.25)10 = (1011 0110 1111.0100)2 Another Important Table Decimal (base 10) Binary (base 2) Octal (base 8) Hex (base 16) 0 0000 00 0 1 0001 01 1 2 0010 02 2 3 0011 03 3 4 0100 04 4 5 0101 05 5 6 0110 06 6 7 0111 07 7 8 1000 10 8 9 1001 11 9 10 1010 12 A 11 1011 13 B 12 1100 14 C 13 1101 15 D 14 1110 16 E 15 1111 17 F Conversion from base r to Decimal The conversion of a number in base r to decimal number (base 10) is done by expanding the number in power series and adding all the terms as shown below: (An-1An-2…A1A0.A-1A-2…A-m+1A-m)r = An-1 r n-1 + An-2 r n-2 +…+ A1 r 1 + A0 r 0 + A-1 r -1 + A-2 r -2 +…+ A-m+1 r –m+1 + A-m r -m
Example of converting Binary (base 2) to Decimal (base 10): (1011.01)2 = 1x23 + 0x22 + 1x21 + 1x20 + 0x2-1 + 1x2-2 = 8 + 2 + 1 + 0.25 = (11.25)10
Example of converting number in base 5 to Decimal (base 10): (132.4)5 = 1x52 + 3x51 + 2x50 + 4x5-1 = 25 + 15 + 2 + 0.8 = (42.8)10 Example of converting Octal (base 8) to Decimal (base 10): (127.4)8 = 1x82 + 2x81 + 7x80 + 4x8-1 = (87.5)10
Example of converting Hexadecimal (base 16) to Decimal (base 10): (B6F.4)16 = 11x162 + 6x161 + 15x160 + 4x16-1 = (2927.25)10
Conversion from Decimal to base r The conversion is done as follows: 1) If the number has a radix point then separate the number into an integer part and a fraction part, since the two parts must be converted differently. 2) The conversion of a decimal integer part to a number in base r is done by dividing the integer part and all successive quotients by r and accumulating the remainders. 3) The conversion of a decimal fraction part to a number in base r is done by multiplying the fractional parts by r and accumulating integers.
Example of converting Decimal (base 10) to Binary (base 2): (41.6875)10 Converting the integer part (41)10 : Converting the fraction part (0.6875)10 : 41/2 = 20 + 1/2 20/2 = 10 + 0/2 10/2 = 5 + 0/2 5/2 = 2 + 1/2 2/2 = 1 + 0/2 1/2 = 0 + 1/2 0.6875 x 2 = 1.3750 Integer = 1 0.3750 x 2 = 0.7500 0 0.7500 x 2 = 1.5000 1 0.5000 x 2 = 1.0000 1 (0.6875)10 = (0.1011)2 Remainder = 1 0 0 1 0 1 (41)10 = (101001)2 LSB MSB LSB MSB (41.6875)10 = (101001.1011)2 Other Conversions

Binary to Octal or Hexadecimal: grouping bits starting from the radix point
(1101010.01)2 to Octal (groups of 3): (001|101|010.010|)2 = (152.2)8
(1101010.01)2 to Hex (groups of 4): (0110|1010.0100|)2 = (6A.4)16 Octal to Binary: convert each digit to binary using 3 bits

Hexadecimal to Binary: convert each digit to binary using 4 bits

(7A5F.C)16 = (0111 1010 0101 1111. 1100)2 = (111101001011111.11)2 Hexadecimal to Octal

(475.2)8 = (100 111 101. 010)2 Hexadecimal
Binary
Octal Octal to Hexadecimal
Octal
Binary
Hexadecimal Number Ranges





The range of numbers in base (radix) r depends on the number of digits used to represent the numbers. Assume the number (An-1An-2…A1A0.A-1A-2…A-m+1A-m)r represented by n digits for the integer part and m digits for the fraction part. The smallest integer number is 0 and the larges is (r-1) r n-1 + (r-1) r n-2 + …+ (r-1)r 1 + (r-1) r 0 = rn-1 ,i.e., the range is from 0 to rn-1 The smallest fraction number is 0.0 and the largest is (r-1) r -1 + (r-1) r -2 + …+ (r-1) r –m+1 + (r-1) r –m = 1- r –m ,i.e., the range is from 0.0 to 1- r –m The range of numbers is from 0.0 to rn - r –m Examples:




Largest 3-digit integer decimal (base 10) number is 103-1 = 1000 - 1 = 999 Largest 8-digit integer binary (base 2) number is (11111111)2 ,i.e., 28-1 = 255 Largest 5-digit decimal (base 10) fraction is 1-10-5 = 1 – 0.00001 = 0.99999 Largest 16-digit binary (base 2) fraction is 1-2-16 = 0.9999847412 What about the range of negative numbers? Representations of Numbers in Digital Computers (1)
Numbers are represented in binary format as strings of bits




Bit is the smallest binary quantity with a value of 0 or 1. Byte is a string (sequence) of eight bits. Word is a string (sequence) of n bits (n > 8). In most cases n is a power of 2 (n = 24 = 16, n = 25 = 32, n = 26 = 64, etc…). Examples
bit: 1 byte: 01101111 16-bit word: 11110100 10001010 Positive Integer Numbers

Positive integers and the number zero can be represented as unsigned binary numbers using a byte or an n-bit word. Magnitude representation – number N in binary having n bits.

Radix complement ( r’s complement ) representation in our case 2’s complement – Given number N in binary having n bits, the 2’s complement of N is defined as 2n – N .

Example: 00001001 ( represents integer number 9 using 8 bits ). Example: 11110111 ( 2’s complement of integer number 9 ). Diminished radix complement ( (r-1)’s complement ) representation in our case 1’s complement - Given number N in binary having n bits, the 1’s complement of N is defined as (2n – 1) – N .
Example: 11110110 ( 1’s complement of integer number 9 ). Representations of Numbers in Digital Computers (2)
Positive and Negative Integer Numbers

Positive and negative integers and the number zero can be represented as signed binary numbers using a byte or an n-bit word where the most significant bit is interpreted as a sign bit. The convention is to make the sign bit 0 for positive numbers and 1 for negative numbers. Signed-Magnitude representation


Signed-Radix complement ( signed-r’s complement ) representation in our case signed-2’s complement


Example: 0|0001001 ( signed-2’s complement of integer number +9 ). Example: 1|1110111 ( signed-2’s complement of integer number -9 ). Signed-Diminished radix complement ( signed-(r-1)’s complement ) representation in our case signed-1’s complement


Example: 0|0001001 ( represents integer number +9 using 8 bits ). Example: 1|0001001 ( represents integer number -9 using 8 bits ). Example: 0|0001001 ( signed-1’s complement of integer number +9 ). Example: 1|1110110 ( signed-1’s complement of integer number -9 ). How do we get the signed complements? Arithmetic Operations
Arithmetic operations with numbers in base r follow the same rules as for decimal numbers.
Examples: addition, subtraction, and multiplicationMultiplicand: in base-2. Carries: 111 Augend: 10110 + Addend: 01110 Sum: 100100 Borrows: Minuend: 00110 Subtrahend: 11101 Difference: 11 -11101 00110 -10111 1010 Multiplier: 101 1010 + 0000 1010 Product: 110010 x


In Digital Computers arithmetic operations are done with the binary number system (base-2) - Binary Arithmetic. In many cases binary subtraction is done in a special way by binary addition. Why?

It is much more simple to do it that way. One simple building block called adder can be implemented and used for both binary addition and subtraction. Unsigned Binary Subtraction
Binary subtraction by 2’s complement addition



Assume two n-bit unsigned numbers M and N, M - N can be done as follows: Add the 2’s complement of N to M. This performs the sum M + (2n - N) = = M – N + 2n . If M ≥ N, the sum produces an end carry, 2n. We can discard it, leaving the correct result M – N. If M < N, the sum does not produces an end carry since it is equal to 2n – (N - M), which is the 2’s complement of N – M. To obtain the correct result take the 2’s complement of the sum, i.e., 2n – (2n – (N - M)) = (N - M) and place a minus sign in front. Examples: 15 1111 (15) + 5 1011 (2’s compl. of 5) 10 1 1010 (the sum)
discard carry - 5 15 -10 no carry + 0101 (5) 0001 (2’s compl. of 15) 0110 (the sum) correction is needed -1010 ( “-” 2’s compl. of sum )
What about binary subtraction by 1’s complement addition?
Fall 2005 I leave this for you as a home work (see the course web page) !!! Digital Technique by Todor Stefanov, Leiden University Signed Binary Addition/Subtraction
Signed binary addition using 2’s complement representation


Assume two n-bit signed numbers M and N represented in signed-2’s complement format. The sum M + N can be obtained as follows: Add M to N, including their sign bits to get the correct sum in signed-2’s complement format. A carry out of the sign bit position is discarded. Examples: (- 9) + (+ 5) (- 4) 1|0111 0|0101 1|1100 (- 9) 1|0111 + (- 5) 1|1011 (-14) 11|0010 (+ 9) + (+ 5) (+14) 0|1001 0|0101 0|1110 (+ 9) 0|1001 1|1011 (+ 4) 10|0100 + (- 5) discard discard
Signed binary subtraction using 2’s complement representation


Assume two n-bit signed numbers M and N represented in signed-2’s complement format. The difference M - N can be obtained as follows: Take the 2’s complement of N (including the sign bit) and add it to M (including the sign bit). A carry out of the sign bit position is discarded. Examples: (- 9) - (- 5) (- 4) 1|0111 1|1011 + 1|0111 0|0101 1|1100 (- 9) - (+ 5) (-14) 1|0111 0|0101 1|0111 1|1011 11|0010 + discard Decimal Codes

The binary number system is the most natural system for a digital computer, but people are accustomed to the decimal system. How to resolve this difference?


Convert decimal numbers to binary, perform all arithmetic calculations in binary, and then convert the binary result back to decimal. You already know how to do this. Digital computers can do this as well, but:

We have to store the decimal numbers in the computer in a way that they can be converted to binary. Since the computer can accept only binary values, we must represent the decimal digits by a code that contains 1’s and 0’s. Binary Coded Decimals (BCD)


The BCD code is the most commonly used code. Each decimal digit (0, 1, 2, …, 9) is coded by a 4-bit string (half a byte) called BCD digit. A decimal number is converted to a BCD number by replacing each decimal digit of the number with the corresponding BCD digit code. Example: (369)10 = ( 0011 0110 1001 )BCD = (101110001)2 3 6 9
A BCD number needs more bits than its equivalent binary value. However, the advantages of using BCD are:


Computer input and output data are handled by people who use the decimal system. BCD numbers are decimal numbers (not binary numbers) even though they are represented in bits. Computers can store decimal numbers using BCD, convert the BCD numbers to binary, perform binary operations, and convert the result back to BCD. (1) Decimal Digit BCD Digit 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 Note: the binary combinations 1010 through 1111 are not used and have no meaning in the BCD code. Other Useful Decimal Codes: Excess-3 Code
Given a decimal digit n, its corresponding excess-3 codeword is (n+3)2 Decimal

Example: n=5
n+3=8
1000excess-3 n=0
n+3=3
0011excess-3 Decimal number in Excess-3 code.
Example: (158)10 = ( 0100 1000 1011 )excess-3 = (10011110)2 1+3 5+3 8+3
Digit Excess-3 Digit 0 0011 1 0100 2 0101 3 0110 4 0111 5 1000 6 1001 7 1010 8 1011 9 1100 Useful in some cases for digital arithmetic, e.g., decimal subtraction. 

Combinational Logic Design Overview



Combinational Circuits Design Procedure Examples: Code Converters Binary Decoders





Binary Encoders Priority Encoders Multiplexers (MUXs)



Functionality Circuit Implementation with Decoders Expansion Functionality Circuit Implementation with MUXs Expansions Demultiplexers Combinational Circuits



A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables, there are 2n possible binary input combinations. For each binary combination of the input variables, there is one possible binary value on each output. Hence, a combinational circuit can be described by:

A truth table that lists the output values for each combination of the input variables, or m Boolean functions, one for each output variable. n-inputs •• • Combinational Circuit •• • m-outputs Combinational vs. Sequential Circuits
Combinational circuits are memory-less. Thus, the output values depend ONLY on the current input values. m Combinational m-outputs n-inputs Circuit
Sequential circuits (Will be discussed later in the course) consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements). m-outputs n-inputs Combinational Storage Circuit Present Elements Next state state n Combinational Circuit Design

Design of a combinational circuit is the development of a circuit from a description of its function. Starts with a problem specification and produces a logic diagram or set of Boolean equations that represent the circuit. Design Procedure 1. 2. 3. 4. 5. Determine the required number of inputs and outputs and assign variables to them. Derive the truth table that defines the required relationship between inputs and outputs. Obtain and simplify the Boolean function (K-maps, algebraic manipulation, CAD tools, …). Consider any design constraints (area, delay, power, available libraries, etc). Draw the logic diagram. Verify the correctness of the design. Design Example
Design a combinational circuit with 4 inputs that generates a 1 when the # of 1s equals the # of 0s or the # of 1s equals to 1. Use only 2-input NAND gates. More Examples - Code Converters
Code Converters transform/convert information from one code to another:
BCD-to-Excess-3 Code Converter

Useful in some cases for digital arithmetic BCD-to-Seven-Segment Converter
Used to display numeric info on 7 segment displays BCD-to-Excess-3 Code Converter


Design a circuit that converts a binary-codeddecimal (BCD) codeword to its corresponding excess-3 codeword. Excess-3 code: Given a decimal digit n, its corresponding excess-3 codeword (n+3)2 Example: n=5
n+3=8
1000excess-3 n=0
n+3=3
0011excess-3 We need 4 input variables (A,B,C,D) and 4 output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D). BCD-to-Excess-3 Converter (cont.)

The truth table relating the input and output variables is shown below. Note that the outputs for inputs 1010 through 1111 are don't cares (not shown here). Maps for BCD-to-Excess-3 Converter The K-maps for outputs W, X, Y, Z are constructed using the don't care terms BCD-to-Excess-3 Converter (cont.) W = A + BC + BD = A + B(C+D) X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’ Y = CD + C’D’ Z = D’ Another Code Converter Example: BCD-to-Seven-Segment Converter


Input is a 4-bit BCD code
4 inputs (w, x, y, z). Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. Example: a

Input: 0000BCD Output: 1111110 (a=b=c=d=e=f=1, g=0) f b g e c d BCD-to-Seven-Segment (cont.) Truth Table Digit wxyz abcdefg Digit wxyz abcdefg 0 0000 1111110 8 1000 1111111 1 0001 0110000 9 1001 111X011 2 0010 1101101 1010 XXXXXXX 3 0011 1111001 1011 XXXXXXX 4 0100 0110011 1100 XXXXXXX 5 0101 1011011 1101 XXXXXXX 6 0110 X011111 1110 XXXXXXX 7 0111 11100X0 1111 XXXXXXX a ?? f g b e c d Design Procedure for Complex Circuits


In general, digital systems are complex and sophisticated, i.e., they consists of millions of gates. It is impossible to design each and every circuit from scratch using the procedure you have just seen. There is not practical formal procedure to design complex digital circuits. Currently the design is more an art than a science! How to design complex digital circuits? Design Procedure for Complex Circuits





Fortunately, complex digital circuits can be implemented as composition of smaller and simpler circuits. These smaller and simpler circuits are fundamental and we call them basic functional blocks. Reuse basic functional blocks to design new circuits. Use Design Hierarchy Use Top-Down, Bottom-Up, or Meet in the Middle Design Approaches Use Computer-Aided Design (CAD) tools



Schematic Capture tools Hardware Description Languages (HDL) Logic Simulators Logic Synthesizers 1-bit Adder

Performs the addition of two binary bits. Four possible operations:




0+0=0 0+1=1 1+0=1 1+1=10 Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry. Half Adder




Performs 1-bit addition. Inputs: A0, B0 Outputs: S0, C1 Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Boolean equations:

S0 = A0B0’+A0’B0 = A0 ⊕ B0 C1 = A0B0 Truth Table A0 B0 S0 C1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Half Adder (cont.)

S0 = A0B0’+A0’B0 = A0⊕ B0 C1 = A0B0 Block Diagram Logic Diagram B0 A0 A0 C1 1 bit half adder S0 B0 S0 C1 n-bit Addition

Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. Example: Let n=4 Cout C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 ------------------S3 S2 S1 S0
1 1 0 1 0 1 1 0 1 +1 1 0 1 ------------1 0 1 0 Notice that in each column we add 3 bits! Full Adder

Combinational circuit that performs the additions of 3 bits (two bits and a carry-in bit). Full Adder is used for addition of n-bit binary numbers (for higher-order bit addition). Ai Bi Block Diagram Ci+1 1 bit full adder Si Ci Truth Table Ai Bi Ci Si Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Full Adder (cont.)
K-maps: BiCi K-map for Si Ai 0 Ai 1 Bi 00 01 11 10 1 1 1 1 BiCi K-map for Ci+1 Ai 0 Ai 1 Ci
Boolean equations:



Bi 00 01 11 10 1 1 1 1 Ci Ci+1 = AiBi + AiCi + BiCi Si = AiBi’ Ci’ + Ai’Bi’Ci + Ai’BiCi’ + AiBiCi = Ai ⊕ Bi ⊕ Ci You can design full adder circuit directly from the above equations (requires 3 ANDs and 1 OR for Ci+1 and 2 XORs for Si) Can we do better? Full Adder using 2 Half Adders
A full adder can also be realized with two half adders and an OR gate, since Ci+1 can also be expressed as:

Ai Bi Ci+1 = AiBi + AiCi + BiCi = AiBi + Ai(Bi+Bi’)Ci + (Ai+Ai’)BiCi = AiBi + AiBiCi + AiBi’Ci + AiBiCi + Ai’BiCi = AiBi(1+Ci +Ci) + Ci(AiBi’ + Ai’Bi) = AiBi + Ci(Ai ⊕ Bi) Si = Ai ⊕ Bi ⊕ Ci Si Ci+1 Ci n-bit Combinational Adders


Perform parallel addition of n-bit binary numbers. Ripple Carry Adder
Simple design.
Time consuming. Why? (you’ll see …) Carry Lookahead Adder
More complex than ripple-carry adder.
Reduces circuit delay. n-bit Ripple Carry Adder


C4 C3 C2 C1 C0 Constructed using n 1-bit full adder A3 A2 A1 A0 blocks in parallel. + B3 B2 B1 B0 Cascade the full adders so that the carry -------------------------out from one becomes the carry in to the S3 S2 S1 S0 next higher bit position. Example: 4-bit Ripple Carry Adder Ripple Carry Adder Delay

Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C0) to the MSB (Cn). Let the delay in a 1-bit FA be ∆. Then, the delay of an n-bit ripple carry adder is n∆. Carry Look-ahead Adder

Alternative design for a combinational n-bit adder. Reduced delay at the expense of more complex hardware. Ripple Carry Delay (RD) Carry Look-ahead Delay (LD) LD < RD
Study this circuit in detail using the textbook. Block Diagram for Subtractor M0M1M2M3 N0N1N2N3 B 4-bit Subtractor If B = 1 then N>M Selective 2’s Complementer Subtract numbers M-N Correct the result if N>M Enabled when B=1; otherwise, just pass the result from the subtractor Not the best way to implement a subtractor circuit! Block Diagram for Binary Adder-Subtractor N0N1N2N3 M0M1M2M3



Binary Adder



B 4-bit Subtractor Selective 2’s Complementer Sub/Add Sub/Add=1  Result=|M-N| Sub/Add=0  Result=M+N 2-to-1 4-line MUX Result Again, not the best way to implement a Sub/Add circuit! Binary Adder/Subtractors

If we perform subtraction using complements, we eliminate the subtraction operation, and thus, we can use an adder with appropriate complementer for subtraction. Actually, we can use an adder for both addition and subtraction:




Complement subtrahend for subtraction Do not complement subtrahend for addition Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder. The subtraction A-B can be performed by taking the 2's complement of B and adding to A. The 2's complement of B can be obtained by complementing B and adding one to the result. A-B = A + 2C(B) = A + 1C(B) + 1 = A + B’ + 1 4-bit Binary Adder-Subtractor using 2’s Complement Adder Selective complementer: XOR gates act as programmable inverters 4-bit Binary Adder-Subtractor (cont.) S=0 B3 B2 B1 B0 0
When S = 0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched. 4-bit Binary Adder-Subtractor (cont.) S=1 B3’ B2’ B1’ B0’ 1
When S = 1, the circuit performs A - B , i.e., A - B = A + 2C(B) = A + 1C(B) + 1 = A + B’ + 1 The Overflow problem


If the sum of two n-bit numbers results in an n+1 number, then an overflow conditions is said to occur. Detection of overflow can be implemented using either hardware or software. Detection depends on number system used: signed or unsigned. The Overflow problem in Unsigned System
Addition:

Subtraction:

When Carry out is 1 we have overflow. Can never occur. Magnitude of the result is always equal or smaller than the larger of the two numbers.
Not REALLY a problem! V Cn n-bit Adder/Subtractor • V = 1 indicates overflow condition when adding unsigned numbers. Binary Multiplier
Binary multiplication resembles decimal multiplication:




n-bit multiplicand is multiplied by each bit of the m-bit multiplier, starting from LSB, to form m partial products. Each successive partial product is shifted 1 bit to the left. Derive result by addition the m rows of partial products. The resultant product is a binary number that consists of n + m bits. Example:


Multiplicand B = (1011)2 Multiplier A = (101)2 Find Product C = B x A: Multiplicand: 1011 x Multiplier: 101 1011 + 0000 1011 Product: 110111 2-bit by 2-bit Binary Multiplier Half Adders are Sufficient since there is no Carry-in in addition to the two inputs to sum 4-bit by 3-bit Binary Multiplier 4 bit by 3 bit yields a 7 bit result Other Arithmetic Functions



Incrementing Decrementing Multiplication by Constant Division by Constant Binary Decoders


A combinational circuit that converts binary information from n coded inputs to a maximum 2n decoded outputs
n-to- 2n decoder n-to-m decoder, m ≤ 2n Enable signal (E) if E = 0 then all outputs are 0 else yj = f(x0,x1,…,xn-1) (j = 0..2n-1) 1-to-2 Decoder
1-to-2 Decoder without Enable signal Logic Symbol 1-to-2 Decoder 20 A
0 1 D0 D1 A D0 D1 0 1 0 1 0 1 Logic Circuit A D0 = A’ D1 = A D0 D1 1-to-2 Decoder with Enable signal 1-to-2 Decoder A E Truth Table and Equations 20 enable 0 1 D0 D1 E A D0 D1 0 0 0 0 0 1 0 0 1 0 1 1 1 0 A D0 E 0 D0 = EA’ 1 D = EA 1 D1 decoder enable logic logic 2-to-4 Decoder Logic Symbol A1 A0 2-to-4 Decoder 20 A0 A1 21 Truth Table and Equations D0 = A1’A0’ D0 D1 D2 D3 D1 = A1’A0 1 0 0 0 D2 = A1A0’ 0 1 0 0 D3 = A1A0 All minterms of 0 0 1 0 2 variables 0 0 0 1 D0 D1 D2 D3 0 1 2 3 0 0 0 1 1 0 1 1 Logic Circuit A1 A1 A0 A0 E 2-to-4 Decoder with Enable 2-to-4 Decoder D0 D1 D2 D3 A0 A1 20 E enable 21 0 1 2 3 D0 D0 D1 D2 D3 D1 D2 D3 3-to-8 Decoder Logic Symbol 3-to-8 Decoder A0 A1 A2 20 21 22 0 1 2 3 4 5 6 7 3-to-8 Decoder A0 A1 A2 E 0 1 20 2 1 2 3 4 22 5 6 enable 7 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Notice: D0 to D7 represent all minterms of 3 variables. 3-to-8 Decoder (Logic Circuit) n-to-2n Decoder (generalization)





n inputs, A0, A1,..., An-1, are decoded into 2n outputs, D0 through D2n-1. Each output Dj represents one of the minterms of the n input variables. Dj = 1 when the binary number (An-1…A1A0) = j Shorthand: Dj = mj The output variables are mutually exclusive; exactly one output has the value 1 at any time, and the others are 0. Due to the above properties, an arbitrary Boolean function of n variables can be implemented with n-to-2n Decoder and OR gates. Implementing Boolean Functions using Decoders
Any combinational circuit can be constructed using decoders and OR gates! Why?


Because any Boolean function can be implemented using a decoder due to the fact that a decoder implements minterm functions. Just select outputs of a decoder that implement minterms included in a Boolean function and make a logic OR of the selected outputs. Here is an example: Implement Boolean function F(W,X,Y,Z) = Σm(1,5,6,13,15)
F is a function of 4 variables
we use 4-to-16 Decoder 4-to-16 Decoder Z Y X W 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 F Another Example: Implementing a Binary Full Adder using a Decoder
Binary Full Adder has 3 inputs and 2 outputs:


Inputs: two bits to be added (b1 and b0) and a carry-in (Cin) Outputs: sum (S = b0+b1+Cin) and carry-out (Cout) Logic Functions: S(Cin,b1,b0) = Σm(1,2,4,7) Cout(Cin,b1,b0) = Σm(3,5,6,7) Cin b1 b0 S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 b0 1 0 0 1 0 b1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Cin S Cout Decoder Expansions


Larger decoders can be constructed using a number of smaller ones. How? We will use composition of smaller decoders to construct larger decoders. Example:


Given: 2-to-4 decoders Required: 3-to-8 decoder Solution: Each decoder realizes half of the minterms. Enable selects which decoder is active:

A2 = 0: enable top decoder A2 = 1: enable bottom decoder 4-to-16 Decoder with 2-to-4 Decoders: Tree Composition of Decoders Binary Encoders



An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1. Enable signal (E): if E = 0 then all outputs are 0 else yj = f(x0,x1,…,x2n-1), j = 0..n-1 Valid signal (V): V = 1 if valid code is present at the outputs; otherwise V = 0. V 4-to-2 Encoder Truth Table Logic Symbol A1 A0 V 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 x x x x x x 0 4-to-2 Encoder D0 D1 D2 D3 0 1 2 3 D1D0 D3D2 00 D3 D3 D2 D1 D0 20 A0 A1 V 21 01 D1 11 10 D1D0 D3D2 00 01 D1 11 10 00 x 0 x 0 00 x 0 x 1 01 1 x x x 01 0 x x x D3 11 10 x x x x 1 x x x 11 x x x x 10 1 x x x D2 D0 D0 A1 = D3 + D2 A0 = D3 + D1 D1D0 D3D2 00 00 01 D2 D3 11 10 D1 11 10 01 1 1 1 D2 1 D0 V = D3’D2’D1’D0 + D3’D2’D1D0’ + D3’D2D1’D0’ + D3D2’D1’D0’ 4-to-2 Encoder (Logic Circuit) 4-to-2 Encoder without Enable 4-to-2 Encoder with Enable D3 D3 D2 D1 A1 = D3 + D2 A0 = D3 + D1 D0 D2 D1 D0 E A1 A1 A0 A0 V V V = D3’D2’D1’D0 + D3’D2’D1D0’ + D3’D2D1’D0’ + D3D2’D1’D0’ Priority Encoders



Solves the ambiguities mentioned earlier. Multiple asserted inputs are allowed; one has priority over all others. Separate indication of no asserted inputs. Example: 4-to-2 priority encoder 4-to-2 Priority Encoder (cont.)


The operation of the priority encoder is such that: If two or more inputs are equal to 1 at the same time, the input in the highest-numbered position will take precedence. A valid output indicator, designated by V, is set to 1 only when one or more inputs are equal to 1. V = D3 + D2 + D1 + D0 by inspection. 4-to-2 Priority Encoder (cont.) K-maps for A0 and A1 Logic Circuit: Notice that 4-to-2 Priority Encoder is simpler than 4-to-2 Encoder because the function of the V signal is simpler. Multiplexers (MUXs)



Selects binary information from one of many input lines and directs it to a single output line. Also known as the “selector” circuit, Selection is controlled by a n particular set of input lines whose # 2 Data Inputs depends on the # of the data input lines. For a 2n-to-1 multiplexer, there are 2n data input lines and n selection lines whose bit combination determines which input is selected. Enable 0 1 Data Output : 2n-1 n Select Inputs 2-to-1 Multiplexer 2-to-1 MUX Logic Symbol I0 0 I1 1 Y Truth Tables S (compact and full) 0 Y S I0 I1 Y I0 0 0 0 0 1 I1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 K-map and Equation S 2-to-1 MUX 0 With Enable I0 I1 I0I1 S Y 1 0 S1 S I0 00 01 11 10 1 1 1 1 I1 Logic Circuits 1-to-2 Decoder Y = SI1 + S’I0 E 1-to-2 Decoder 2 x 2 AND-OR Selection Circuit S Enable 2 x 2 AND-OR Selection Circuit Circuit S I0 I1 Y I0 I1 Y E 4-to-1 Multiplexer without Enable Logic Symbol 4-to-1 MUX I0 0 I1 I2 I3 1 2 3 Equation Compact Truth Tables Y S0 S1 S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3 2-to-4 Decoder 4 x 2 AND-OR Selection Circuit S1 S0 Logic Circuit I0 I1 I2 I3 Y 4-to-1 Multiplexer with Enable Logic Symbol Compact Truth Tables 4-to-1 MUX I0 0 I1 I2 I3 1 2 3 Y S0 S1 E E S1 S0 Y 1 0 0 I0 1 0 1 I1 1 1 0 I2 1 1 1 I3 0 x x 0 Logic Circuit Y = E•( S1’S0’I0 + S1’S0I1+ S1S0’I2 + S1S0I3 ) 4 x 2 AND-OR Selection Circuit 2-to-4 Decoder S1 S0 Equation Enable Circuit I0 I1 Y I2 I3 E 2n-to-1 Multiplexer 2n x 2 AND-OR Selection Circuit n-to-2n Decoder D0 S0 I0 A0 :. Sn-1 Enable Circuit :. :. :. Y An-1 D2n-1 I2n-1 E Implementing Boolean Functions using Multiplexers




Any Boolean function of n variables can be implemented using a 2n-to-1 Multiplexer. Why? A Multiplexer is basically a decoder with outputs ORed together, hence this is not surprising. The SELECT signals generate the minterms of the function. The data inputs identify which minterms are to be combined with an OR. Example: Consider function F(A,B,C) = ∑m(1,3,5,6). It has 3 variables, therefore we can implement it with 8-to-1 MUX. A BC 0 1 1 0 1 0 1 0 S2 S1 S0 7 0 6 5 4 3 8-to-1 Muliplexer Y F 2 1 Another Example
Consider function F(A,B,C,D) specified by the truth table on the right-hand side. F has 4 variables
we use 16-to-1 MUX. 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 D C B A 0 1 16-to-1 MUX 2 3 4 5 6 7 8 9 Y 10 11 12 13 14 15 S0 S1 S2 S3 F A B C D F 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 Efficient Method for Implementing Boolean Functions using Multiplexers

We have seen that implementing a function of n variables with 2n-to-1 MUX is straightforward. However, there exist more efficient method where any function of n variables can be implemented with 2n-1-to-1 MUX. Consider an arbitrary function F(X1,X2,…,Xn): n-1 line MUX with n-1 select lines.
We need a 2

Enumerate function as a truth table with consistent ordering of variables, i.e., X1,X2,…,Xn . Attach the most significant n-1 variables to the n-1 select lines, i.e., X1,X2,…,Xn-1


Examine pairs of adjacent rows. The least significant variable in each pair is Xn = 0 and Xn = 1. Determine whether the function output F for the (X1,X2,…,Xn-1,0) and (X1,X2,…,Xn-1,1) combination is (0,0), (0,1), (1,0), or (1,1). Attach 0, Xn, Xn’, or 1 to the data input corresponding to (X1,X2,…,Xn-1) respectively. Example
Again, consider function F(A,B,C) = ∑m(1,3,5,6). It has 3 variables. We can implement it using 4-to-1 MUX instead of 8-to-1 MUX. A B C F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 C 4-to-1 MUX F=C 0 1 2 3 F=C F=C F = C’ B A S0 S1 Y F Another Example
Again, consider function F(A,B,C,D) specified by the truth table below. F has 4 variables
we use 8-to-1 MUX instead of 16-to-1 MUX. Multiplexer Expansions


Larger multiplexers can be constructed using a number of smaller ones. How? We will use composition of smaller multiplexers. I0 0 Example: 4-to-1


Given: 4-to-1 multiplexers Required: 8-to-1 multiplexer Solution: Each multiplexer selects half of the data inputs. Enable signal selects which multiplexer is active:

I1 I2 I3 S0 S1 S2 S2 = 0: enable top multiplexer S2 = 1: enable bottom multiplexer 1 2 3 S0 S1 MUX Y E Y I4 I5 I6 I7 0 1 2 3 4-to-1 MUX S0 S1 E Y Multiplexer Expansions (cont.)


Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words? Combine MUX blocks in parallel with common select and enable signals Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution). 4 A(0..3) B(0..3) 4 2-to-1 4 4-line MUX S E Y(0..3) E S Y(0..3) 1 0 A(0..3) 1 1 B(0..3) 0 x 0000 Example: 2-to-1 4-line Multiplexer


Uses four 2-to-1 MUXs with common select (S) and enable (E). Select line chooses between Ai’s and Bi’s. The selected four-wire digital signal is sent to the Yi’s Enable line turns MUX on and off (E=1 is on). A0 0 B0 1 S S E A1 0 B1 1 S A2 0 B2 1 S A3 0 B3 1 S 2-to-1 MUX Y0 E 2-to-1 MUX Y1 E 2-to-1 MUX Y2 E 2-to-1 MUX E Y3 Demultiplexers (DMUXs)
Performs the inverse of a multiplexing operation:




Receives data from a single line. Transmit it to one of the 2n Data possible output lines. Input Selection of a specific output is controlled by the n select lines. Demultiplexers are basically decoders! 1-to-2n DMUX is n-to-2n decoder with enable input where the enable input is the DMUX data input (See next slide). 0 1 : 2n-1 n Select Inputs 2n Data Outputs Demultiplexers (cont.)
1-to-2n DMUX is n-to-2n Decoder with Enable input 1-to-2 DMUX 1-to-2 Decoder 0 20 enable 1 Y 1-to-4 DMUX I0 I1 2-to-4 Decoder 20 21 S Y You already know how a Decoder works. Therefore, S1 S0 you should be able to understand the DMUXs on this slide. enable 0 1 2 3 1-to-8 DMUX 3-to-8 Decoder I0 I1 I2 I3 Y 0 1 20 2 1 2 3 4 22 5 6 enable 7 S2S1S0 I0 I1 I2 I3 I4 I5 I6 I7 

Two-Variable K-map Y X Y F(X,Y) 0 0 0 F(0,0) 1 0 1 F(0,1) 2 1 0 F(1,0) 3 1 1 F(1,1)

X 0 1 Y X 0 1 1 0 0 F(0,0) F(0,1) 1 0 0 m0=X’Y’ m1=X’Y 2 3 1 F(1,0) F(1,1) 2 3 1 m2=XY’ m3=XY Cell 0 corresponds to row 0 in the truth table and represents minterm X’Y’; Cell 1 corresponds to row 1 and represents X’Y; etc. If Boolean function F(X,Y) has value 1 in a row of the truth table, i.e., a minterm is present in the function, then a 1 is placed in the corresponding cell. Two-Variable K-map -- Examples Truth Table X 0 0 1 1 Y 0 1 0 1 F1 0 0 0 1 X 0 0 1 1 Y 0 1 0 1 F2 0 0 1 1 X 0 0 1 1 Y 0 1 0 1 F3 0 1 1 0 X 0 0 1 1 Y 0 1 0 1 F4 1 1 0 1 K - map X 0 Y 0 1 X 0 1 X 0 1 X 0 1 1 1 Y 0 Canonical and Standard SOP F1 = m3 = XY (canonical) F2 = m2 + m3 = XY’ + XY =X (canonical) (standard) 1 1 1 Y 0 1 1 1 Y 0 1 1 1 1 F3 = m1 + m2 = X’Y + XY’ (canonical) F4 = m0 + m1 + m3 = X’Y’ + X’Y + XY (canonical) (standard) = X’ + Y Two-Variable K-map (cont.)
Any two adjacent cells in the map differ by ONLY one variable, which appears complemented in one cell and uncomplemented in the other.

X Examples:

2-cell area m2|m3 corresponds to term X: m2 + m3 = XY’+XY = X•(Y’+Y) = X 4-cell area m0 m1 corresponds to constant 1: m2 m3 m0 + m1 + m2 + m3 = X’Y’ + X’Y + XY’ + XY = = X’•(Y’+Y) + X•(Y’+Y) = X + X’ = 1 0 1 0 m0=X’Y’ m1=X’Y Example: m0 (=X’Y’) is adjacent to m1 (=X’Y) and m2 (=XY’) but NOT m3 (=XY) Multiple-cell areas of the map correspond to standard terms.
Y 1 m2=XY’ m3=XY Y X 0 1 0 m0=X’Y’ m1=X’Y 1 m2=XY’ m3=XY Three-Variable K-map 0 1 2 3 4 5 6 7

X Y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Z 0 1 0 1 0 1 0 1 F(X,Y,Z) F(0,0,0) F(0,0,1) F(0,1,0) F(0,1,1) F(1,0,0) F(1,0,1) F(1,1,0) F(1,1,1) Cell 0 corresponds to row 0 in the truth table and represents minterm X’Y’Z’; Cell 1 corresponds to row 1 and represents X’Y’Z; etc. If F(X,Y,Z) has value 1 in a row of the truth table, i.e., a minterm is present in the function, then a 1 is placed in the corresponding cell. YZ X Y 00 01 11 1 0 10 2 3 0 F(0,0,0) F(0,0,1) F(0,1,1) F(0,1,0) 4 7 5 6 X 1 F(1,0,0) F(1,0,1) F(1,1,1) F(1,1,0) Z YZ X 0 Y 00 01 11 1 3 10 2 0 m0=X’Y’Z’ m1=X’Y’Z m3=X’YZ m2=X’YZ’ 4 7 5 6 X 1 m4=XY’Z’ m5=XY’Z m7=XYZ m0=XYZ’ Z Three-Variable K-map -- Examples Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z F1 0 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z F2 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 1 K - map YZ X 00 0 Y 01 11 1 X1 Canonical and Standard SOP 10 1 1 1 F1 = m0 + m3 + m5 + m6 = = X’Y’Z’ + X’YZ + XY’Z + XYZ’ (canonical) Z YZ X 00 0 Y 01 1 X1 Z 11 10 1 1 1 1 F2 = m0 + m2 + m3 + m6 + m7 = = X’Y’Z’ + X’YZ’ + X’YZ + XYZ’ + XYZ (canonical) = X’Z’ + Y (standard) Three-Variable K-map (cont.) YZ X 0 Y 00 01 1 11 3 10 2 0 m0=X’Y’Z’ m1=X’Y’Z m3=X’YZ m2=X’YZ’ 4 5 7 6 X 1 m4=XY’Z’ m5=XY’Z m7=XYZ m0=XYZ’





Z Note: variable ordering is important – assume function F(X,Y,Z) then X specifies the rows in the map and YZ the columns. Each cell is adjacent to three other cells (left, right, up or down). Leftedge cells are adjacent to right-edge cells. One cell represents a minterm of 3 literals. A rectangle of 2 adjacent cells represents a product term of 2 literals. A rectangle of 4 cells represents a product term of 1 literal. A rectangle of 8 cells encompasses the entire map and produces a function that is equal to logic 1. Four-Variable K-map 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z F(W,X,Y,Z) 0 F(0,0,0,0) 1 F(0,0,0,1) 0 F(0,0,1,0) 1 F(0,0,1,1) 0 F(0,1,0,0) 1 F(0,1,0,1) 0 F(0,1,1,0) 1 F(0,1,1,1) 0 F(1,0,0,0) 1 F(1,0,0,1) 0 F(1,0,1,0) 1 F(1,0,1,1) 0 F(1,1,0,0) 1 F(1,1,0,1) 0 F(1,1,1,0) 1 F(1,1,1,1) YZ WX Y 00 01 11 10 0 3 1 2 00 m0=W’X’Y’Z’ m1=W’X’Y’Z m3=W’X’YZ m2=W’X’YZ’ 4 7 5 6 01 m4=W’XY’Z’ m5=W’XY’Z m7=W’XYZ m6=W’XYZ’ W 12 15 13 14 11 m12=WXY’Z’ m13=WXY’Z m15=WXYZ m14=WXYZ’ 8 11 9 10 10 m8=WX’Y’Z’ m9=WX’Y’Z m11=WX’YZ m10=WX’YZ’ Z

Cell 0 corresponds to row 0 in the truth table and represents minterm W’X’Y’Z’; Cell 1 corresponds to row 1 and represents W’X’Y’Z; etc. If F(W,X,Y,Z) has value 1 in a row of the truth table, i.e., a minterm is present in the function, then a 1 is placed in the corresponding cell. X Four-Variable K-map -- Examples W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 Truth Table YZ WX 00 00 Y 01 1 11 10 1 1 K - map 01 X K - map 11 1 1 1 1 10 1 1 1 1 W Canonical and Standard SOP Z F = m0 + m2 + m3 + m8 + m9 + m10 + m11 + m12 + m13 + m14 + m15 = = W’X’Y’Z’ + W’X’YZ’ + W’X’YZ + WX’Y’Z’ + WX’Y’Z + WX’YZ’ + WX’YZ + (canonical form) WXY’Z’ + WXY’Z + WXYZ’ + WXYZ = W’X’Z’ + W’X’YZ’ + W’X’YZ + WX’Y’Z’ + WX’Y’Z + WX’YZ’ + WX’YZ + (standard form) WXY’Z’ + WXY’Z + WXYZ’ + WXYZ = W’X’Z’ + X’Y + (standard form) WX’Y’Z’ + WX’Y’Z + WX’YZ’ + WX’YZ + WXY’Z’ + WXY’Z + WXYZ’ + WXYZ (standard form) = W’X’Z’ + X’Y + W Four-Variable K-map (cont.) Y YZ 00 WX 0 01 m0 1 m4 5 11 m1 3 m5 7 10 m3 2 m7 6 m2 00 W’X’Y’Z’ W’X’Y’Z W’X’YZ W’X’YZ’ 01 W 4 m6 11 W’XY’Z’ W’XY’Z W’XYZ W’XYZ’ X 12 m 13 m 15 m 14 m 10 WXY’Z’ WXY’Z WXYZ WXYZ’ 11 m 8 m 10 m 9 m 12 8 15 13 11 9 14 10 WX’Y’Z’ WX’Y’Z WX’YZ WX’YZ’ Z






Note: variable ordering is important – assume function F(W,X,Y,Z) then WX specifies the rows in the map and YZ the columns. Each cell is adjacent to four cells (left, right, up, down). Top cells are adjacent to bottom cells. Left-edge cells are adjacent to right-edge cells. One cell represents a minterm of 4 literals. A rectangle of 2 adjacent cells represents a product term of 3 literals. A rectangle of 4 cells represents a product term of 2 literals. A rectangle of 8 cells represents a product term of 1 literal. A rectangle of 16 cells produces a function that is equal to logic 1. Five-Variable K-map F(T,W,X,Y,Z) YZ T=1 WX 16 17 19 18 20 21 23 22 YZ WX 0 1 3 28 2 29 31 30 4 5 7 24 6 25 27 26 12 13 15 14 8 9 11 10 T=0
Can you draw six-variable K-map ? TWXYZ’ T’WXYZ’ Complement of a Boolean Function



The complement representation for a function F is denoted as F’ and obtained by interchanging 1’s to 0’s and 0’s to 1’s in the truth table column showing F. The complement of a function can be derived algebraically by applying the DeMorgan’s theorem. The complement of a function can be derived by taking the dual of the function equation (interchange “•”
 “+”, and “1”
 “0”), and complementing each literal. The complement of a function IS NOT THE SAME as the dual of a function. Complementation: Example Consider function F(X,Y,Z) = X’YZ + XY’Z’
Table method
X Y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
Z 0 1 0 1 0 1 0 1 F 0 0 0 1 1 0 0 0 F’ 1 1 1 0 0 1 1 1 DeMorgan method: F’ = ( X’YZ + XY’Z’ )’ -- apply DeMorgan = (X’YZ)’ • (XY’Z’)’ -- DeMorgan again = (X+Y’+Z’) • (X’+Y+Z) Dual method: F = (X’YZ) + (XY’Z’) -- interchange “•”
 “+” to find the dual of F G = (X’+Y+Z)•(X+Y’+Z’) G is the dual of F -- complement each literal to find F’ F’ = (X+Y’+Z’) • (X’+Y+Z) Boolean Functions as Equations


Truth table and K-map represent a Boolean function in a unique way. However, representing a Boolean function as Boolean equation can be done in many different ways, e.g., Canonical and Standard forms. Example:






F1(X,Y,Z) = X’•Y’•Z’ + X’•Y•Z’ + X•Y•Z’ F2(X,Y,Z) = X’•Y’•Z’ + Y•Z’ F3(X,Y,Z) = X’•Z’ + X•Y•Z’ F4(X,Y,Z) = X’•Z’ + Y•Z’ The corresponding truth tables for F1 to F4 are to the right. They are identical! Thus, F1 = F2 = F3 = F4 However, F2 and F3 are simpler than F1 and F4 is simpler than the others. X Y Z F1 F2 F3 F4 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 How do we simplify Boolean functions? Simplifying a Boolean Function


Why simplifying Boolean functions? Boolean functions are used to design digital logic circuits. Simpler Boolean function can mean cheaper, smaller, faster circuit (more details later). Three main approaches to simplify Boolean functions:


Algebraic Manipulations – using Boolean algebra as a tool for simplifications. Karnaugh Map Manipulations – very easy graphical method to simplify Boolean functions (it works for functions of up to 4 variables). Algorithmic Techniques – used to program a computer to do the simplifications. Algebraic Manipulation


We use basic identities, properties, and theorems of the Boolean Algebra to manipulate and simplify Boolean functions. Example: Simplify F = X’YZ + X’YZ’ + XZ F = X’YZ + X’YZ’ + XZ -- apply identity 14 = X’Y(Z+Z’) + XZ -- apply identity 7 = X’Y•1 + XZ -- apply identity 2 = X’Y + XZ Example: Simplify G = X’Y’Z’ + X’YZ’ + XYZ’ F = X’Y’Z’ + X’YZ’ + XYZ’ -- apply identity 5 = X’Y’Z’ + X’YZ’ + X’YZ’ + XYZ’ -- apply identity 14 = X’Z’(Y’+Y) + YZ’(X’+X) -- apply identity 7 = X’Z’•1 + YZ’•1 -- apply identity 2 = X’Z’ + YZ’ Karnaugh Map Manipulations

We can use a K-map to simplify a Boolean function of 2, 3, or 4 variables as Sum-Of-Products. Procedure:





Enter 1s in the K-map for each minterm (product term) in the function. Group adjacent K-map cells containing 1s to obtain a product with fewer variables. The number of cells in a group must be a power of 2 (2, 4, 8, …). Try to group as much as possible cells containing 1s when making a group (such group corresponds to a simpler product term). Try to make as less as possible groups to cover all cells containing 1s (this corresponds to fewer product terms in the simplified function). Do not forget to handle boundary cells for K-maps of 3 or 4 variables when you do the grouping. Important: The result after the simplification may not be unique. Simplifying a Boolean Function using 2-variable K-map (examples) Given functions: F1(X,Y) = Σm(0,1) = = X’Y’ + X’Y F2(X,Y) = Σm(0,3) = = X’Y’ + XY Y 0 X 0 1 F4(X,Y) = Σm(0,1,2,3) = = X’Y’ + X’Y + XY’ + XY 1 Simplified functions: F1(X,Y) = X’ 1 Y 0 X 0 1 1 1 F2(X,Y) = X’Y’ + XY 1 Y 0 F3(X,Y) = Σm(0,2,3) = = X’Y’ + XY’ + XY 1 1 X 0 1 1 1 1 Y 0 1 0 1 1 1 1 1 F3(X,Y) = X + Y’ F4(X,Y) = 1 Simplifying a Boolean Function using 3-variable K-map (groupings) minterm
1 m0 m1 m3 m2 0 00 m0 m4 m5 m7 m6 X 1 m4 01 m1 11 m3 10 m2 m5 m7 m6 Group of 2 adjacent cells gives product term of two literals. X’Z’ YZ 0 00 m0 01 m1 11 m3 10 m2 X 1 m4 m5 m7 m6 XZ Z Z X’Z X’Y’ Y XZ’ Y’Z
Y Y 0 00 m0 01 m1 11 m3 10 m2 X 1 m4 m5 m7 m6 XY’ X 1 m4 m5 m7 Z m6 X 1 X XY Z Group of 4 adjacent cells gives product term of one literals. Y Z Z’ X’ 00 01 11 10 00 01 0 m0 0 m0 m1 m3 m2 m1 Y’ m4 X’Y Y m5 Z 11 m3 10 m2 m7 m6 Y Simplifying a Boolean Function using 3-variable K-map (examples) Given functions: F1(X,Y,Z) = Σm(1,2,4,7) YZ X 00 0 1 X1 01 11 1 F2(X,Y,Z) = Σm(2,3,4,5) 10 Simplified functions: 1 Simplification is not possible 1 Z YZ X 00 0 X1 1 Y 01 11 Y 1 10 1 F2(X,Y,Z) = XY’ + X’Y 1 Z F3(X,Y,Z) = Σm(0,2,4,6) YZ X 00 1 0 1 X1 01 11 Y 10 1 1 F3(X,Y,Z) = Z’ Z F4(X,Y,Z) = YZ X 00 Σm(0,1,2,3,4,6,7) 0 1 X1 01 11 1 1 1 Z Y 10 1 1 F4(X,Y,Z) = X’ + Y Simplifying a Boolean Function using 3-variable K-map (more examples) Given functions: F5(X,Y,Z) = Σm(3,4,6,7) YZ X 00 0 1 X1 01 11 1 1 Z F6(X,Y,Z) = Σm(0,2,4,5,6) YZ X 00 0 1 X1 1 Y 01 11 10 1 Y F5(X,Y,Z) = XZ’ + YZ 10 1 1 1 Simplified functions: F6(X,Y,Z) = Z’ + XY’ Z F7(X,Y,Z) = Σm(1,2,3,5,7) YZ X 00 0 X1 01 11 1 1 1 1 Y 10 1 F7(X,Y,Z) = Z + X’Y Z F8(X,Y,Z) = Σm(1,3,4,5,6) YZ X 00 0 X1 1 01 11 1 1 1 Y 10 1 Z F8(X,Y,Z) = XZ’+X’Z +Y’Z or F8(X,Y,Z) = XZ’+X’Z +XY’ Not unique solution Simplifying a Boolean Function using 4-variable K-map (grouping examples)
Group of 2 adjacent cells gives product term of 3 literals. Y YZ 01 00 WX 00 m0 m1 10 m3 m2 11 m12 m13 m7 m6 X m15 m14 10 m8 m9 m11 m10 01 m4 m5 W 11
WXY X’Y’Z W Group of 8 adjacent cells gives product term of 1 literals. Z’ Y YZ 01 00 WX 00 m0 m1 11 10 m3 m2 m4 m5 m7 m6 X m m m m 12 13 11 15 14 W 10 m8 m9 m11 m10 10 m3 m2 11 m12 m13 10 m8 m9 m11 m10 X’Z’ WY Z
Group of all cells gives constant one. Y YZ 01 00 WX 00 m0 m1 W W 11 10 m3 m2 11 m12 m13 m7 m6 X m15 m14 10 m8 m9 m11 m10 01 m4 m5 01 Z 11 m7 m6 X m15 m14 01 m4 m5 W’Y’ Z
Y YZ 01 00 WX 00 m0 m1 W’X’Z’ W’YZ Group of 4 adjacent cells gives product term of 2 literals. Z 1 Simplifying a Boolean Function using 4-variable K-map (examples) YZ 00 WX 00 1 W Y 01 11 1 01 1 1 11 1 1 10 1 1 10 Given function: 1 F2(W,X,Y,Z) = = Σm(0,1,2,4,5,6,8, 9,12,13,14) 1 X 1 Z Simplified function: W 10 1 1 01 1 1 1 11 1 1 1 10 1 1 Z 1 10 1 1 1 1 1 Given function: Y 11 11 Z F2(W,X,Y,Z) = = Y’ + W’Z’ + XZ’ 01 01 11 10 Simplified function: YZ 00 F1(W,X,Y,Z) = WX = Σm(0,1,2,4,5,7,8,9,10,12,13) 00 1 Y 01 W Given function: F1(W,X,Y,Z) = = Y’ + X’Z’ + W’XZ YZ 00 WX 00 1 F3(W,X,Y,Z) = W’X’Y’ + X’YZ’ + WX’Y’ + W’XYZ’ X Simplified function: F3(W,X,Y,Z) = = X’Y’ + X’Z’ + W’YZ’ X Grouping Cells in a K-map Systematically

The procedure for combining cells in a K-map may be made more systematic if we introduce the terms: implicants, prime implicants, and essential prime implicants. An Implicant (I) of a function F is a product term which implies F, i.e., F = 1 whenever I = 1.



All minterms of a function F are implicants of F. All rectangles in a K-map made up of cells containing 1s correspond to implicants. An implicant of F is called a Prime Implicant (PI) if any product term obtained by deleting a literal of PI is NOT an implicant of F. Thus, a prime implicant is not contained in any “larger” implicant.
On a K-map of n-variable function, the set of prime implicants corresponds to the set of all rectangles made up of 2m cells containing 1s (m = 0, 1,2,…,n), with each rectangle containing as many cells as possible. Example of Prime Implicants (PIs)

Consider function F(W,X,Y,Z) whose K-map is shown at right. Product terms Z’, XY, WX’Y’ are prime implicants. Why?
Consider the term XY and obtain terms by deleting any literal:




We get two terms: term X and term Y. Both terms are NOT implicants of F. Thus, the term XY is prime implicant. Y’Z’ is not a prime implicant because it is contained in Z’. WXY is not a prime implicant because it is contained in XY. XY Z’ YZ 00 WX 00 1 01 11 10 1 1 1 1 11 1 1 1 10 1 01 W Y 1 X 1 Z Y’Z’ WX’Y’ WXY Essential Prime Implicants (EPIs)


If a minterm of a function F is included in ONLY one prime implicant pi, then pi is an Essential Prime Implicant of F. An essential prime implicant MUST appear in all possible SOP expressions of function F. To find essential prime implicants:


Generate all prime implicants of a function Select those prime implicants that contain at least one 1 that is not covered by any other prime implicant. For the previous example, the PIs are Z’, XY, and WX’Y’; all of these are essential. XY Z’ YZ 00 WX 00 1 Y 01 11 10 1 1 1 1 11 1 1 1 10 1 01 1 1 Z WX’Y’ X Essential Prime Implicants (examples)
Consider function F1(W,X,Y,Z) whose K-map is shown below:

All Prime Implicants are: XZ’, W’XY’, W’Y’Z, X’Y’Z, WX’Z, WX’Y, WYZ’ Essential Prime Implicants are: XZ’ YZ 00 WX 00 W 01 1 11 1 Y 01 11 1 1 1 X 1 1 10 10 1 1 Z
Consider function F2(W,X,Y,Z) whose K-map is shown below:

All Prime Implicants are: XZ’, W’Z, W’X Essential Prime Implicants are: XZ’ and W’Z YZ WX 00 00 W 01 1 11 1 Y 01 11 1 1 1 1 10 1 1 10 Z X Systematic Procedure for Simplifying Boolean Functions Given : The K-map of a Boolean function Obtain: The simplest SOP expression for the function 1. 2. 3. 4. Find all primary implicants (PIs) of the function. Select all essential PIs. For remaining minterms not included in the essential PIs, select a set of other PIs to cover them, with minimal overlap in the set. The resulting simplified function is the logical OR of the product terms selected above. Example



YZ 00 WX 00 1 F(W,X,Y,Z) = ∑m(0,1,2,3,4,5,7,14,15). 01 All prime implicants (PI) are: 11 W W’X’, W’Y’, W’Z, XYZ, WXY 10 Select all essential PIs: W’X’, W’Y’, WXY Select other PIs to cover all 1s with minimal overlap:


Possibilities: W’Z or XYZ We select W’Z because it is simpler. F(W,X,Y,Z) = W’X’+W’Y’+WXY+ W’Z 1 Y 01 11 10 1 1 1 1 1 1 Z 1 X Other Examples

Consider function F(W,X,Y,Z) whose K-map is shown at right. All prime implicants are: YZ

Essential prime implicants are:

WXZ, WYZ Simplified function (solution not unique):

00 WX 00 1 F = W’X’Y’Z’+WXY’+WX’Y+XY’Z + WXZ F = W’X’Y’Z’+WXY’+WX’Y+XY’Z + WYZ W 11 01 11 10 1 01 W’X’Y’Z’, WXY’, WX’Y, XY’Z Nonessential prime implicants are:

W’X’Y’Z’, WXY’, WX’Y, WXZ, WYZ, XY’Z Y 1 X 1 1 1 10 Z 1 Other Examples (cont.)

Consider function F(W,X,Y,Z) =∑m(0,1,2,4,5,10,11,13,15) whose K-map is shown at right. All prime implicants are:

Essential prime implicants are:

01 W’Y’ Nonessential prime implicants are:

W’Y’, XY’Z, WXZ, WYZ, WX’Y, W’X’Z’, X’YZ’ W’Y’, XY’Z, WXZ, WYZ, WX’Y, W’X’Z’, X’YZ’ Simplified function (solution not unique):



YZ 00 WX 00 1 F = W’Y’+WXZ+WX’Y+W’X’Z’ F = W’Y’+WXZ+WX’Y+X’YZ’ F = W’Y’+WYZ+X’YZ’+XY’Z F = W’Y’+WYZ+X’YZ’+WXZ W 11 1 Y 01 11 10 1 1 1 X 1 1 1 10 1 Z WXZ and WX’Y are NON-overlapping PIs. WYZ and X’YZ’ are NON-overlapping PIs. Product-Of-Sum (POS) Simplification



So far, we have considered simplification of a Boolean function expressed in Sum-Of-Products (SOP) form using a K-map . Sometimes the Product-Of-Sums form of a function is simpler than the SOP form. Can we use K-maps to simplify a Boolean function in Product-Of-Sums form? Procedure:

Use sum-of-products simplification on the zeros of function F in the Kmap. In this way you will get the simplified complement of F (F’). Find the complement of F’ which is F, i.e., (F’)’ = F

Recall that the complement of a Boolean function can be obtained by (1) taking the dual and (2) complementing each literal. OR, using DeMorgan’s Theorem. POS Simplification Example F = ∑m(0,1,2,3,4,5,7,14,15) YZ 00 WX 00 1 W Y 01 11 10 1 1 1 01 1 1 1 0 11 0 0 1 1 10 0 0 0 0 Z

The complement of F (F’) YZ 00 WX 00 Y 01 11 01 X W 10 1 11 1 1 10 1 1 1 1 Z Simplify using zeros: F’ = WX’ + WY’+ W’XYZ’ Complement F’ to find F, i.e., F = (F’)’

First get the dual of F’: dual(F’) = (W+X’) • (W+Y’) • (W’+X+Y+Z’) Complement each literal in dual(F’) to get F as POS F = (W’+X) • (W’+Y) • (W+X’+Y’+Z) X Don’t-Care Conditions
Sometimes a Boolean function is not specified for some variable value combinations. Why?




There may be a combination of input values which will never occur. If they do occur, the value of the function is of no concern. The function value for such combinations is called a don't-care and the combination is called don’t-care condition. The don’t-care function values are usually denoted with x. Each x may be arbitrarily assigned the value 0 or 1 in an implementation. Don’t-cares can be used to further simplify a function. Simplification using Don’t-Cares


Treat don't-cares as if they are 1s to generate prime implicants in order to produce simple expressions. Delete prime implicants that cover only don't-care minterms. Treat the covering of remaining don't care minterms as optional in the selection process (i.e. they may be, but need not be, covered). Example with Don’t-Care Conditions
Consider the following incompletely specified function F that has three don’t-care minterms d:

F(A,B,C,D) = ∑m(1,3,7,11,15) d(A,B,C,D) = ∑m(0,2,5) C CD 00 AB 00 x A 01 11 10 1 1 x 01 0 x 1 0 11 0 0 1 0 10 0 0 1 0 C CD 00 AB 00 x B A 01 11 10 1 1 x 01 0 x 1 0 11 0 0 1 0 10 0 0 1 0 D D F1 = CD + A’B’ F2 = CD + A’D B Notice: F1 and F2 are algebraically not equal. Both include the specified minterms of F, but each includes different don’t-care minterms. Other Examples with Don’t-Cares (1) C CD 00 AB 00 x
Simplify the function G(A,B,C,D) whose K-map is shown at right. A 01 11 10 1 0 0 01 1 x 0 x 11 1 x x 1 10 0 x x 0 B D G = A’C’+ AB C CD 00 AB 00 x A or 01 11 10 1 0 0 01 1 x 0 x 11 1 x x 1 10 0 x x 0 D G = A’C’+BD’ or G = BD’ + C’D C CD 00 AB 00 x B A 01 11 10 1 0 0 01 1 x 0 x 11 1 x x 1 10 0 x x 0 D C CD 00 AB 00 x B A 01 11 10 1 0 0 01 1 x 0 x 11 1 x x 1 10 0 x x 0 D B Other Examples with Don’t-Cares (2)




Simplify the function F(A,B,C,D) whose K-map is shown at the top-right. F = A’BC’+AB’+CD’+A’C’D or F = A’BD’+AB’+CD’+A’C’D The middle two terms are EPIs, while the first and last terms are selected to cover the minterms m1, m4, and m5. There’s a third solution! Can you find it? C CD 00 AB 00 0 A 01 11 10 1 0 1 01 1 1 0 1 11 0 0 x x 10 1 1 x x D CD 00 AB 00 0 A C 01 11 10 1 0 1 01 1 1 0 1 11 0 0 x x 10 1 1 x x D CD 00 AB 00 0 A B C 01 11 10 1 0 1 01 1 1 0 1 11 0 0 x x 10 1 1 x x D B B