Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

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João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins and Nuno C. C. Lourenço

Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

João P. S. Rosa

Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

Daniel J. D. Guerra

Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

Nuno C. G. Horta

Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

Ricardo M. F. Martins

Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

Nuno C. C. Lourenço

Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

ISSN 2191-530Xe-ISSN 2191-5318

SpringerBriefs in Applied Sciences and Technology

ISBN 978-3-030-35742-9e-ISBN 978-3-030-35743-6

https://doi.org/10.1007/978-3-030-35743-6

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2020

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To João, Fernanda and Filipa

João P. S. Rosa

To Carla, João and Tiago

Nuno C. G. Horta

To Martim

Ricardo M. F. Martins

To Alina, Íris and Ana

Nuno C. C. Lourenço

Preface

In the last years, the world has observed the increasing complexity of integrated circuits (ICs), strongly triggered by the proliferation of consumer electronic devices. While these ICs are mostly implemented using digital circuitry, analog and radio frequency circuits are still necessary and irreplaceable in the implementation of most interfaces and transceivers. However, unlike the digital design where an automated flow is established for most design stages, the absence of effective and established computer-aided design (CAD) tools for electronic design automation (EDA) of analog and radio frequency IC blocks poses the largest contribution to their bulky development cycles, leading to long, iterative, and error-prone designer intervention over their entire design flow. Given the economic pressure for high-quality yet cheap electronics and challenging time-to-market constraints, there is an urgent need for CAD tools that increase the analog designers’ productivity and improve the quality of resulting ICs.

The work presented in this book addresses the automatic sizing and layout of analog ICs using deep learning and artificial neural networks (ANNs). Firstly, this work explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a regression-only model and a classification and regression model. The goal of the regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The classification and regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies.

Afterward, ANNs are applied to the placement part of the layout generation process, where the position of devices is defined according to a set of topological constraints so that the minimum die area is occupied and the circuit’s performance degradation from pre-layout to post-layout is minimized. Analog IC layout placement is one of the most critical parts of the whole circuit design flow and one of the most subjective as well, as each designer has his/her own preferences and layout styles when placing devices. A model using ANNs is trained on previous placement designs, and instead of explicitly considering all the topological constraints when doing this process, the ANN learns those constraints implicitly from the patterns present in those legacy designs. The proposed model takes as input the sizing of the devices and outputs their coordinates in the circuit layout. The ANNs are trained on a dataset of an analog amplifier containing thousands of placement solutions for 12 different and conflicting layout styles/guidelines and used to output different placement alternatives, for sizing solutions outside the training set at push-button speed.

The trained ANNs were able to size circuits that extend the performance boundaries outside the train/validation set, showing that, more than a mapping for the training data, the model is actually capable of learning reusable analog IC sizing patterns. The same is valid for the placement model, which not only replicates the legacy designs’ placement, but also shows indications that it learns patterns from different templates and applies them to new circuit sizings. Ultimately, both methodologies offer the opportunity to reuse all the existent legacy sizing and layout information, generated by either circuit designers or EDA tools.

Finally, the authors would like to express their gratitude for the financial support that made this work possible. The work developed in this book was supported by FCT/MEC through national funds and when applicable co-funded by FEDER–PT2020 partnership agreement under the project UID/EEA/50008/2019.

This book is organized into five chapters.

Chapter 1 presents an introduction to the analog IC design area and discusses how the advances in machine learning can pave the way for new EDA tools.

Chapter 2 presents a study of the available tools for analog design automation. First an overview of existing works where machine learning techniques are applied to analog IC sizing is presented. Then, the three major methodologies used in the automatic layout of analog ICs are described.

Chapter 3 conducts a review of modern machine learning techniques, where the advantages and disadvantages of several machine learning methods taking into account its application to the automation of analog integrated circuit sizing and placement are discussed. Afterward, a brief overview of how the ANN learning mechanism works, the optimization techniques to speed up the convergence of the learning algorithm and the regularization techniques are presented.

Chapter 4 presents two ANN models for analog IC sizing, i.e., a regression-only model and a classification and regression model. The first serves as a proof of concept of the applicability of ANNs to analog sizing and the second that selects the most appropriate circuit topology and respective sizing for a target specification.

Chapter 5 introduces the exploratory research using ANNs to automate the placement task of analog IC layout design. The ANNs are trained on a dataset of an analog amplifier containing thousands of placement solutions for 12 different and conflicting layout styles/guidelines and used to output different placement alternatives, for sizing solutions outside the training set at push-button speed.

João P. S. Rosa

Daniel J. D. Guerra

Ricardo M. F. Martins

Nuno C. C. Lourenço

Nuno C. G. Horta

Lisbon, Portugal

Abbreviations

Adam

Adaptive Moment Estimation

AI

Artificial Intelligence

AMS

Analog and/or Mixed-Signal

ANN

Artificial Neural Network

CAD

Computer-Aided Design

CMOS

Complementary Metal-Oxide-Semiconductor

CNN

Convolutional Neural Network

EA

Error Accuracy

EDA

Electronic Design Automation

ELU

Exponential Linear Unit

EOA

Error and Overlap Accuracy

GBW

Gain–Bandwidth

IC

Integrated Circuit

IDD

Current Consumption

MAE

Mean Absolute Error

MAED

Mean Absolute Error per Device

ML

Machine Learning

MLP

Multi-Layer Perceptron

MSE

Mean Squared Error

NAG

Nesterov Accelerated Gradient

NLP

Natural Language Processing

OA

Overlap Accuracy

PM

Phase Margin

RMS

Root-Mean-Square

RNN

Recurrent Neural Network

SGD

Stochastic Gradient Descent

SoC

System-on-a-Chip

SSCE

Sparse Softmax Cross-Entropy

SVM

Support Vector Machine

Contents

1 Introduction 1

1.​1 Analog Integrated Circuit Design Automation 1

1.​2 Analog IC Design Flow 2

1.​3 Machine Learning and Analog IC Sizing and Placement 4

1.​4 Conclusions 7

References 7

2 Related Work 9

2.​1 Existing Approaches to Analog IC Sizing Automation 9

2.​1.​1 Machine Learning Applied to Sizing Automation 10

2.​2 Existing Approaches to Automatic Layout Generation 13

2.​2.​1 Layout Generation with Placement and Routing Constraints 13

2.​2.​2 Layout Migration and Retargeting 15

2.​2.​3 Layout Synthesis with Knowledge Mining 15

2.​2.​4 Analog Placement Constraints 16

2.​3 Conclusions 17

References 18

3 Overview of Artificial Neural Networks 21

3.​1 Machine Learning Overview 21

3.​1.​1 Supervised or Unsupervised Learning 22

3.​1.​2 Batch or Online Learning 24

3.​1.​3 Instance-Based or Model-Based Learning 24

3.​2 Challenges in Creating ML Systems 25

3.​3 The Five Tribes of Machine Learning 26

3.​3.​1 Why Use ANNs for EDA 29

3.​4 Neural Network Overview 30

3.​4.​1 Size of the Model 32

3.​4.​2 Activation Functions 34

3.​4.​3 How ANNs Learn 35

3.​4.​4 Optimizers 38

3.​4.​5 Early Stop, Regularization, and Dropout 40

3.​5 Summary 42

References 42

4 Using ANNs to Size Analog Integrated Circuits 45

4.​1 Design Flow 45

4.​2 Problem and Dataset Definition 46

4.​3 Regression–Only Model 48

4.​3.​1 Training 51

4.​3.​2 Using the ANN for Circuit Sizing 53

4.​4 Classification and Regression Model 53

4.​4.​1 Training 55

4.​5 Test Case–Regression–Only Model 57

4.​5.​1 Single-Stage Amplifier with Voltage Combiners 58

4.​5.​2 Two-Stage Miller Amplifier 60

4.​5.​3 Test Case—Classification and Regression Model 62

4.​6 Conclusions 65

References 66

5 ANNs as an Alternative for Automatic Analog IC Placement 67

5.​1 Layout Synthesis by Deep Learning 67

5.​2 Development of an ANN Model 68

5.​2.​1 Circuit Used for Tests 68