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[PDF] Design of High-Speed Multi-Phase Clock Corrector - S-Space

s-space.snu.ac.kr › bitstream
Aug 15, 2023 · Jeong, “A 2.5–32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR. Engine and Hybrid DFE,” IEEE Transactions on Circuits and Systems II: Express. Briefs, vol. 69 ...