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HPSm, a high performance restricted data flow architecture having minimal functionality

Authors:

W. Hwu,

Y. N. PattAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 14, Issue 2

Pages 297 - 306

https://doi.org/10.1145/17356.17391

Published: 01 May 1986 Publication History

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Abstract

Our recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data flow techniques are used to coordinate out-of-order execution of sequential instruction streams. We believe that the restricted data flow model has great potential for implementing very high performance computing engines. This paper defines a minimal functionality variant of our model, which we are calling HPSm. The instruction set, data path, timing and control of HPSm are all described. A simulator for HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. We report the measurements obtained from these benchmarks, along with the measurements obtained for the Berkeley RISC II. The results are encouraging.

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HPSm, a high performance restricted data flow architecture having minimal functionality

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 14, Issue 2

Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

May 1986

429 pages

ISSN:0163-5964

DOI:10.1145/17356

Editor:
Hideo Aiso

Issue’s Table of Contents

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture
June 1986
454 pages
ISBN:081860719X
Chairman:
Hideo Aiso

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Published in SIGARCH Volume 14, Issue 2

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Guo DLi MLyu ZKang KWu WZhong RHuang G(2021)Synchroperation in industry 4.0 manufacturingInternational Journal of Production Economics10.1016/j.ijpe.2021.108171238(108171)Online publication date: Aug-2021
https://doi.org/10.1016/j.ijpe.2021.108171
Prabakaran BDave MKriebel FRehman SShafique M(2019)Architectural-Space Exploration of Heterogeneous Reliability and Checkpointing Modes for Out-of-Order Superscalar ProcessorsIEEE Access10.1109/ACCESS.2019.29456227(145324-145339)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2945622
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https://dl.acm.org/doi/10.1145/3150376.3150380
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