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InputFinder: Reverse Engineering Closed Binaries using Hardware Performance Counters

Published: 08 December 2015 Publication History

Abstract

The effectiveness of many dynamic program analysis techniques depends heavily on the completeness of the test suite applied during the analysis process. Test suites are often composed by developers and aim at testing all of the functionality of a software system. However, test suites may not be complete, if they exist at all. To date, only two methods exist for automatically generating test input for closed binaries: fuzzing and symbolic execution. Despite previous successes of these methods in identifying bugs, both techniques have limitations. In this paper, we propose a new method for autonomously generating valid input and identifying protocols for closed x86 binaries. The method presented can be used as a standalone tool or can be combined with other techniques for improved results. To assess its effectiveness, we test InputFinder, the implementation of our method, against binaries from the DARPA Cyber Grand Challenge example set. Our evaluations show that our method is not only effective in finding input and determining whether a protocol is expected but can also find unexpected control flow paths.

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  1. InputFinder: Reverse Engineering Closed Binaries using Hardware Performance Counters

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    cover image ACM Other conferences
    PPREW-5: Proceedings of the 5th Program Protection and Reverse Engineering Workshop
    December 2015
    89 pages
    ISBN:9781450336420
    DOI:10.1145/2843859
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 08 December 2015

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    PPREW-5 Paper Acceptance Rate 8 of 12 submissions, 67%;
    Overall Acceptance Rate 21 of 36 submissions, 58%

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    View all
    • (2024)Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe)ACM Transactions on Embedded Computing Systems10.1145/366367323:4(1-27)Online publication date: 11-May-2024
    • (2024)CarePlus: A general framework for hardware performance counter based malware detection under system resource competitionComputers & Security10.1016/j.cose.2024.103884143(103884)Online publication date: Aug-2024
    • (2022)Fight Hardware with Hardware: Systemwide Detection and Mitigation of Side-channel Attacks Using Performance CountersDigital Threats: Research and Practice10.1145/35196014:1(1-24)Online publication date: 30-Apr-2022
    • (2022)Investigating Black-Box Function Recognition Using Hardware Performance CountersIEEE Transactions on Computers10.1109/TC.2022.3226302(1-14)Online publication date: 2022
    • (2019)SoK: The Challenges, Pitfalls, and Perils of Using Hardware Performance Counters for Security2019 IEEE Symposium on Security and Privacy (SP)10.1109/SP.2019.00021(20-38)Online publication date: May-2019
    • (2019)A Gray-Box Vulnerability Discovery Model Based on Path CoverageArtificial Intelligence and Security10.1007/978-3-030-24268-8_1(3-12)Online publication date: 11-Jul-2019
    • (2018)Automated Detection, Exploitation, and Elimination of Double-Fetch Bugs using Modern CPU FeaturesProceedings of the 2018 on Asia Conference on Computer and Communications Security10.1145/3196494.3196508(587-600)Online publication date: 29-May-2018

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