Automated design management using traces
An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed. The trace, represented as a bipartite directed and acyclic graph in which the nodes represent either design data or tool ...
Interaction semantics of a symbolic layout editor for parameterized modules
An interactive graphical editor for parameterized layout generators, based on symbolic layout, is discussed. One basic idea is to have built-in rules, corresponding to basic knowledge about elementary things in VLSI design, in order to make the tool ...
SALSA: a new approach to scheduling with timing constraints
An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA ...
STOIC: state assignment based on output/input functions
A finite-state-machine (FSM) synthesis procedure, specifically aimed at using primary inputs and primary output functions as state variables, is proposed. The number of next-state functions that have to be implemented is thus reduced, potentially ...
Synchronization of pipelines
A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches,...
On the circuit implementation problem
The authors consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, the basic circuit ...
Matching-based methods for high-performance clock routing
The authors point out that minimizing clock skew is important in the design of high-performance VLSI systems. A general clock routing scheme that achieves extremely small clock skews while still using a reasonable amount of wirelength is presented. The ...
Post-layout timing simulation of CMOS circuits
As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes ...
An efficient algorithm for some multirow layout problems
Three multirow layout problems are presented: transistor orientation, contact positioning and symbolic-to-shape translation. It is shown that these multirow problems have a common property, called quantitative dependency. Using this property, an ...
Area routing for analog layout
An area router specifically tailored for the layout of analog circuits is presented. It is based on the A * algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable ...
On clustering for maximal regularity extraction
The authors point out that proper usage of regularity in digital systems leads to efficient as well as economical designs. This important question of regularity extraction is examined, and a general and efficient methodology for component clustering ...
Automatic grid refinement and higher order flux discretization for diffusion modeling
The authors point out that modern numerical process simulators are becoming increasingly complicated in both physical models and domain shape. Grid generation is difficult for these simulators because of the inherently transient nature of the problems ...
Delay-fault test generation and synthesis for testability under a standard scan design methodology
The problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology are considered. Theoretical results regarding the standard scan-delay testability of finite ...
Scan-based transition test
Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan ...
Drift reliability optimization in IC design: generalized formulation and practical examples
A generalized formulation of the drift reliability optimization problem is presented. Algorithmic solutions are also proposed. They can be implemented readily in the existing circuit optimization environments and applied to integrated circuit design. ...
