Yan Xu

We encourage you to dive into the recently published paper "GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation". 📝 Authored by: Yu-Lun Hsu; Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang IEEE Open Journal of Circuits and Systems (Volume: 5) The trade-off between decoding performance and hardware costs has been a long-standing challenge in Low-Density Parity Check (LDPC) decoding. Based on model-driven methodology, the Neural Network-Aided Variable Weight Min-Sum (NN-aided vwMS) algorithm is proposed to address this dilemma in this paper. 🔗 Continue reading on IEEE Xplore here: https://loom.ly/h73OCpg #OJCAS #OA #OpenAccess #PaperHighlight

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We have the pleasure of hosting Prof. Wen Ma from UVM Physics for seminar this Thursday (10:05 am, Innovation E105)! His talk will be on the "Unveiling Atomistic Mechanisms of Large Molecular Machines through the Computational Microscope." Abstract is below:

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We are excited to announce that our soon-to-be Ph.D., Michael Canesche, has secured a position as Lead Software Engineer at Cadence Design Systems. Michael is a Ph.D. candidate at UFMG’s Compilers Lab, with his final defense scheduled for early November. During his Ph.D. studies, Michael focused on optimizing compiler parameters, tackling questions like: What’s the optimal unrolling factor for a given loop? Or how many threads should be used to parallelize that loop? His research led to Droplet Search, a kernel optimization algorithm now part of Apache TVM. Additionally, his loop fusion algorithm has been adopted by Tensilica’s XNNC compiler. Michael’s Ph.D. at Departamento de Ciência da Computação - UFMG was fully sponsored by Cadence Design Systems, and we extend our sincere thanks to Vanderson Rosario and Eric Stotzer for their support. Through their efforts, Cadence invested in fundamental research at a public and free university, contributing to the education of a highly skilled workforce. Read some of Michael's papers: The Droplet Search Algorithm for Kernel Scheduling: https://lnkd.in/dNsPwtHi Explore as a Storm, Exploit as a Raindrop: On the Benefit of Fine-Tuning Kernel Schedulers with Coordinate Descent: https://lnkd.in/dgxxfdYR A Polynomial Time Exact Solution to the Bit-Aware Register Binding Problem: https://lnkd.in/dfXctSBY #compilers #programming #machinelearning #optimization #research #academia

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We encourage you to delve into the IEEE TVLSI September 2024 paper highlight "Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads". 📝 Authored by: Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer; Jorge Tomas Gomez; Syed Shakib Sarwar; Ziyun Li; Reid Pinkham; Barbara De Salvo Volume: 32, Issue: 9, September 2024 Heterogeneous 3-D (H3D) integration not only reduces the chip form factor and fabrication cost but also allows the merging of diverse compute paradigms that suit different applications. This is especially attractive when modern algorithms, such as the augmented reality/virtual reality (AR/VR) workloads, consist of mixed machine learning (ML) and non-ML workloads. To date, codesign that considers the thermal, latency, and power constraints of H3D hardware is largely unexplored. In this work, a thermally aware framework for H3D hardware design is developed to evaluate the thermal, latency, and power trade-offs for a heterogeneous system with compute-in-memory (CIM), digital ML cores, and RISC-V cores. The framework solves for runtime tunable operating points described as the optimal speedup factor, the number of activated RISC-V cores, the cooling coefficient, and the activity rate based on user-defined criteria, achieving up to 135 TOPS and 215 TOPS/W under 74 ∘ C for the AR/VR workloads. 🔗 Continue reading on IEEE Xplore here: https://loom.ly/XRkJS1U #TVLSI #VeryLargeScaleIntegrationSystems #VeryLargeScaleIntegration

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