Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine Generation

IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735. Volume 6, Issue 5 (Jul. - Aug. 2013), PP 49-56
www.iosrjournals.org
www.iosrjournals.org 49 | Page
Implementation of Efficiency CORDIC Algorithmfor Sine &
Cosine Generation
P.Keerthi, ShaikJaffar
(M.Tech),Vlsi Design Dept Of Electronics And Communications Madina Engineering College Kadapa, Andhra
Pradesh.
M.Tech, (Ph.D.) Miste, Mie, Assoc.ProfessorDeptOf Electronics And Communications Madina Engineering
College Kadapa, Andhra Pradesh
Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm
that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high
speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations.
This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared
to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan
XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations
depending on the accuracy, area and latency requirements.
Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate
array(FPGA),most-significant-1, recursive architecture.
I. Introduction
For systems such as Calculator, keeping the size of calculator very small is of prime importance. For
these systems the cost (e.g. chip gate count has to be minimized) is more important than speed. Also it is very
important to calculate the values with good accuracy and precision. Though sometimes by increasing the bit
length we can obtain better precision, but it is more important to select a method which gives more accurate
results.
The coordinate rotation digital computer (CORDIC) has established its popularity in several
important areas of application, like generation of sine and cosine functions, calculation of discrete sinusoidal
transforms like fast Fourier transform (FFT), discrete sine/cosine transforms (DST/DCT), householder
transform (HT),etc. [1]–[3]. Manyvariations have been suggested for efficient implementation of CORDIC with
less number of iterations over the conventional CORDIC algorithm.The number of CORDIC iterations are
optimized in [4]–[6] by greedy search at the cost of additional areaand time for the implementation of variable
scale-factor. In efficient scale-factor compensationtechniques are proposed, which adversely affect the
latency/throughput of computation.
Two area-time efficient CORDIC architectures have been suggested , which involve constant scale-
factor multiplication for adequate range of convergence (RoC). The virtually scale-
free CORDIC also requires multiplication by constant scale-factor and relatively more area to achieve
respectable RoC. The enhanced scale-free CORDIC combines few conventional CORDIC iterations with
scaling-free CORDIC iterations for an efficient pipelined CORDIC implementation with improved RoC.
However, if used for recursive CORDIC architecture, combining two different types of CORDIC iterations,
degrades performance. In this paper, we propose a novel scaling-free CORDIC algorithm for area-time efficient
implementation of CORDIC with adequate RoC.
II. Brief Overview Of Cordicalgorithm
CORDIC (Coordinate Rotation Digital Computer) was introduced in 1959 by Jack E. Volder. It is very
efficient to compute the values of sin, cos, sin, tan, sinh, Cosh, tanh. It’s a Hardware Efficient Algorithm. It is
an iterative Algorithm for Circular Rotation. It requires no Multiplication. Delay/Hardware cost comparable to
division or square rooting. Compared to other approaches, CORDIC is a clear winner when:Hardware
Multiplier is unavailable (e.g. microcontroller),You wants to save the gates required to implement (e.g.
FPGA).Its basic ideas is-Embedding of elementary function evaluation as a generalized rotation operation,
Decompose rotation operation into successive basic rotations,Each basic rotation can be realized with shift and
add arithmetic operations. Shift and-add arithmetic operations. To evaluate trigonometric functions we have
many approaches suchas -1) Table lookup2) Polynomial Approximations3)CORDIC.

Implementation of Efficiency CORDIC Algorithm For Sine & Cosine Generation
A. Taylor Series
The Taylor series expansion for sine is:
sin 𝑥 = 𝑥 −
𝑥3
3!
+
𝑥5
5!
−
𝑥7
7!
+ ⋯
This method is one of the oldest and most widely, but the problem associated with this method is, to get values
of higher accuracies, higher order factorial and power has to be calculated. Moreover to implement this we
would at least require a multiplier, divider, adder and a subtractor. For good accuracy it would be required to
take each term incalculation till they become insignificant. Thus this approach has a lot of hardware
requirements as well as it is slow.
B. Look up Table
The Lookup table approach involves storing values of sine and cosine at different angles. Based on
the number of values stored, the lookup table can be big or small, but clearly, the smaller the lookup table, more
is the error involved. The problem with a bigger lookup table is that it requires more memory and memory is
expensive. Moreover the size of the Lookup table increases exponentially with the increase in the precision of
the angle. Though this approach provides fast results it is very expensive to implement.
C. Cordic Algorithm
CORDIC is an acronym for Coordinate Rotation Digital Computer introduced by Jack E. Volder. It
is an iterative algorithm capable of calculating trigonometric and various other functions. In this algorithm with
the help of an adder/subtractor, a small look up table and a shifter the trigonometric functions can be calculated
very easily. The advantage that Cordic offers over other algorithms are that it does not require multiplication or
division blocks, instead it works only with a shifter, adder/subtractor and a small lookup table. This reduces the
hardware requirement drastically and provides reasonably good speed.
Many variations have been suggested for efficient implementation of CORDIC with less number of
iterations over the conventional CORDIC algorithm [4]–[11]. The number of CORDIC iterations are optimized
in [4]–[6] by greedy search at the cost of additional area and time for the implementation of variable scale-
factor. In [7] and [8] efficient scale-factor compensation techniques are proposed, which adversely affect the
latency/throughput of computation. Two area-time efficient CORDIC architectures have been suggested in [9],
which involve constant scale-factor multiplication for adequate range of convergence (RoC). The virtually
scale-free CORDIC in [10] also requires multiplication by constant scale-factor and relatively more area to
achieve respectable RoC. The enhanced scale-free CORDIC in [11] combines few conventional CORDIC
iterations with scaling-free CORDIC iterations for an efficient pipelined CORDIC implementation with
improved RoC. However, if used for recursive CORDIC architecture, combining two different types of
CORDIC iterations, degrades performance.
The low complexity technique for eliminating the scale factor is the use of Taylor series expansion. The
Scaling-Free CORDIC and modified scale-free CORDIC are techniques based on Taylor series approach. The
former suffers from low range of convergence (RoC) which renders it unsuitable for practical applications,
while the latter extends the RoC but introduces predictable but constant scale-factor of 1/ 2. The other
hardware efficient architectures require scale-factor compensations to extend the range of convergence to the
entire coordinate space.
III. Sequential/Iterative Cordic
It requires Maximum number of Clock Cycles to calculate output,Minimum Clock Period
periteration,Variable Shifters do not map well on certain FPGA’s due to high Fan-in.

Fig:1.Variable Shifters
Parallel/Cascaded CORDIC:
It hasCombinational circuit More Delay, but processing time is reduced as compared to iterative
circuit.Shifters are of fixed shift, so they can be implemented in the wiring.Constants can be hardwired instead
of requiring storage space.
Fig.2. Parallel/Cascaded CORDIC
Coordinate Rotation Digital Computer is abbreviated as CORDIC. The key concept of CORDIC arithmetic is
based on the simple and ancient principles of two-dimensional geometry. But the iterative formulation of a
computational algorithm for its implementation was first described in 1959 by Jack E. Volder for the
computation of trigonometric functions, multiplication and division. This year therefore marks the completion
of 50 years of the CORDIC algorithm. Not only a wide variety of applications of CORDIC have emerged in the
last 50 years, but also a lot of progress has been made in the area of algorithm design and development of
architectures for high performance and low-cost hardware solutions of those applications. CORDIC-based
computing received increased attention in 1971, by varying a few simple parameters; it could be used as a
single algorithm for unified implementation of a wide range of elementary transcendental functionsinvolving
logarithms, exponentials, and square roots along with those suggested by Volder. During the same time,
Cochran benchmarked various algorithms, and showed that CORDIC technique is a better choice for scientific
calculator applications. The popularity of CORDIC was very much enhanced thereafter primarily due to
itspotential for efficient and low-cost implementation of a large class of applications which include: the
generationof trigonometric, logarithmicand transcendental elementary functions; complex number
multiplication, eigenvalue computation, matrix inversion, solution of linear systems and singular value
decomposition (SVD) for signal processing, image processing, and general scientific computation.
The name CORDIC stands for Coordinate Rotation Digital Computer. Volder [Vold59] developed the
underlying method of computing the rotation of a vector in a Cartesian coordinate system and evaluating the
length and angle of a vector. The CORDIC method was later expanded for multiplication, division, logarithm,
exponential and hyperbolic functions.

IV. Pipelined Architecture
The principle of pipelining has emerged as a major architectural attribute of most present computer
systems.Pipelining is one form of imbedding parallelism or concurrency in a computer system. It refers to a
segmentation of a computational process (say, an instruction) into several sub processes which are executed by
dedicated autonomous units (facilities, pipelining segments)
Fig.3.Pipe line architecture logical view
Parallel CORDIC can be pipelined by inserting registers between the adders stages. In most FPGA
architectures there are already registers present in each logic cell, so pipeline registers has no hardware cost.
Number of stages after which pipeline register is inserted can be modeled, considering clock frequency of
system.When operating at greater clock period power consumption in later stages reduces due to lesser
switching activity in each clock period.
V. Proposed Algorithm For Scaling Free Cordic :
The proposed design is based on the following key ideas: 1) we use Taylor series expansion of sine
and cosine functions to avoid scaling operation and 2) suggest a generalized sequence of micro-rotation to have
adequate range of convergence (RoC) based on the chosen order of approximation of the Taylor series.
A.Taylor Series Approximation of Sine and Cosine Functions
The Taylor expansions of sine and cosine of an angle “-” are given by
sin ∝= ∝ − 3! −1
∝3
+ 5! −1
∝5
− ⋯
cos ∝ = 1 − 2! −1
∝2
+ 4! −1
∝4
− ⋯
We have estimated the maximum error in the evaluation of sine and cosine functions for different order of
approximations. Therefore, we choose third order of approximation for Taylor’s expansion of sine and cosine
functions.
1) Representation of Micro-Rotations Using Taylor Series Approximation:
Here, we study the impact of orders of approximation ofTaylor series of sine and cosine functions on the
micro-rotations to beused in CORDIC coordinate calculation. Both theoretical and simulationresults are
discussed to confirm the appropriate selection of theorder of approximation. Using different orders of
approximation of sineand cosine functions in (2), we can have
𝑥𝑖+1 = 1 −
∝2
𝑖
2!
. 𝑥𝑖 − ∝𝑖−
∝3
𝑖
3!
. 𝑦𝑖
𝑦𝑖+1 = 1 −
∝2
𝑖
2!
. 𝑦𝑖 + ∝𝑖−
∝3
𝑖
3!
. 𝑥𝑖 (1a)
𝑥𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
. 𝑥𝑖 − ∝𝑖−
∝3
𝑖
3!
. 𝑦𝑖
𝑦𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
. 𝑦𝑖 + ∝𝑖−
∝3
𝑖
3!
. 𝑥𝑖(1b)
𝑥𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
. 𝑥𝑖 − ∝𝑖−
∝3
𝑖
3!
+
∝5
𝑖
5!
. 𝑦𝑖

𝑦𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
. 𝑦𝑖 + ∝𝑖−
∝3
𝑖
3!
+
∝5
𝑖
5!
. 𝑥𝑖 (1c)𝑥𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
−
∝6
𝑖
6!
. 𝑥𝑖 − ∝𝑖−
∝3
𝑖
3!
+
∝5𝑖5!.𝑦𝑖
𝑦𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
−
∝6
𝑖
6!
. 𝑦𝑖 + ∝𝑖−
∝3
𝑖
3!
+
∝5
𝑖
5!
. 𝑥𝑖(1d)
𝑥𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
−
∝6
𝑖
6!
. 𝑥𝑖 − ∝𝑖−
∝3
𝑖
3!
+
∝5
𝑖
5!
−
∝7
𝑖
7!
. 𝑦𝑖
𝑦𝑖+1 = 1 −
∝2
𝑖
2!
+
∝4
𝑖
4!
−
∝6
𝑖
6!
. 𝑦𝑖 + ∝𝑖−
∝3
𝑖
3!
+
∝5
𝑖
5!
−
∝7
𝑖
7!
. 𝑥𝑖 (1e)
We have used (1) for coordinate calculation for evaluating the best possible combination of approximation,
which satisfies the accuracy and RoC requirements, with minimum possible hardware. In Fig. 1,we have plotted
the error in magnitude estimated according to (1) (with respect to the corresponding built-in functions of
MATLAB). Since Errors resulting from the five combinations (1a)–(1e) are of very small order, we prefer to
use (1a) for coordinate calculation with minimum complexity.
2) Expressions for Micro-Rotations Using Taylor Series Approximation and Factorial Approximation:
Although, we find that we canuse Taylor series expansion with third order of approximation
(1a),with desired accuracy and RoC requirement, (1a)cannot be used inthe CORDIC shift-add iterations. To
implement (1a) by shift-add operations,we need to approximate the factorial terms by the power of 2values,
replacing 3! by 2^3 in the (1a) we find
𝑥𝑖+1
𝑦𝑖+1
=
1 − 2! −1
. ∝𝑖
2
−(∝𝑖− 2−3
∝𝑖
3
)
(∝𝑖− 2−3
∝𝑖
3
) (1 − 2! −1
. ∝𝑖
2
)
.
𝑥𝑖
𝑦𝑖
(2)
In Fig. 1 only, we have plotted the error in magnitude using the approximated factorial values and exact
factorial values after a CORDIC rotation for initial vector with coordinates X=1 and Y=1. The maximum
percentage of error in sine and cosine values for both third order of approximation and factorial approximation
is 0.0004% and 0.0168%, respectively, within the permissible CORDIC elementary angles range of 0,
7𝜋
88
discussed.
B. Determination of the Basic-Shift for a Given Order of Approximation of Taylor Series Expansion
One can find that: 1) the order of approximation of Taylor series expansion of sine and cosine
functions determines the basic-shift to be used for CORDIC iterations, and 2) the basic-shift of CORDIC
microoperation determines the range of convergence. The expressions for the basic-shifts, the first elementary
angle of rotation ∝1 and RoCfor different orders of approximations for different word-length of
implementations are as follows:
Basic shift S=
𝑏−log 2 𝑛+1 !
(𝑛+1)
(3a)
Where b is the wordlength
ROC=𝑛1. ∝1 (3b)
N is number of micro rotations
∝1= 2−𝑠
(3c)
The values in Table I are derived from (3). We find with increase in the order of approximation, the
basic-shift decreases, the first elementary angle of rotation increases and RoC is expanded. Very often inclusion
of higher order terms does not have any impact on the accuracy for smaller word-lengths. The basic-shift for
third order of approximation using (3a), for 16-bit word-length is [2.854].
TABLE I
COMPARISION OF APPROXIMATION ORDERS VERSUS ROC FOR VARIOUS BIT WIDTHS BASED
ON(7)
Order of
Approx.
Basic shift First Elementary Angle
(Radians)
RoC for 𝑛1=4
(Radians)
16-bit 32-bit 16-bit 32-bit 16-bit 32-bit
3 2 6 0.25 0.01562 1 0.0625
4 1 5 0.5 0.03125 2 0.125
5 1 3 0.5 0.125 2 0.5

TABLE II
BIT REPRESENTATION OF ELEMENTARY ANGLES AND CORRESPONDING SHIFTS
Shift
(si)
Elementary angle(𝛼𝑖)
Decimal 16-bit HexaDecimal
2 0.25 4000
3 0.125 2000
4 0.0625 1000
5 0.03125 0800
In this paper, we propose a novel scaling-free CORDIC algorithm for area-time efficient implementation of
CORDIC with adequate RoC. The proposed recursive architecture has comparable or less area complexity with
other existing scaling-free CORDIC algorithms. Moreover, no scale-factor multiplications are required for
extending the RoC to entire coordinate Space.
TABLE III
PSEUDO CODE FOR GENERATING THE MICRO-ROTATION SEQUENCE
Input: angle to be rotated 𝜃𝑖
Begin
M=Most significant-1location(𝜃𝑖)
If(M==15)then
α=0.25 radians
shift,𝑠𝑖 = 2 𝑎𝑛𝑑𝜃𝑖+1 = 𝜃𝑖 − 𝛼
else
shift,𝑠𝑖=16-M
𝜃𝑖+1 = 𝜃𝑖with𝜃𝑖[M]=’0’
END
VI. Proposed Cordic Architecture
The block diagram for the proposed CORDIC architecture is shown in Fig. below. It makes use of
the same stage for all the iterations for the coordinate calculations, as well as for the generation of shift values.
The structure of each stage (shown in Fig. 5) consists of three computing blocks namely the 1) shift-value
estimation; 2) coordinate calculation;and 3) micro-rotation sequence generator.
Fig.4. Recursive architecture of the proposed CORDIC processor.
Fig. 5. Block diagram for the stage.
The combinatorial circuit for generating the micro-rotation sequence is shown in Fig. 4. The number of
iterations required in a CORDIC processor decides the rollover count of the counter. The rollover count is seven
for basic shift =2 and ten for basic-shift =3.

Fig. 6.Combinatorial circuit for generating the shift values.
The expiry of the counter signals the completion of a CORDIC operation; depending on this signal, the
multiplexer either loads a new data-set (rotation angle,initial value of and “x”and”y”) to start a fresh CORDIC
operation, or recycles the output of the stage to begin a new iteration for the current CORDIC operation. The
input and output register files act as latches for synchronization.
Fig. 7.Micro-rotation sequence generation.
VI. Fpga Implementation
The proposed architecture is coded in Verilog and synthesized using Xilinx ISE9.2i to be
implemented in Xilinx Spartan 2E (XC2S200EPQ208- 6) device. Slice-delay-product of the proposed
architecture is compared with the existing CORDIC designs in Table IV; where, all designs are synthesized on
Xilinx Spartan 2E XC2S200E device to maintain uniformity. The power dissipation of the proposed
architecture for different clock frequencies is estimated by Xilinx XPower tool.
VII. Experimental Result And Discussion
TABLE IV
SLICE DELAY PRODUCT
Slice-delay-product of the proposed architecture is compared with the existing CORDIC designs in
TableIVis suggested to reduce the number of iterations for low latency implementation. The proposed CORDIC
processor has 17% lower slice-delay product for identifying the micro-rotations.
VIII. Conclusion
The proposed algorithm provides a scale-free solution for realizing vector-rotations using CORDIC.
The order of Taylor series approximation is decided appropriately by the proposed algorithm, not only to meet
the accuracy requirement but also to attain adequate range of convergence. The generalized micro-rotation
selection technique is suggested to reduce the number of iterations for low latency implementation. Moreover, a
high speed most-significant-1 detection scheme obviates the complex search algorithms for identifying the
micro-rotations. The proposed CORDIC processor has 17% lower slice-delay product with a penalty of about
13% increased slice consumption on Xilinx Spartan 2E device.
Logic Utilization Used Available Utilizatio
n
Number of Slices 958 5472 17%
Number of Slice Flip Flops 862 10944 7%
Number of 4 input LUTs 1749 10944 15%
Number of bonded IOBs 57 240 23%
Number of GCLKs 1 32 3%

References
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BIOGRAPHIES
P.Keerthi, received B.Tech degree in Electronics & Communication Engineering from
Madanapalle Institute of Technology and Science, Madanapalle,in 2011.Worked as
Assistant Professor in MITS for 6 months. She is now M.Tech scholarin VLSI
Design,Madina Engineering College,Kadapa,AP.
Shaik.Jaffar receivedB.Techdegree in Electronics & Communication Engineering in
1991,M.TechElectronics & Communication Engineering in 2002.He is currently doing
research in JNTUA University.He is having an experience of15years,in the field of
teaching, presently workingas Assco. Professor in the department of ECE, MadinaEngg
College,Kadapa. He is a life time memberof MIE&MISTE.

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Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine Generation