ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

Abstract

This paper demonstrates an on–off keying (OOK) super-regenerative quenching transmitter operating in 402–405 MHz MICs band applications. To reduce power consumption, the transmitter is controlled by a novel digital quenching signal controller that generates a digital control signal to start transmitter operation when a baseband signal is input to the transmitter. The digital signal controller consists of an envelope detector, a comparator, and a quench timer designed using a state machine to synchronize the operation between the digital controller and the input baseband signal. The transmitter consists of a Colpitts oscillator operating in double operating frequency followed by a frequency divider by 2; this configuration reduces system area and improves phase noise and signal spectrum. The proposed transmitter is implemented using UMC 130 nm CMOS technology and a 1.2 V supply. Simulation shows that the proposed transmitter can meet MICS band mask specifications with data rates up to 1 Mbps and total power dissipation of 537 uW.

1. Introduction

Recently, the demand for ultra-low power (ULP) transceivers for implantable devices has grown dramatically with different solutions for energy consumption reduction and optimization [1,2,3,4]. In 1999, the FCC published the medical implant communication service (MICS) around 400 MHz to provide a good compromise between device size and penetration depth into living tissue, while concerns about interferences are relaxed [5]. To further reduce the risk of interference, maximum effective isotropic radiated power (EIRP) and bandwidth are limited to −16 dBm and 3 MHz, respectively. Thereby, out-of-channel emission has to be −20 dB [6,7]. ULP typically means an average power consumption in the range of sub-mW, considering MICS applications to allow for energy harvesting operation using on-chip antennas (operates in MMwave frequency ranges such occupied area is very small compared with a complete system) [7,8]. ULP transceivers are required for implantable sensors and surgical procedures in the sub-mW supply operation for the usage of energy harvesters and wireless power transfer modules [9,10]. To achieve ULP operation, on–off keying (OOK) combined with super-regenerative reception (SRR) is often used in ULP MICS transceivers [11,12,13,14,15,16,17,18] with very low energy per bit ratios from 4.2 nJ/b down to 0.18 nJ/b [15,16]. The main operating principle is to switch off the transceiver when no data transfer occurs. In this paper, a quenched transmitter as a part of a fully regenerative OOK transceiver is designed in standard UMC 130 nm CMOS technology and can be used with an already designed low-power OOK regenerative receiver. Various works of SR technique are presented, such as the use of digital-to-analog quench controller, phase-locked loop frequency synthesis, and low-efficiency envelope detectors [19], which increases power consumption and circuits’ complexity. A novel digital quenching signal controller is proposed to control the operation periods of the transmitter, which enables the oscillator—the main block in the proposed transmitter—to switch on only during data transfer and switch off during idle operation. The proposed controller consists of a state machine that determines the oscillation period start-up and controls a quenching timer. The state machine is controlled using a comparator digital signal derived from an envelope detector for the transmitted signal. The paper is organized as follows. Section 2 describes a block diagram of the complete system. Section 3 demonstrates the quenched transmitter building blocks and their simulation results. The design concept of the proposed quenching signal controller and the state machine is in Section 4. Complete system simulation results are reported in Section 5. Finally, a conclusion is drawn in Section 6.

2. Proposed Regenerative Transmitter Block Diagram

The block diagram of the quenched transmitter is shown in Figure 1. It contains an oscillator turned on and off by enabling and disabling its bias current Ibias. This is controlled by multiplying the output signal enBias from a quench generator with that of the OOK input sBB in the digital domain. Then, the result is converted into the bias current. Hence, if enabled by the quench control, the bias current is only available during a high state of the baseband signal. As the bias current is activated, an oscillating output voltage rises up. The oscillator outputs a signal at around 800 MHz, which is fed through a buffer followed by a dynamic frequency divider that creates the desired frequency of about 400 MHz. To control the quenching signal, the oscillator’s output runs through an envelope detector first. By comparing its output to a reference signal Iref, a started oscillation is indicated. Based on this ‘detection signal’ output from the comparator, combined with a signal from a quench timer, a state machine decides whether the bias current is enabled. This ensures synchronization between quenching and the input bit pattern. Furthermore, the state machine enables the divider operation, once the oscillator has settled. Working at twice the frequency offers usage of integrated inductors having nearly twice the quality factor and smaller area within this frequency range, which results in reduced power dissipation. Furthermore, it isolates the oscillator from a power amplifier (PA), thus suppressing the effect of injection pulling [19]. A power amplifier is not included in this work, but is considered as a load. In the following sections, the implementation of the signal path architecture is presented first. Afterwards, the building of the feedback path generating the quenching signal is worked through.

3. Signal Path Circuit Design

The signal path block consists of three parts, a bias current control circuit, a Colpitts oscillator followed by a NAND buffer, and a master–slave true single-phase clock (TSPC) frequency divider. In this section, the circuit diagram for each block is explained.

3.1. Bias Current Control

The bias current control shown in Figure 2a provides the bias current Ibias for the quenched oscillator. The bias current is fed to the oscillator only if enabled by two control signals applied to an AND gate. One signal is provided from a state machine enBias, and another from the digital baseband signal sBB. The working principle is shown with simulated waveforms in Figure 2b. If both inputs are driven to a high state, a reference current is allowed to be mirrored up as the oscillator’s bias. Otherwise, no current is applied to the oscillator.

3.2. Oscillator

To generate the local oscillator signal, the Colpitts oscillator in the common gate configuration shown in Figure 3 is used. It provides large output voltage swings with good phase noise performance. Quenching is made possible by a controlled bias current. By setting Ibias below the required for starting an oscillation, the oscillator is quenched. The design considerations for starting the Colpitts oscillator are given by [20]

$$g_m{R}_p\ge \frac{{\left(C_{top}+C_{bot}\right)}^2}{C_{top}.C_{bot}}$$

(1)

As the quality factor QL of integrated inductors is small, Rp is dominated by the inductor, as R_p ≈ Lω0QL [20]. For ω₀ = 2τ *400 Mrads⁻¹ an inductance of 22 nH with Q_L ≈ 5 is provided—by the UMC130 nm CMOS technology—yielding R_p ≈ 276 Ω. By doubling ω0 to 2τ *800 Mrads⁻¹, an inductance of 2 × 11 nH is used with QL is increased. As a result, R_p reaches roughly 1k. Thus, the required gm and Ibias for a set swing are reduced. The simulated waveform is shown in Figure 4.

3.3. Frequency Divider

The frequency divider is necessary to obtain the desired carrier frequency of about 400 MHz from the local oscillator, which operates at 800 MHz. A TSCP divider architecture shown in Figure 5 exploits the master–slave configuration presented in [21]. The master–slave architecture prevents glitches, which would occur at the output for the traditional flip-flop. To prevent driving the switches of the divider by the oscillator, a CMOS NAND gate serves as a driver. One input comes from the oscillator, the other from a digital logic. A NAND logic is necessary to fully shut off the driver. Otherwise, in absentia of an AC signal, the DC voltage from the oscillator (of 0.75 V) would cause the driver to consume static power. The simulated waveform of the divider for an ideal input oscillation is presented in Figure 6a. Once the divider is activated, the task of dividing the input frequency by two is completed even for an input amplitude of 12% below the nominal value achieved by the Colpitts oscillator. The simulated spectral characteristics, if combined with the designed oscillator, are given in Figure 6b, with the input frequency at 800 MHz sufficiently suppressed by −30 dB and frequency spurs well below −80 dB relative to the carrier of 400 MHz. To provide a measure of the power consumption, the individual stages of the divider are regarded as inverters driven at 400 MHz. Additionally, the switches driven by the NAND gate at 800 MHz are considered. The average dynamic power consumption of a digital inverter is calculated by

$$P_{avg}=V_{DD}^2{C}_{load}f$$

(2)

Assuming a capacitive load of 100 fF, power consumption of 85 μW for driving the switches and, respectively, 123 μW for the divider stages is estimated, which in total is about 0.2 mW.

4. Quenching Signal Controller

The quenching signal controller deals with generating the quenching signal input to the oscillator, as shown in Figure 1. Since the quenching is controlled with digital signals, the analog output of the oscillator is transformed into the digital domain. In order to obtain this, an envelope detector followed by a comparator is used. These two circuits indicate a started or quenched oscillation, by generating a detection signal. Depending on their output, a state machine starts the quenching period or not. For a defined quench cycle, a quench timer is used, which is part of the feedback for the state machine.

4.1. Envelope Detector

The envelope detector (ED) establishes the first part by means of generating an oscillation ‘detection signal’. As indicated by its name, this device outputs a signal depending on the envelope curve of the input signal, while the high-frequency oscillation is removed. Hence, the following stages have to process low-frequency signals only, thereby reducing their power consumption. The schematic of the implemented ED is presented in Figure 7. It contains an input transistor biased as a diode and a filter capacitor. The diode only lets through positive voltages relative to the input common-mode voltage (0.75 V) and suppresses the negative ones. So, it works as a half-wave rectifier. The rectified input voltage causes a current successively charging the filter capacitor C_f. Since the charging process is faster than the discharging by the bias circuit, the output voltage Venv rises. So, it performs similar to a first-order sample-and-hold which is similar to a first-order low-pass filter. Considering the suggested design, the filter pole frequency P is at [22]:

$$P\approx \frac{g{m}_{diode}}{C_f}$$

(3)

With gmdiode = 130 μS. C_f of 0.5 pF the pole frequency is 260 MHz. With an input frequency—from the oscillator—of 800 MHz below the filter frequency, a first-order low-pass input signal is suppressed. Since the fundamental of a halfwave rectified sinusoidally is only half of its amplitude, another −6 dB is obtained in a steady state. Figure 8 shows the simulation of the ED, with a charging time of 2.9 ns, discharging time 23 ns, and voltage ripples of 10 mV. The delay caused by the discharge time of 23 ns is not very critical, because the oscillator requires about 100 ns for the start-up.

4.2. Comparator

The comparator is used to transform the output voltage of the envelope detector into a usable voltage for the digital control logic. Because the signal levels of the envelope detector are too low to sufficiently drive conventional comparators, the architecture shown in Figure 9a is used. Here the output voltage of the envelope detector Venv is converted to a current, which is mirrored and compared to a reference current. If the resulting current is higher than the reference, the output is driven low; otherwise, the output remains at a high state. Since currents are compared, it is called a current comparator; however, to somehow obtain a logical meaning, an inverter follows the output. Hence, an increased voltage of the envelope detector results in a high state at the output. Moreover, the output is more ’hard switched’, giving a more defined logic state. To ensure the detection of a started oscillation, the switching point is chosen at the minimum value provided by the envelope detector; a detection point is compromised to 0.45 V. The DC characteristic of the comparator is presented in Figure 9b.

The transient behavior of the current comparator, while connected to the envelope detector, is shown in Figure 10. It can be seen that the decision point is shifted in the time domain due to some delay introduced by parasitic capacitances. Further, the dead time is extended from 23 ns (Figure 8) to 35ns, but is still not critical. Performing a Monte Carlo simulation for 200 runs with envelope detector and comparator connected results in 100% detected oscillations, but 7 out of 200 are false detections, which gives a 96.5% yield. Hence, the minimum DC level seems to be more critical. To solve this problem, the nominal detection point is adjusted to a higher value of 0.55 V. The simulated static power consumption is 11 μW if no oscillation is detected (output low) and, respectively, 26μW in case of a detected oscillation (output high).

4.3. Quench Timer

The quench timer determines the duration of the quench period as well as the on-time of the oscillator but becomes only active if an oscillation is detected and is controlled by the state machine. Thus, the quench timer outputs two states. First, the timer is in the quench period, and second, the timer is in the sample or ’allow oscillation’ mode. In turn, the current state is fed back to the state machine, which decides whether the timer is reset, or its state is changed. To generate these two periods, the circuit shown in Figure 11a is used. A current source charges or discharges a capacitor depending on the state of the input signal enQctrl. If enQctrl is low, the capacitor is charged and discharged otherwise. The charging is sensed by a subsequent Schmitt-Trigger; as long as the capacitor voltage is above a lower threshold, the output of the Schmitt-Trigger enTimer is low. Once the lower threshold is hit, the output switches to high and vice versa for an upper threshold voltage. Whether the capacitor is charged or discharged depends on the output signal, which is processed by the state machine giving the input signal enQctrl; hence, the quench timer operates in feedback—basically, discharging occurs during sampling mode and charging during the quench period. To provide the same initial conditions for each cycle of sampling and quenching, a timer reset is available, which is controlled by the state machine, too. Moreover, the timer reset is enabled if nothing is available to do. Thus, the quench timer is waiting in sampling mode with the output enTimer at low. To determine the duration of the sample and quench period, the system’s delay times have to be considered. These are about 125 ns from the switched bias control (Figure 2b), 100 ns until the oscillator builds up a detectable oscillation (Figure 4), and 35 ns from the dead time of the envelope detector combined with the comparator (Figure 10a). Adding up these values results in 260 ns, which represents the nominal time of the system during the oscillator is indicated as quenched. Since sample and quench time need to be equal to obtain a clean spectrum, the minimum time for oscillation would be 260 ns as well; however, this would mean the quench timer does not need a quench or charge period. Hence, the timer cycle is doubled to about 1 µs or in means of frequency 1 MHz, which also is the maximum pulse rate needed to be detected on the receiver side. Thus, the quench period is a third of the entire timer cycle. To realize this, the capacitor is preloaded to 1.2 V at the beginning of a cycle. Further, the threshold voltages are set to 0.9 V and 0.3 V. Well, to change the output from low to high, the capacitor needs to be discharged from 1.2 V to 0.3 V. To switch back the output, charging from 0.3 V to 0.9V has to be achieved. By defining the charging current, as a quarter less the discharging current, the quench period (charging) needs one-third of a cycle now. The mismatch in currents is achieved by using properly designed current mirrors within the switched current source. The idea is verified by simulation, as shown in Figure 11b.

4.4. State Machine

To achieve synchronization between the start of quenching and an incoming high bit, a state machine is used. This is realized by delay elements [23] that activate the quench timer as soon as a high state is detected. Moreover, the state machine ensures divider start-up only once the oscillator has settled. This prevents the self-oscillation of the dynamic divider due to the common-mode voltage of the oscillator. The idea of the synchronized quenching is shown in Figure 12. The quenching is divided into three stages. In the first phase, the state machine lies in wait for an incoming input denoted by ‘Listen’. Once an input is detected, it passes over to the ‘Sample’ phase. This state is held until the quench timer reaches its upper limit. Hereafter, the ‘Quench’ phase begins and is kept until the quench timer hits its lower limit. Then it goes back to ‘Listen’ state to check if an input is still available and if true, the cycle starts again. Circuit implementation of the system state machine is not considered in this work. During Listen and Sample states, the output signal for bias control enBias is set to high, which, multiplied by the input signal sBB, lets the signal activate the oscillator’s bias current Ibias. The state diagram is illustrated in Figure 13. The inputs T and O consider the quench timer output and the ’oscillation detected’ signal, respectively. The outputs B, D, Q, and C denote the states for enBias, enDivider, enQctrl, and enQclr, as presented in Figure 1, respectively. Thereby, enQctrl and enQclr stand for ’activate quench timer’ and ’clear quench timer’, respectively.

The results for the outputs are calculated as follows:

$$\begin{array}{l}B=enBias=\overline{\overline{Z_oɅ\overline{TɅ\overline{Z_1}Ʌ\overline{O}}}Ʌ\overline{\overline{Z_o}Ʌ\overline{Z_1}}}\\ D=enDiv=\overline{\overline{TɅO}}Ʌ\overline{Z_1Ʌ\overline{Z_o}}\\ Q=enQctrl=TɅ\overline{\overline{O}Ʌ\overline{Z_o}}Ʌ\overline{Z_1Ʌ\overline{Z_oɅO}}\\ C=enQdr=Z_1Ʌ\overline{TɅ\overline{Z_o}}Ʌ\overline{Z_oɅO}\end{array}$$

(4)

with the combinatorics of the states Z (the three phases Listen, Sample, Quench) yield to:

$$\begin{array}{l}{Z}_{0,+1}=\overline{\left(TɅ\overline{\overline{O}Ʌ\overline{Z_1Ʌ\overline{Z_o}}}\right)}Ʌ\overline{\left(\overline{O}Ʌ\overline{\overline{Z_oɅ\overline{Z_1}}}Ʌ\overline{\overline{\overline{T}Ʌ\overline{Z_1}}}\right)}\\ Z_{1,+1}=\overline{\overline{T}Ʌ\overline{Z_1Ʌ\overline{OɅZ_o}}}\end{array}$$

(5)

The block diagram of the state machine is shown in Figure 14. For simplicity of implementation, its combinatorics and delay elements are implemented by minimum-sized static CMOS NAND and NOT gates only. Moreover, CMOS gates provide the advantage of ideally dissipating no static power; however, the number of gates is set in

Table 1. Number of gates for state machine.

Gate	State Logic	Output Logic	Inputs	Delay
NAND	11	15	0	0
NOT	1	4	4	12

. The number of delay elements is chosen so that a change in the state takes twice the time of the critical path within the output logic, while symmetry is respected for state paths. The remaining fourth state Error indicates a timing mismatch, as described in Figure 15, which can happen if the quench cycle does not fit in multiples of the bit time. A simulated timing diagram for a random input pattern at 1 Mbps is shown in Figure 15. Once the input is switched to high, the state machine starts the quench cycle, which means enQctrl is set high and goes to the sample state afterward by setting Z1 to low. As long as the input is kept at high, the alternates between sample Quench and Listen state, while the quench timer is reset by enable enQclr after each cycle. The Listen state is not visible because of its short duration. Further, the bias of the oscillator enBias, as well as the divider enDivider, are disabled in the Quench state (Z1 = high, Z0 = low). The Quench timer is driven into charge period with enQctrl = low during quench state, too. When the input osc detected changes back to low, the state machine returns to Listen mode and waits for the next input, which will cause the cycling to start again. Note that the divider is only enabled in sample mode (Z1 = low, Z0 = high) here. Hence, an output signal is available only during the sample mode as well. An average and root mean square (rms) power of the state machine of 60 μW and 210 μW, respectively, are simulated for the given input signal.

5. System Performance

Figure 16 shows system performance for random input data at 1 Mbps to the proposed transmitter with quench frequency 1 MHz, and the oscillator output signal and envelop detector/comparator signals are shown. The frequency spectrum is shown in Figure 17 with the desired carrier at 0.4 GHz–30 dB, but the oscillator signal (800 MHz) leaks to the output at 27 dB below the carrier power. Hence, the bandwidth limit considering MICS spectral is dominated by the quench frequency. To meet MICS band, pulse shaping is required to meet the MICS band requirements and can be obtained by RF matching circuits or pulse shaping filters. Complete transmitter specifications are shown in

Table 2. Simulation results of the entire quench transmitter.

Parameter	Carrier Freq. ( MHz)	Tuning Range ( MHz)	Max. input Data Rate (Mbps)	Max./Min Quench freq.( MHz)	Carrier PSD (dB/Hz)	Carrier 3rd Harm. (dB)	Oscill. Isolation (dB)	1 MHz Prms (µW)
Sim. result	402–405	±1	2	1/0.19	−30	−10	−27	537

.

Table 3. Transmitter performance summary and comparison with other OOK super regenerative transmitters.

Parameter	[17]	[18]	[24]	[27]	[28]	[29]	[30]	This Work
Freq. (MHz)	402–405	400	402–405	13.56	2400	401–406	433	402–405
Technology	130 nm	130 nm	90 nm	65 nm	90 nm	180 nm	180 nm	130 nm
Data rate	54 Mbps	200 Kbps	1 Mbps	100 Kbps	100 Kbps	1 Mbps	NA	2 Mbps
Supply Voltage (V)	1.2	1	0.6–1	0.8		1.8	1.8	1.2
Energy/bit	1.2 nJ	0.45 nJ	0.16 nJ	0.425 nJ		23 nJ	NA	0.27 nJ
Power dissipation	68.2 mW	90 µW	160 µ[email protected]	42.5 µW	2.53 mW	23 mW	580 µW	537 µW

shows a comparison between this work and previously published OOK and super-regenerative transmitters. The proposed transmitter has a high data rate and low energy/bit compared with other architectures except for [24]; this can be considered due to the use of 130 nm technology. As scaling down CMOS technology reduces total power consumption and increases the cutoff frequency, which leads to higher data rate [25,26], applying the proposed technique using a more recent technology (as 65nm or less) will lead to better improvements in power consumption and data rate. This shows the simplicity of complete transmitter design with ULP dissipation.

6. Conclusions

In this paper, an ultra-low power high/data rate quenched transmitter for OOK super-regenerative biomedical applications is designed. A transmitter consists of a bias current control block, a Colpitts oscillator, and a frequency divider, all used to generate the oscillation signal. A novel digital quenching signal generator is proposed to control the quenched oscillator operation. The digital control is obtained using an envelope detector that converts the oscillator’s high frequency to a low-frequency signal, and input to a comparator to be converted into a digital detection signal indicates the switching of the oscillator. The detection signal is input to the state machine to control the transmitter operation. The complete proposed transmitter is implemented using UMC 130 nm CMOS technology 1.2 V. The frequency spectrum of the proposed system is simulated to check its ability to meet FCC regulations, and the harmonics PSD can be improved using a pulse shaping filter. The proposed transmitter has high data rates and low power dissipation compared with other architectures (up to 2 Mbps) and consumes 537 µW.