An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules

Abstract

A multi-level 2D Discrete wavelet transform (DWT) architecture for JPEG2000 is proposed, enhancing speed through parallel processing multiple tile blocks. Based on the lifting scheme, folded architecture and unfolded architecture achieving critical path delay with only one multiplier are designed to increase throughput rate. Connecting the folded and unfolded architecture through a pipeline architecture ensures uniform throughput rates across all DWT levels within a singular clock domain. Computational resource consumption is reduced by adjusting the timing to allow one folded architecture to process three tile blocks of three to five levels of DWT, and a transposing module requiring merely six registers is devised to decrease storage resource consumption. The quantization module, crucial for code-word control in JPEG2000, is integrated into the scaling module with minimal additional resource expenditure. Compared to the existing architecture, the analysis demonstrates that the proposed architecture exhibits enhanced hardware efficiency, with a reduction in transistor-delay-product (TDP) of no less than 14.69%. Synthesis results further reveal an area reduction of at least 26.64%, and a decrease in area-delay-product (ADP) by a minimum of 29.89%. Results from FPGA implementation indicate a significant decrease in resource utilization.

1. Introduction

JPEG2000 stands as a highly effective image compression standard [1], extensively utilized in the realms of medical and satellite imagery. The fundamental enhancement in JPEG2000 is the substitution of the discrete cosine transform (DCT) with the discrete wavelet transform (DWT), as it demonstrates an improvement in coding efficiency and image quality [2]. DWT is a multiresolution analysis tool adept at decomposing a signal into distinct subbands with both time and frequency information [3], which finds extensive application across image processing and image encryption domains [4,5,6]. The performance of 9/7 DWT hardware depends on the precision and efficiency of the quantization filters. Higher precision ensures compression quality close to unquantized data but requires more hardware and processing time [7].

In JPEG2000, images are typically segmented into smaller tile blocks with a typical size of $128\times 128$. Subsequently, these tiles undergo compression using a five-level two-dimensional (2D) DWT to achieve optimal compression efficacy [8]. However, to meet real-time computation demands, contemporary multi-level 2D DWT architectures face challenges with heightened computational complexity and increased memory resource requirements [9]. Consequently, researching and developing a more efficient VLSI architecture for multi-level DWT is essential.

In recent years, DWT architectures have been categorized into the convolution-based scheme [9,10,11] and lifting-based scheme [12,13,14,15,16,17]. The lifting-based architecture is favored over its convolution-based counterpart due to its reduced computational complexity, narrower internal bit widths, and diminished memory requirements [18,19]. In the domain of single-level DWT, George [10] introduced architectures termed horizontal-FrWF and vertical-FrWF based on a convolutional framework. These architectures eliminate the dependency of FrWF computation’s memory requirements on image resolution, effectively reducing both area and memory needs. Naseer [12] employed a lifting-based architecture with a CSD-DA structure to decrease the complexity of multiplication operations, enhancing the clock frequency. Mohamed [17] achieved a significant reduction in resource utilization and obtained a higher PSNR through hardware–software codesign with partial reconfiguration. However, the resource demands of single-level architectures increase exponentially with the number of levels when processing multi-level DWT, significantly reducing encoding efficiency.

Multi-level DWT architecture has also been extensively researched. Mohanty [20] proposed a line-based parallel lifting modular and pipelined architecture, effectively obviating the requirement for lines and frame memories. However, this design results in a critical path delay (CPD) of $Tm+2Ta$, where $Ta$ represents the delay of an adder and $Tm$ signifies the delay associated with a multiplier. Wu [21] utilized a CSD multiplier to lower the critical path delay to $Ta$, though it complicates the internal structure and control signals. Zhang [22] developed a parallel architecture integrating first-stage unfolding and internal semi-folding, combined with folding, to achieve synchronization with the rate and high throughput requirements of three-level DWT. However, this architecture lacks flexibility in modifying parallelism and DWT levels. Furthermore, when managing multi-level DWT with a high number of levels, Refs. [21] and [22] both encountered the issue of multiple clock domains. This results in a structure that fails to reach optimal efficiency, consequently consuming additional clock cycles. Hu [23] proposed a scanning method based on overlapping stripes and developed a scalable pipelined multilevel DWT architecture, which eliminates the need for frame memory, yet the seven-pixel overlap in scans significantly increases the required input RAM size.

Quantization modules have been thoroughly examined, with a primary focus on minimizing the loss of image quality during the quantization process. Kotteri [7] explored a two-stage cascading quantization structure that enhances filter performance by compensating quantization coefficients. Chaker [24] employed preprocessing steps to extract image features, enabling uniform scalar quantization that reduces loss in image compression quality. Moreno [25] introduced alternative estimations and normalizes quantization coefficients to improve the quality of image encoding. However, the studies in [7,24,25] faced the challenge of increased hardware resource consumption to improve quality. Furthermore, the quantization module functions as a separate component, leading to additional clock cycles and further hardware overhead.

In this article, an efficient multi-level 2D DWT architecture using a lifting scheme capable of processing multiple tile blocks concurrently is proposed, with the quantization module integrated into the scaling module with minimal additional resource consumption. The proposed architecture synchronizes throughput within a single clock domain through the integration of both folded and unfolded architectures which reduce CPD to $Tm$. In the architecture, level 1 employs a three-way parallel unfolded architecture, whereas level 2 utilizes a three-way parallel folded architecture. For level 3 to 5, only one folded architecture is implemented to compute three-way parallel DWT, diminishing the consumption of computational resources, and a simplified control module is designed to minimize system complexity. The quantization module is integrated with the scaling module by adding only a few selectors, effectively avoiding additional hardware resource consumption and clock cycle overhead. Additionally, a novel transposing module requiring merely six registers is introduced to minimize the requirements of the transposing buffer. Consequently, this approach markedly enhances hardware efficiency.

The rest of this article is organized as follows. Section 2 explains the lifting algorithm, DWT process, and the integration of the quantization formula. Section 3 introduces the proposed multi-level 2D DWT architecture. Section 4 discusses implementation results and comparisons. Conclusions and a discussion are in Section 5.

2. Refinements to DWT and Quantization Formulas

2.1. Algorithm of Lifting-Based 2D DWT

In the implementation of the 2D DWT column and row filters, an identical lifting scheme corresponding to the 9/7 filter in a dual application is employed, encompassing two distinct lifting steps and one scaling step. To enhance the critical path delay and avoid additional registers, Huang [26] introduced an innovative formula tailored for the flipping scheme, delineated as follows:

$${\displaystyle \frac{1}{\alpha }}y(2n+1)={\displaystyle \frac{1}{\alpha }}x(2n+1)+x\left(2n\right)+x(2n+2)$$

(1)

$${\displaystyle \frac{1}{\alpha \beta }}y\left(2n\right)={\displaystyle \frac{1}{\alpha \beta }}x\left(2n\right)+{\displaystyle \frac{1}{\alpha }}y(2n-1)+{\displaystyle \frac{1}{\alpha }}y(2n+1)$$

(2)

$${\displaystyle \frac{1}{\alpha \beta \gamma }}H(2n+1)={\displaystyle \frac{1}{\alpha \beta \gamma }}y(2n+1)+{\displaystyle \frac{1}{\alpha \beta }}y\left(2n\right)+{\displaystyle \frac{1}{\alpha \beta }}y(2n+2)$$

(3)

$${\displaystyle \frac{1}{\alpha \beta \gamma \delta }}L\left(2n\right)={\displaystyle \frac{1}{\alpha \beta \gamma \delta }}y\left(2n\right)+{\displaystyle \frac{1}{\alpha \beta \gamma }}H(2n-1)+{\displaystyle \frac{1}{\alpha \beta \gamma }}H(2n+1)$$

(4)

$$S_H(2n+1)=\alpha \beta \gamma K{\displaystyle \frac{1}{\alpha \beta \gamma }}H(2n+1)$$

(5)

$$S_L\left(2n\right)={\displaystyle \frac{\alpha \beta \gamma \delta }{K}}{\displaystyle \frac{1}{\alpha \beta \gamma \delta }}L\left(2n\right)$$

(6)

where $\alpha$, $\beta$, $\gamma$, $\delta$ are the lifting coefficients, where $\alpha =-1.586134342$, $\beta =-0.052980118$, $\gamma =0.882911075$, and $\delta =0.443506852$, K is the scaling coefficient, where $K=1.230174105$, and the variable $x\left(n\right)$ represents the pixel value of the input image, with $x(2n+1)$ and $x\left(2n\right)$ corresponding to the odd and even indexed inputs, respectively. The intermediate variables of the lifting process are represented by $y\left(n\right)$, $H(2n+1)$, and $L\left(2n\right)$. The culmination of the lifting process yields $S_H(2n+1)$ and $S_L\left(2n\right)$, which are the high-frequency and low-frequency components outputted by the 9/7 wavelet transform, respectively.

The execution of the 2D DWT necessitates an initial column transformation succeeded by a subsequent row transformation, thereby requiring a pair of sequential applications of the flipping operation. Within the second iteration, the high-frequency component $H(2n+1)$ and the low-frequency component $L\left(2n\right)$, derived from the initial calculation, serve as distinct inputs. Specifically, the high-frequency output from $H(2n+1)$ constitutes the high-high ($HH$) component, whereas its low-frequency counterpart results in the high-low ($HL$) component. Similarly, the high-frequency output from $L\left(2n\right)$ forms the low-high ($LH$) component and the corresponding low-frequency output generates the low-low ($LL$) component.

In 2D DWT, the $LL$ component contains the majority of the signal’s energy and information, and the multi-level DWT methodology involves employing this $LL$ component from a given level as the input data $x\left(n\right)$ for the ensuing level’s analysis. By iteratively applying the 2D DWT, one acquires the sophisticated subband components $HH$, $HL$, $LH$, and $LL$ at higher hierarchical levels. Figure 1 elucidates the principle of the 2D DWT and simultaneously depicts the decomposition process via an exemplification of a two-level DWT.

2.2. Integration of Quantization and Scaling Formulas

Quantization is a crucial aspect of bit-rate control in JPEG2000, where it compresses wavelet coefficients further to eliminate redundancy in image details imperceptible to the human eye. The JPEG2000 standard specifies a method of dead-zone scalar quantization [27], as demonstrated in Equation (7). This method relies on subband information derived from wavelet transformations to determine the quantization step sizes appropriate for different subbands:

$$q=sign\left(x\right)\lfloor \left|x\right|/\Delta \rfloor$$

(7)

where q is the quantization result, x represents the components of each level of subbands processed by DWT, $\lfloor \rfloor$ represents rounding down to the nearest integer, $\Delta$ denotes the quantization step size for the subbands, and $sign\left(x\right)$ indicates the sign of x.

$$q=h\times S\left(n\right)$$

(8)

$$q\left(HH\right)=h_{HH}^{\ast }\times {\displaystyle \frac{1}{\alpha \beta \gamma }}HH(2n+1)$$

(9)

$$q\left(LH\right)=h_{LH}^{\ast }\times {\displaystyle \frac{1}{\alpha \beta \gamma }}LH(2n+1)$$

(10)

$$q\left(HL\right)=h_{HL}^{\ast }\times {\displaystyle \frac{1}{\alpha \beta \gamma \delta }}HL\left(2n\right)$$

(11)

$$q\left(LL\right)=h_{LL}^{\ast }\times {\displaystyle \frac{1}{\alpha \beta \gamma \delta }}LL\left(2n\right)$$

(12)

$$h_{HH}^{\ast }={\left(\alpha \beta \gamma K\right)}^2\times h_{HH}$$

(13)

$$h_{LH}^{\ast }={\left(\alpha \beta \gamma \right)}^2\delta \times h_{LH}$$

(14)

$$h_{HL}^{\ast }={\left(\alpha \beta \gamma \right)}^2\delta \times h_{HL}$$

(15)

$$h_{LL}^{\ast }={\left({\displaystyle \frac{\alpha \beta \gamma \delta }{K}}\right)}^2\times h_{LL}$$

(16)

In a five-level 2D DWT, each wavelet subband has different quantization step sizes, though the step size remains constant within each subband. The quantization result is obtained by multiplying the DWT wavelet coefficients by the corresponding quantization coefficients, converting the formula from Equation (7) to Equation (8). In Equation (8), $S\left(n\right)$ represents the subband components processed by DWT and h denotes the quantization coefficient. The quantization coefficients for different levels and subbands are shown in

Table 1. Quantization coefficients for different subbands.

Subband	h	${\mathit{h}}^{\ast }$
HH1	1.040466	0.008674635
HL1	1.011230	0.002468401
LH1	1.011230	0.002468401
HH2	1.934753	0.016130537
HL2	1.997070	0.004874826
LH2	1.997070	0.004874826
HH3	4.160461	0.034686842
HL3	4.183838	0.010212703
LH3	4.183838	0.010212703
HH4	8.605042	0.071742466
HL4	8.542175	0.020851355
LH4	8.542175	0.020851355
HH5	17.392761	0.145007958
HL5	17.173950	0.041921423
LH5	17.173950	0.041921423
LL5	16.995850	0.012146502
LL1-LL4	1	0.000714675

. Since Equations (5), (6), and (8) all involve multiplication, their coefficients can be combined into a single operation. By replacing Equations (5) and (6) in the column transformation with Equations (9)–(12), the scaling and quantization steps can be performed simultaneously. In Equations (9) to (12), the $HH(2n+1)$ and $HL\left(2n\right)$ components are derived by applying row transformation to the column transformed H component. Similarly, the $LH(2n+1)$ and $LL\left(2n\right)$ components result from row transformation on the column transformed L component. In the scaling process following DWT encoding, the HH subband component is multiplied twice by the coefficient $\alpha \beta \gamma K$ from Equation (5), while the LL subband component is multiplied twice by the coefficient in Equation (6). The LH and HL subband components are each multiplied once by the coefficients in Equations (5) and (6), respectively. The combined coefficient is obtained by applying these multiplications to the original quantization coefficient, as shown in Equations (13)–(16). The specific values of the combined coefficients $h^{\ast }$ for each subband are provided in Table 1.

By combining quantization with the scaling step in the column transformation of DWT, as described in Equations (9)–(16), both DWT and quantization in JPEG2000 encoding are completed without adding hardware resources or clock cycles to the original DWT module. This approach effectively improves the efficiency of JPEG2000 encoding. Furthermore, encoding with different quantization step sizes can be achieved by modifying the h values in Table 1 and computing the corresponding $h^{\ast }$ values using Equations (13)–(16) for substitution, demonstrating the flexibility of this approach.

3. Proposed Architecture for Multi-Level 2D DWT

3.1. Folded and Unfolded Architecture

Considering each flipping equation being computed through two additions and one multiplication, and acknowledging $Tm\approx 2Ta$, a three-input basic processing unit (BPU) has been designed. This BPU, delineated by the dashed box in Figure 2 and Figure 3, executes two additions and one multiplication concurrently, thereby reducing the CPD to $Tm$. Notably, the ∗ sign in the figures signifies the necessity for the multiplier input to precede the adder input by one clock cycle, ensuring accurate timing synchronization.

The proposed folded architecture and unfolded architecture are based on the BPUs proposed above as shown in Figure 2 and Figure 3, where only row filters include the scaling module. The folded architecture is characterized by its utilization of a solitary BPU, which is complemented by MUXs to modulate the outputs from the adder and multiplier to sequentially address the four lifting equations. Additionally, the unfolded architecture is constructed upon a four-stage pipeline framework, whereby each stage is equipped with a distinct BPU that is tasked with the computation of one of Equations (1) through (4), respectively. Since only one BPU is utilized, the folded architecture necessitates four clock cycles to compute four lifting equations and sequentially deliver two lifting results over two cycles. In contrast, the unfolded architecture, leveraging a pipelined design, is capable of outputting two lifting results per clock cycle. Consequently, this architectural distinction results in a data throughput ratio of 1:4 between the folded and unfolded architectures.

Furthermore, the scaling module tailored for the unfolded architecture, owing to timing constraints, necessitates the deployment of two multipliers to execute the scaling function. In contrast, the scaling module designed for the folded architecture efficiently utilizes a single multiplier, which alternately scales the H and L frequency components.

3.2. Data Input Method

The proposed architecture uses a three-input scanning method with a one-pixel overlap, a technique widely applied in studies such as [21]. This method was chosen for several reasons: both folded and unfolded architectures are three-input systems, so the three-input scanning method, which reads three pixels at once, is ideal for providing input to the encoding module. Additionally, this method only requires overlapping one row per scan, unlike the seven-column overlap used in [23]. This minimizes redundant data encoding, thereby improving encoding efficiency. Furthermore, the three-input scanning method requires less input memory and reduces the internal temporal memory within the architecture to only three units, thereby lowering hardware resource consumption.

As illustrated in Figure 4, our approach adopts a Z-type pattern for reading image pixels, wherein data from three rows are simultaneously accessed. To ensure the timely arrival of $x(2n+1)$, a staggered data input method is employed, as depicted in Figure 5, where the data of identical color are involved in concurrent operations. Additionally, the final line of data, indicated by a dashed circle in the figure, is subjected to overlap scanning.

3.3. Overall DWT Hardware Architecture

The overall architecture of the 2D DWT is presented in Figure 6, and all levels of DWT are predicated upon this overall architecture. Input RAM stores the input image and frame RAM saves the $LL$ components from a low level, while column and row filters execute the lifting process. Based on the sequence of data input, the column filter needs temporal memory for intermediate variables and the row filter merely requires a two-unit buffer. The transposing module rearranges and synchronizes the L and H components from the column filter. Lastly, the scaling and quantization module scales and quantizes the data, obtaining the final DWT results with redundant precision removed. These results are then used for subsequent encoding in JPEG2000.

For the first-level 2D DWT, the influx of raw input data occurs at a rate of three units per clock cycle. To accommodate this rate and ensure the completion of data processing within each cycle, an unfolded architecture for the column and row filters is utilized, as illustrated in Figure 3.

Given that only the $LL$ frequency component from the first-level DWT output requires processing by the second-level DWT, the data volume entering the second-level DWT is a mere quarter of that fed into the first-level DWT. Consequently, for the second-level 2D DWT, the folded architecture is used in the column and row filters to maintain throughput consistency between the two DWT levels. However, a complication arises as the $LL$ components produced by the first-level DWT are delivered every two cycles, while the second-level DWT reads data every four cycles. To bridge this temporal gap, a frame memory storing two rows of data are required.

For third-level and subsequent DWT, the indivisible nature of the folded architecture necessitates an alternative strategy. To address this challenge, a novel multi-level DWT architecture that matches the required throughput is proposed, as depicted in Figure 7. The first and second level both employ a three-way parallel architecture. For 3–5 level DWT, only one folded architecture is deployed, which can process components from three tile blocks by timing adjustments as depicted in Figure 8.

Figure 8 elucidates the timing and sequential data processing of 3–5 level DWT. To ensure staggered data flow, the input to the first-level DWT modules is sequentially offset by four cycles. The initial 12 cycles are dedicated to the uninterrupted processing of data from the third-level DWT modules. Subsequently, every 16 cycles are allocated for processing fourth-level DWT data, and every 64 cycles address the data from the fifth-level DWT. In scenarios limited to five levels of DWT, a pattern emerges where 4 idle cycles are observed after every set of 256 cycles, during which no data processing occurs. However, if additional levels of DWT computation are required, these idle intervals can be strategically utilized for such calculations, though this would increase the clock cycles needed to obtain the encoded data. For an N-level DWT beyond three levels, the system must wait for $4^{(N-2)}$ clock cycles before producing each wavelet coefficient. For example, a 5-level DWT requires a wait of 64 clock cycles, while a 6-level DWT requires 256 clock cycles, which may impact subsequent encoding. Therefore, the proposed architecture is optimally suited for up to 5-level DWT. Furthermore, although a recurring pattern prevents the proposed architecture from achieving 100% hardware utilization, the first two levels reach full utilization, and the final folded architecture achieves 98.44%, leading to an overall hardware utilization above 99.9%. Consequently, the proposed architectural framework demonstrates high efficiency in managing multiple DWT levels, even as the required clock cycles increase for processing beyond five levels.

Assuming that the folded architecture has a maximum throughput of 1. Given that only the $LL$ component from second level is propagated to the third level DWT processing, the collective output from the three modules at the second level equates to $3/4$ of the input data volume for the subsequent third level. This cascading effect results in a proportional reduction of data volume conveyed to the fourth and fifth levels of DWT processing, yielding fractions of $3/16$ and $3/64$, respectively. From this pattern, it is evident that extending DWT processing beyond five levels would culminate in a total data volume sum that remains below unity, as shown in Equation (17). Under the given inequality constraints, 3 is the largest integer that can multiply the left-hand side, making three-way parallelism the maximum achievable level of parallelism. This aggregate is less than the maximum throughput of the folded architecture, thereby enabling one folded architecture to manage the entire data processing workload effectively.

$$3\times (1/4+1/16+1/64+...+1/\left(4^n\right))<1$$

(17)

3.4. Simplified Control Module

A simplified control module is designed for the folded architecture to handle 3–5 levels DWT, which manages image data from different tiles and levels, ensuring DWT computations are executed in the intended sequence. The control module only incorporates three distinct counting signals: cnt3, cnt4, and cnt5. The cnt3 signal is a 4-bit counter with a range from 0 to 15, while cnt4 and cnt5 are 2-bit counters, each with a counting range from 0 to 3. The corresponding counting signals initiate their counting process immediately when the $LL$ component from the preceding level DWT starts being fed into this folded architecture.

As presented in

Table 2. Count signals for 3–5 level DWT.

cnt3[3:0]	cnt4[1:0]	cnt5[1:0]	Level	Module
0–3	x	x	3	1
4–7	x	x	3	2
8–11	x	x	3	3
9–12	1	x	4	1
9–12	2	x	4	2
9–12	3	x	4	3
9–12	4	1	5	1
9–12	4	2	5	2
9–12	4	3	5	3
9–12	4	4	N	N

, when cnt3 is within the ranges of 0–3, 4–7, and 8–11, the third-level DWT is counted for the first, second, and third tile blocks. When cnt3 ranges from 12 to 15, the fourth-level DWT is executed for the first, second, and third tile blocks, contingent upon cnt4 values of 1, 2, and 3, respectively. Likewise, with cnt3 ranging from 12 to 15 and cnt4 set to 4, the fifth-level DWT is performed on the first, second, and third tile blocks based on cnt5 values of 1, 2, and 3. No calculations are conducted when cnt3 is between 12 and 15 and both cnt4 and cnt5 are set to 4. In Table 2, the symbol ’x’ denotes an arbitrary value, while ’N’ indicates that no operation is performed in this instance. Equipped with only three counting signals, the control module effectively reduces hardware complexity. This simplification is further elucidated in the subsequent resource comparison section.

3.5. Transposing Module

A novel transposing buffer module has been developed to align with the temporal requirements of both the unfolded and folded architectural designs. In the unfolded architecture, the continuous flow of column filter data necessitates merely four registers to achieve transposition as Figure 9 shows. Conversely, due to the variable interval arrival of column filter data at different levels within the folded architecture, the transposing buffer, as depicted in Figure 10, employs six registers to store the H and L frequency components separately.

4. Results

In the context of processing input images or tile blocks with dimensions $N\times N$,

Table 3. Hardware resources for the proposed multi-level 2D DWT architecture.

Level	Multiplier	Adder	Register	Temporal RAM	Parallelism
1	10	16	26	$3N$	S
2	3	4	16	$5N/2$	S
3	3	4	40	$5N/4$	$S/3$
3, 4, 5	3	4	112	$35N/16$	$S/3$
1–5	42	64	238	$299N/16$	$3S$

delineates the hardware resource allocation for the proposed multi-level 2D DWT architecture across varying DWT levels. Transposition memory, temporal memory, and frame memory are included in the temporal RAM, and the parallelism S for the proposed architecture signifies the count of tile blocks processed simultaneously.

The transistor-delay-product (TDP) introduced in [21] serves as a viable metric for assessing the efficiency of hardware architectures. Concurrently, the area-delay-product (ADP) proposed in [23] provides a visual framework for comparing the efficiency of different architectures, utilizing synthesis results as a basis. Lower TDP and ADP values signify a more efficient hardware architecture. Equations (18)–(20) detail the calculation involving transistor count (TC), active cycle time (ACT), and data arrival time (DAT), and the TC is calculated using a method from [20]. A lower TC indicates reduced resource consumption and better architectural efficiency; a lower ACT suggests fewer clock cycles required to process an image, reflecting an improved design; and a lower DAT implies reduced latency, indicating a more optimized architecture. Additionally, it is posited that $Tm=2Ta=6.02$ ns.

$$TDP=TC\times CPD\times ACT$$

(18)

$$ACT=N^2/throughput$$

(19)

$$ADP=Area\times ACT\times DAT$$

(20)

Table 4. The hardware performance for 5-level 2D DWT on a 128 × 128 image with $S=3$.

Architecture	Multiplier	Adder	Register	Internal Memory	Input Memory	Throughout Rate	CPD	TC$(\times {10}^5)$	ACT	TDP
[10]	195	270	540	x	x	$6/Ta$	$2Ta$	x	x	x
[12]	0	330	x	x	x	$6/Ta$	$Ta$	x	x	x
[14]	60	120	3567	12,310	1152	$3/2Ta$	$4Ta$	25.71	2730.67	84.53
[20]	43	76	1410	128	896	$3/2Ta$	$4Ta$	7.16	2730.67	23.55
[22]	56	88	318	816	896	$3/Ta$	$2Ta$	5.75	5461.33	18.90
[23]	46	76	90	527	1664	$2/Ta$	$3Ta$	5.06	2730.67	12.47
Proposed	42	64	238	2392	1152	$3/Ta$	$2Ta$	6.47	2730.67	10.63

x: the data are not available in the cited sources.

presents a comparison of hardware performance between existing architecture and the proposed architecture. Notably, while other studies focus solely on DWT encoding, the proposed architecture additionally performs quantization calculations. Refs. [10] and [12] described high-performing single-level DWT architectures recently introduced, assuming a configuration that employs five single-level architectures in series for processing a 5-level DWT. However, accurately estimating the requisite cache resources for multi-level DWT remains problematic. The data presented in Table 4 indicate that although throughput rate and CPD are enhanced in these architectures, a considerable increase in computational resources is required. Consequently, the proposed architecture outperforms existing single-level DWT designs in handling multi-level DWT.

For architectures specifically designed for multi-level DWT, the proposed architecture demonstrates notable improvements. Compared to [14], the proposed architecture features a shorter critical path and a more efficient multi-level structure, achieving twice the throughput, along with a 74.84% reduction in TC and an 87.42% decrease in TDP. Ref. [20] employed excessive registers for caching and exhibits a higher CPD. In contrast, the proposed architecture reduces TC by 9.67%, lowers TDP by 54.83%, and doubles throughput relative to [20]. In Ref. [22], CPD is reduced to $2Ta$, and parallel processing eliminates intermediate variable storage, minimizing RAM usage. However, for DWT levels exceeding three, Ref. [22] required cross-clock domain processing to match throughput, effectively halving the clock frequency and doubling encoding time compared to the proposed architecture. Against [22], the proposed architecture shows a 12.55% increase in TC but a 50% reduction in ACT and a 43.73% decrease in TDP. The input scheme in [23] involves scanning seven rows of pixels repetitively, significantly increasing input memory. Additionally, a lack of register segmentation in the adders and multipliers results in a CPD of $3Ta$. In comparison, the proposed architecture increases TC by 27.97% but lowers CPD by 33.33%, enhancing throughput by 50% and reducing TDP by 14.69%.Overall, for a 5-level DWT, although the proposed architecture slightly increases storage resource usage, it significantly reduces computational resource consumption and CPD. The proposed architecture demonstrates superior hardware efficiency, with at least a 14.69% improvement over existing designs.

Table 5. Synthesis results for the $N\times N$ image without RAM.

Architecture	N	S	Level	DAT (ns)	Area ($\mathsf{\mu }$m2)	Power (mw)	ADP ($\mathsf{\mu }$m2)	EPI ($\mathsf{\mu }$J)
[14]	512	8	3	42.66	3,377,870.70	24.45	3098.72	26.28
[20]	512	8	3	45.58	3,104,371.05	22.59	2318.29	18.50
[22]	512	8	3	27.70	1,362,035.87	12.94	618.14	10.60
Proposed	512	8	3	26.74	999,231.90	23.70	433.35	19.42
Proposed	128	3	5	14.62	409,442.04	16.66	16.35	2.27

EPI: Energy per Image, $EPI=Power\times ACT÷ClockFrequency$.

presents the synthesis results and comparisons excluding RAM. Compared to [14] and [20], the proposed architecture achieves only half the CPD, with a reduction in area exceeding 67.81% and an 81.31% decrease in ADP, indicating significantly higher hardware efficiency. When compared to [22], the proposed design uses fewer computational resources, leading to a 26.64% reduction in area and a 29.89% decrease in ADP. These findings are consistent with the theoretical analysis presented in Table 4. However, the proposed architecture exhibits slightly higher power consumption than the referenced designs. This is primarily due to the frequent data reads and writes to RAM from three distinct tile blocks during encoding. Additionally, the reduced need for repetitive scans results in more frequent internal signal transitions, which may further contribute to the increased power usage. Overall, the analysis indicates although the proposed architecture does not achieve peak hardware efficiency at the configuration of $N=512$, 3-level, and $S=8$, it achieves a 26.64% reduction in area and a 29.89% decrease in ADP compared to the current best-performing design, albeit with increased power consumption.

The proposed architecture was synthesized and implemented on Xilinx FPGA platforms using ISE 14.7, with the results presented in

Table 6. Implemented results on Xilinx FPGA.

Architecture	Device	S	Level	Fmax (MHz)	Registers	LUTs
[4]	XC6VSX315T	1	2	344.34	3922	4708
[5]	XC5VLX330T	1	2	224.00	1536	2092
[17]	XC7Z020CLG484	1	1	34.83	327	1121
Proposed	XC6VSX315T	1	2	165.75	1173	1679
	XC5VLX330T	1	2	188.89	1179	1631
	XC7Z020CLG484	1	1	143.70	629	602
	XC6VSX315T	3	5	149.12	6974	11,379
	XC5VLX330T	3	5	156.92	7064	11,546
	XC7Z020CLG484	3	5	130.14	6974	11,378
	XC7K325T	3	5	169.27	6978	11,378

. The configuration with S = 3 and level = 5 represents the most efficient architecture in this study. When synthesizing for levels 1 and 2, the FPGA synthesis results of the proposed architecture include both the encoding section and the frame RAM for each level. The study in [4] implemented a watermarking DWT algorithm that lowers the CPD using convolution scheme. However, the hardware inefficiencies associated with convolution lead to substantial resource consumption. In comparison, the proposed architecture reduces register usage by 70.09% and LUT resources by 64.34%, though it also results in a 51.86% decrease in maximum clock frequency. In [5], a Haar DWT formula based solely on addition and subtraction operations achieves a lower CPD, though its complex watermarking module results in higher resource usage. Compared to [5], the proposed architecture reduces register consumption by 23.24% and LUT resources by 22.03%, with a 15.67% decrease in maximum clock frequency. Additionally, the results from [4,5] were obtained using the System Generator tool within a MATLAB environment, which differs from the tools used in this study. This variation may introduce discrepancies in the results; therefore, the findings from [4,5] are provided for reference only. In [17], the DWT design is implemented with hardware–software codesign and partial reconfiguration on the Vivado platform, effectively reducing resource usage. However, the extended combinational logic path significantly increases CPD. Relative to this design, the proposed architecture reduces LUT resource usage by 46.30%, increases register usage by 92.35%, and enhances maximum clock frequency by over 3.13 times. Furthermore, the peak efficiency of the proposed architecture is documented in Table 5 and Table 6, correlating with the synthesis results for N = 128, 5-level, and S = 3. Overall, considering resource consumption and maximum clock frequency, the FPGA synthesis results suggest that the proposed architecture demonstrates increased hardware efficiency in managing multi-level DWT and is well-suited for practical applications like JPEG2000.

5. Conclusions and Discussion

This article introduces a novel VLSI architecture for multi-level 2D DWT, utilizing a lifting-based approach, capable of parallel processing various tile blocks. The proposed architecture integrates folded and unfolded architecture, which reduces the CPD to $Tm$, ensuring rate consistency across all DWT levels and improving the throughput rate. Additionally, using only one folded architecture for processing 3–5 level DWT significantly diminishes the computational resources required. The critical quantization module in JPEG2000 encoding has been integrated into the DWT module with minimal additional resource use. Enhancements in the transposing module lead to a reduction in storage resource requirements. The empirical results demonstrate that the proposed architecture yields a reduction in TDP by 14.69%, a decrease in the required area by 26.64%, a diminution in ADP by 29.89%, and utilizes substantially fewer FPGA resources, thereby evidencing enhanced hardware efficiency. Overall, the proposed architecture facilitates more efficient encoding of DWT and quantization in JPEG2000.

In the future, we will continue to investigate efficient architectures for the DWT in JPEG2000, aiming to further reduce the computational and storage resources consumed by the DWT and quantization modules. Additionally, research will be expanded to enhance the processing accuracy of these modules. Improvements to the interface between the quantization module and the subsequent JPEG2000 encoding modules will also be pursued to achieve rate matching, thereby enhancing the overall hardware efficiency of JPEG2000 encoding. Exploring the application of the proposed DWT and quantization modules to other image encoding protocols also represents a future research direction for our work.