Search Results (2,949)

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (${\mathrm{FOM}}_W$) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm²), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs. Full article

This paper presents the architecture, design, and testing results of a scalable, multi-core, multi-function sensor interface, integrating CMOS technology and memristor elements for efficient neuromorphic and bio-inspired analysis. The architecture leverages the high-density and non-volatile properties of memristors to support different analysis functions. Each processing core is equipped with hybrid CMOS/memristor arrays, enabling real-time parallel acquisition and analysis, and each can be configured independently. The system facilitates communication between cores and is fully scalable. The first implementation supports 16 input channels, storing 256 neural signal samples, and the second implementation supports 576 input channels, storing 9k neural signal samples. Full article

The temperature field of an electronic optical instrument can affect the image quality realised by the instrument and, in extreme cases, lead to damage. This is particularly true for instruments operating in harsh environments such as space. The hyperspectral imaging optical instrument (OI) designed for the Intuition-1 (I-1) nanosatellite, currently in low Earth orbit, has been subjected to a numerical analysis of its thermal state under different operating conditions, and some preliminary experimental tests have been carried out to determine the maximum operating temperatures of its sensitive components and the risk of thermal damage. This work was part of a testing campaign prior to the deployment of Intuition-1. Three operational cases were analysed: (1) behaviour in the Earth’s atmospheric conditions when the OI is pointed at the Sun, (2) the end of the de-tumbling process in orbit with the Sun crossing the diagonal of the OI’s field of view, and (3) identification of the maximum possible number of consecutive Earth imaging cycles in orbit. The ultimate goal of this work was to validate the numerical approach used for these cases and to deepen the understanding of the thermal safety of the CMOS image sensor placed in the OI. For these cases, transient thermal field analyses were performed for the OI to determine the temperature distribution and its variability in the most thermally sensitive CMOS image sensor. The components of the OI and its overall structure were experimentally tested, and the results were used to validate the numerical models. The study showed that the built-in temperature sensor does not always reflect the actual CMOS temperature, and in some extreme cases the current temperature monitoring does not ensure its safe operation. Full article

The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHHS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. Full article

This paper presents a low power wideband dB-linear analog baseband (ABB) circuit for a millimeter-wave (mmW) wireless receiver in 40 nm CMOS technology. The proposed ABB system consists of a multi-stage variable gain amplifier (VGA) and a low-pass filter (LPF). The 5-stage VGA is composed of two variable gain units followed by three fixed gain units with DC offset cancellation (DCOC). The first variable gain unit with a self-compensated transistor pair and compact active inductor load is designed for dB-linear functionality and bandwidth extension, respectively. Moreover, a proposed error compensation method is applied to the second cascaded variable gain unit for further dB-linear gain error correction. A 4th-order Butterworth transconductance-capacitance (Gm-C) LPF with flipped source follower (FSF) as an input transconductance stage for linearity enhancement is designed after the VGA stage. The prototype chip is implemented, and measurement results show a dB-linear gain range from −18 to 26 dB with less than 0.5 dB-linear gain error with a bandwidth of 4 GHz. The VGA and LPF consume 8.3 mW and 3 mW, respectively, under a 1 V power supply, while the entire ABB occupies an area of 0.94 mm² with an active core area of only 0.045 mm². Full article

In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively. Full article

Voltage reference circuits are a basic building block in most integrated microsystems, covering a wide spectrum of applications. Hence, they constitute a subject of great interest for the entire microelectronics community. MOSFET-based solutions, in particular, have emerged as the implementation of choice for realizing voltage reference circuits, given the supply voltage scaling and the ever-lower power consumption specifications in various applications. For these reasons, this paper aims to review MOSFET-based voltage reference circuits, illustrating their principles of operation, as well as presenting a detailed overview of the state-of-the-art, in order to paint an accurate picture of the encountered challenges and proposed solutions found in the field in the last decade, thus providing a starting point for future research in the field. Full article

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications. Full article

This paper explores the implementation of a VCO-based ADC, achieving an ENOB of 12 bits with 1 MHz of a sampling rate in the audio bandwidth. The solution exploits the scalability and PVT invariance of a novel digital-to-frequency converter to reduce the size and consumed power. The architecture has been validated in a 130 nm CMOS technology node displaying a power consumption of 105.57 μW and a silicon footprint of 0.034 mm² in a pseudo-differential configuration. Performance can be dynamically adjusted to trade off power consumption by resolution without changing the sampling rate. In addition, the proposed architecture benefits from multiple instantiations in the same SoC, making it particularly suitable for sensor array applications, such as biomedical sensors and spatial audio arrays. Full article

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW. Full article

This article reports a 110.2 MHz ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications. It utilizes a 6.89 MHz MEMS-based oscillator as an input reference. An ultra-low-power, high-resolution phase-frequency detector (PFD) is utilized to achieve low-noise performance. Eliminating the reset feedback path used in conventional PFDs leads to dead/blind zone-free phase characteristics, which are crucial for low-noise applications within a wide operating frequency range. The PFD operates up to 2.5 GHz and achieves a linear resolution of 100 ps input time difference ($\Delta t_{in}$), without the need for any additional calibration circuits. The linearity of the proposed PFD is tested over a phase difference corresponding to aa $\Delta t_{in}$ ranging from 100 ps to 50 ns. At a 1 V supply voltage, it shows an error of <±1.6% with a resolution of 100 ps and a frequency-normalized power consumption ($P_n$) of 0.106 pW/Hz. The PLL is designed and fabricated using a TSMC 65 nm CMOS process instrument and interfaced with the MEMS-based oscillator. The system reports phase noises of −106.21 dBc/Hz and −135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. It consumes 6.709 $\mathsf{\mu }$W at a 1 V supply and occupies an active CMOS area of 0.1095 mm². Full article

Aiming at the problem of energy-efficient design of polynomial coefficient generation algorithms and reconfigurable units in lattice-based post-quantum cryptography, this paper investigates and implements an efficient coefficient generation acceleration engine for multiple algorithms. In this paper, we investigate discrete Gaussian sampling-based and hash function-based coefficient generation schemes separately. For the schemes based on discrete Gaussian sampling, we propose a reconfigurable discrete Gaussian sampling algorithm utilizing a fusion tree structure, which offers greater flexibility in the random number compression through data extraction, and separates the initial sampling from the correction process, thereby achieving high energy efficiency in a parallel architecture. For those based on hash functions, we propose an energy-efficient parallel algorithm for the generation of reconfigurable coefficients, which could be adapted to a variety of uniform, reject, binomial, and ternary sampling schemes. This algorithm makes effective use of the common arithmetic process for all types of sampling schemes and introduces a data allocation process to improve the efficiency of smaller parameter operations, which provides the basis for an energy-efficient design of the hardware architecture. Building upon these two algorithms, we propose a reconfigurable lattice-based post-quantum cryptographic coefficient generation acceleration engine by investigating the algorithm’s core arithmetic parallelism with the goal of resource efficiency. Experimental results showed that under the 40 nm CMOS process, it takes only $256.2$ ns on average to complete the uniform-reject sampling with 256 points rejection value less than $2^{16}$, and $214.2$ ns on average to complete the binomial sampling with 256 points rejection value less than 8 bits. The maximum operating frequency reached 714 MHz, with an average power consumption of approximately $57.37$ mW. Compared to existing studies, the proposed sampler reduced power consumption by about $13\%$ for binomial sampling and about $21\%$ for discrete Gaussian sampling. Full article

A silica waveguide thermo-optic mode switch with small radius bimodal S-bends is demonstrated in this study. The cascaded multimode interference coupler is adopted to implement the E₁₁ and E₂₁ mode selective output. The beam propagation method is used in design optimization. Standard CMOS processing of ultraviolet photolithography, chemical vapor deposition, and plasma etching are adopted in fabrication. Detailed characterizations on the prepared switch are performed to confirm the precise fabrication. The measurement results show that within the wavelength range from 1530 to 1575 nm, for the E₁₁ mode input, the switch exhibits an extinction ratio of ≥13.1 dB and a crosstalk ≤−22.8 dB at an electrical driving power of 284.8 mW, while for the E₂₁ mode input, the extinction ratio is ≥15.5 dB and the crosstalk is ≤−18.1 dB at an electrical driving power of 282.4 mW. These results prove the feasibility of multimode S-bends in mode switching. The favorable performance of the demonstrated switch promises good potential for on-chip mode routing. Full article

A MEMS gyroscope is a critical sensor in attitude control platforms and inertial navigation systems, which has the advantages of small size, light weight, low energy consumption, high reliability and strong anti-interference capability. This paper presents the design, simulation and fabrication of a Y-axis gyroscope with out-of-plane detection developed using CMOS-MEMS technology. The structural dimensions of the gyroscope were optimized through a multi-objective genetic algorithm, and modal, harmonic response and range simulation analyses were carried out to verify the reasonableness of the design. The chip measured 1.2 mm × 1.3 mm. The simulation results indicate that the driving and detecting frequencies of the gyroscope were 9215.5 Hz and 9243.5 Hz, respectively; the Q-factors were 83,790 and 46,085; the mechanical sensitivity was 4.87 × 10⁻¹¹ m/°/s; and the operational range was ±600°/s. Chip testing shows that the static capacitance was consistent with the preset value. The error between the measured frequency characteristics and the simulation results was 1.9%. This design establishes a foundation for the integration of the gyroscope’s structure and circuitry. Full article