Search Results (16)

Huangjinya has recently seen widespread adoption in key tea-producing areas of China, celebrated for its unique varietal traits. Its leaves are also used to produce black tea with distinctive sensory characteristics. The fragrance-enhancing (EF) process is essential in crafting Huangjinya black tea (HJYBT) and is significant in flavor development. However, the impact of EF on non-volatile metabolites (NVMs), volatile metabolites (VMs), and their interactions remains poorly understood. This study aims to investigate how EF temperatures (60 °C, 70 °C, 80 °C, 90 °C, and 110 °C) influence HJYBT flavor transformation. Quantitative descriptive analysis revealed that EF improved the color, aroma, and appearance of tea leaves. Moreover, after an EF temperature of 80 °C, the HJYBT exhibited lower bitterness and astringency, whereas floral, sweet, and fruity aromas became stronger. However, when EF temperatures exceeded 90 °C, a pronounced burnt aroma developed, with HJYBT at 100 °C exhibiting caramel and roasted notes. Partial least squares discriminant analysis indicated that geraniol and linalool contribute to floral and fruity aromas, while 2-ethyl-6-methyl-pyrazine, furfural, and myrcene are key volatiles for caramel and roast aromas. Heptanal, methyl salicylate, α-citral, 1-hexanol, and (E)-3-hexen-1-ol were found to modify the green and grassy odor. Overall, HJYBT treated at 80 °C EF exhibited the highest umami, sweetness, floral and fruity aromas, and overall taste, exhibiting the least astringency, bitterness, and green and grassy notes. These results provide a significant theoretical basis for enhancing HJYBT quality and selecting the optimal EF method. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO₂/Al₂O₃-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO₂ is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO₂/Al₂O₃-based stacks. Full article

HfO₂-based resistive random-access memory (RRAM) with a Ti buffer layer has been extensively studied as an emerging nonvolatile memory (eNVM) candidate because of its excellent resistive switching (RS) properties and CMOS process compatibility. However, a detailed understanding of the nature of Ti thickness-dependent RS and systematic thermal degradation research about the effect of post-metallization annealing (PMA) time on oxygen vacancy distribution and RS performance still needs to be included. Herein, the impact of Ti buffer layer thickness on the RS performance of the Al/Ti/HfO₂/TiN devices is first addressed. Consequently, we have proposed a simple strategy to regulate the leakage current, forming voltage, memory window, and uniformity by varying the thickness of the Ti layer. Moreover, it is found that the device with 15 nm Ti shows the minimum cycle-to-cycle variability (CCV) and device-to-device variability (DDV), good retention (10⁵ s at 85 °C), and superior endurance (10⁴). In addition, thermal degradation of the Al/Ti(15 nm)/HfO₂/TiN devices under different PMA times at 400 °C is carried out. It is found that the leakage current increases and the forming voltage and memory window decrease with the increase in PMA time due to the thermally activated oxidation of the Ti. However, when the PMA time increases to 30 min, the Ti can no longer capture oxygen from HfO₂ due to the formation of self-limited TiO_x. Therefore, the device shows superior thermal stability with a PMA time of 90 min at 400 °C and no degradation of the memory window, uniformity, endurance, or retention. This work demonstrates that the Ti/HfO₂-based RRAM shows superior back-end-of-line compatibility with high thermal stability up to 400 °C for over an hour. Full article

Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promising features of byte-addressability, high storage density, low cost per byte, and near-zero standby energy consumption. However, since NVMs have limited write endurance, high write latency, and high write energy consumption, it is still challenging to directly replace traditional dynamic random access memory (DRAM) with NVMs. Many studies propose to utilize NVM and DRAM in a hybrid memory system, and explore sophisticated memory management schemes to alleviate the impact of slow NVM on the performance of applications. A few studies architected DRAM and NVM in a cache/memory hierarchy. However, the storage and performance overhead of the cache metadata (i.e., tags) management is rather expensive in this hierarchical architecture. Some other studies architected NVM and DRAM in a single (flat) address space to form a parallel architecture. However, the hot page monitoring and migration are critical for the performance of applications in this architecture. In this paper, we propose Transformer, an OS-supported reconfigurable hybrid memory architecture to efficiently use DRAM and NVM without redesigning the hardware architecture. To identify frequently accessed (hot) memory pages for migration, we propose to count the number of page accesses in OSes by sampling the access bit of pages periodically. We further migrate the identified hot pages from NVM to DRAM to improve the performance of hybrid memory system. More importantly, Transformer can simulate a hierarchical hybrid memory architecture while DRAM and NVM are physically managed in a flat address space, and can dynamically shift the logical memory architecture between parallel and hierarchical architectures according to applications’ memory access patterns. Experimental results show that Transformer can improve the application performance by 62% on average (up to 2.7×) compared with an NVM-only system, and can also improve performance by up to 79% and 42% (21% and 24% on average) compared with hierarchical and parallel architectures, respectively. Full article

Group IV quantum dots (QDs) in HfO₂ are attractive for non-volatile memories (NVMs) due to complementary metal-oxide semiconductor (CMOS) compatibility. Besides the role of charge storage centers, SiGeSn QDs have the advantage of a low thermal budget for formation, because Sn presence decreases crystallization temperature, while Si ensures higher thermal stability. In this paper, we prepare MOS capacitors based on 3-layer stacks of gate HfO₂/floating gate of SiGeSn QDs in HfO₂/tunnel HfO₂/p-Si obtained by magnetron sputtering deposition followed by rapid thermal annealing (RTA) for nanocrystallization. Crystalline structure, morphology, and composition studies by cross-section transmission electron microscopy and X-ray diffraction correlated with Raman spectroscopy and C–V measurements are carried out for understanding RTA temperature effects on charge storage behavior. 3-layer morphology and Sn content trends with RTA temperature are explained by the strongly temperature-dependent Sn segregation and diffusion processes. We show that the memory properties measured on Al/3-layer stack/p-Si/Al capacitors are controlled by SiGeSn-related trapping states (deep electronic levels) and low-ordering clusters for RTA at 325–450 °C, and by crystalline SiGeSn QDs for 520 and 530 °C RTA. Specific to the structures annealed at 520 and 530 °C is the formation of two kinds of crystalline SiGeSn QDs, i.e., QDs with low Sn content (2 at.%) that are positioned inside the floating gate, and QDs with high Sn content (up to 12.5 at.%) located at the interface of floating gate with adjacent HfO₂ layers. The presence of Sn in the SiGe intermediate layer decreases the SiGe crystallization temperature and induces the easier crystallization of the diamond structure in comparison with 3-layer stacks with Ge-HfO₂ intermediate layer. High frequency-independent memory windows of 3–4 V and stored electron densities of 1–2 × 10¹³ electrons/cm² are achieved. Full article

With the rapid advances in mobile app technologies, new activities using smartphones emerge every day including social network and location-based services. However, smartphones experience problems in handling high priority tasks, and often close apps without the user’s agreement when there is no available memory space. To cope with this situation, supporting swap with fast NVM storage has been suggested. Although swap in smartphones incurs serious slowing-down problems in I/O operations during saving and restoring the context of apps, NVM has been shown to resolve this problem due to its fast I/O features. Unlike previous studies that only focused on the management of NVM swap itself, this article discusses how the memory management system of smartphones can be further improved with NVM swap. Specifically, we design a new page reclamation algorithm for smartphone memory systems, which considers the following: (1) storage types of each partition (i.e., file system for flash storage and swap for NVM), and (2) access hotness of each partition including operation types and workload characteristics. By considering asymmetric I/O cost and access density for each partition, our algorithm improves the I/O performance of smartphones significantly. Specifically, it improves the I/O time by 15.0% on average and by up to 35.1% compared to the well-known CLOCK algorithm. Full article

The emergence of non-volatile memories (NVM) brings new opportunities and challenges to data management system design. As an important part of the data management systems, several new file systems are developed to take advantage of the characteristics of NVM. However, these NVM-aware file systems are usually designed and evaluated based on simulations or emulations. In order to explore the performance and characteristics of these file systems on real hardware, in this article, we provide an empirical evaluation of NVM-aware file systems on the first commercially available byte-addressable NVM (i.e., the Intel Optane DC Persistent Memory Module (DCPMM)). First, to compare the performance difference between traditional file systems and NVM-aware file systems, we evaluate the performance of Ext4, XFS, F2FS, Ext4-DAX, XFS-DAX, and NOVA file systems on DCPMMs. To compare DCPMMs with other secondary storage devices, we also conduct the same evaluations on Optane SSDs and NAND-flash SSDs. Second, we observe how remote NUMA node access and device mapper striping affect the performance of DCPMMs. Finally, we evaluate the performance of the database (i.e., MySQL) on DCPMMs with Ext4 and Ext4-DAX file systems. We summarize several observations from the evaluation results and performance analysis. We anticipate that these observations will provide implications for various memory and storage systems. Full article

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔV_th) of 13.7 V when it sweeps from −20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 10⁴ s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology. Full article

The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption. Full article

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices. Full article

Secure booting within a field-programmable gate array (FPGA) environment is traditionally implemented using hardwired embedded cryptographic primitives and non-volatile memory (NVM)-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration bitstream loaded into the FPGA during the start-up. The internal configuration access port (ICAP) interface is accessed to read out configuration information of the unencrypted bitstream, which is then used as input to a secure hash function SHA-3 to generate a digest. In contrast to conventional authentication, where the digest is computed and compared with a second pre-computed value, we use the digest as a challenge to a hardware-embedded delay physical unclonable function (PUF) called HELP. The delays of the paths sensitized by the challenges are used to generate a decryption key using the HELP algorithm. The decryption key is used in the second stage of the boot process to decrypt the operating system (OS) and applications. It follows that any type of malicious tampering with the unencrypted bitstream changes the challenges and the corresponding decryption key, resulting in key regeneration failure. A ring oscillator is used as a clock to make the process autonomous (and unstoppable), and a novel on-chip time-to-digital-converter is used to measure path delays, making the proposed boot process completely self-contained, i.e., implemented entirely within the re-configurable fabric and without utilizing any vendor-specific FPGA features. Full article

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2. Full article

The Internet of Things (IoTs) relies on efficient node memories to process data among sensors, cloud and RF front-end. Both mainstream and emerging memories have been developed to achieve this energy efficiency target. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile memory (NVM) has demonstrated great performance in terms of zero standby power, switching power efficiency, infinite endurance and high density. However, it still has a big performance gap; e.g., high dynamic write energy, large latency, yield and reliability. Recently, voltage-controlled magnetic anisotropy (VCMA) has been introduced to achieve improved energy-delay efficiency and robust non-volatile writing control with an electric field or a switching voltage. VCMA-MTJ-based MRAM could be a promising candidate in IoT node memory for high-performance, ultra-low power consumption targets. Full article

The air-core coil sensor (ACS) is widely used as a transducer to measure the variation in magnetic fields of a helicopter transient electromagnetic (TEM) system. A high periodic emitting current induces the magnetic field signal of the underground medium. However, such current also generates a high primary field signal that can affect the received signal of the ACS and even damage the receiver. To increase the dynamic range of the received signal and to protect the receiver when emitting current rises/falls, the combination of ACS with magnetic flux compensation structure (bucking coil) is necessary. Moreover, the optimized ACS, which is composed of an air-core coil and a differential pre-amplifier circuit, must be investigated to meet the requirements of the helicopter TEM system suited to rapid surveying for shallow buried metal mine in rough topography. Accordingly, two ACSs are fabricated in this study, and their performance is verified and compared inside a magnetic shielding room. Using the designed ACSs, field experiments are conducted in Baoqing County. The field experimental data show that the primary field response can be compensated when the bucking coil is placed at an appropriate point in the range of allowed shift distance beyond the center of the transmitting coil and that the damage to the receiver induced by the over-statured signal can be solved. In conclusion, a more suitable ACS is adopted and is shown to have better performance, with a mass of 2.5 kg, resultant effective area of 11.6 m² (i.e., diameter of 0.496 m), 3 dB bandwidth of 66 kHz, signal-to-noise ratio of 4 (i.e., varying magnetic field strength of 0.2 nT/s), and normalized equivalent input noise of 3.62 nV/m². Full article