Version 1
: Received: 30 July 2018 / Approved: 30 July 2018 / Online: 30 July 2018 (14:45:25 CEST)
How to cite:
Bilendo, F.; Shouzhao, S. Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array. Preprints2018, 2018070590. https://doi.org/10.20944/preprints201807.0590.v1
Bilendo, F.; Shouzhao, S. Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array. Preprints 2018, 2018070590. https://doi.org/10.20944/preprints201807.0590.v1
Bilendo, F.; Shouzhao, S. Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array. Preprints2018, 2018070590. https://doi.org/10.20944/preprints201807.0590.v1
APA Style
Bilendo, F., & Shouzhao, S. (2018). Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array. Preprints. https://doi.org/10.20944/preprints201807.0590.v1
Chicago/Turabian Style
Bilendo, F. and Sheng Shouzhao. 2018 "Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array" Preprints. https://doi.org/10.20944/preprints201807.0590.v1
Abstract
Abstract— Flight Control System is an integrated avionics system equipped with the minimum required components for an autonomous flight. This paper focuses on the Hardware Design of the Flight Control System and presents specific details of the components and its interface. The system architecture is based on Field Programmable Gate Array and Digital Signal Processor. Employing these two processors in the flight control system would improve the Flight Control System performance in terms of fast sequential processing of high-level control algorithms. In addition to Field Programmable Gate Array and Digital Signal Processor, the flight control computer system will also make use of Global Positioning System and Micro Electro Mechanical System sensors. The project will be implemented using Altera’s System On Programmable Chip builder, currently known as Qsys – Platform Designer implemented in Quartus-II. The system employs Nios-II processor which is 32-bit soft-core embedded-processor architecture designed especially for the Altera’s family of Field Programmable Gate Array. From conceptualization to final design, this paper presents the functionality of the different modulus and complex interfaces employed in this Flight Control System.
Keywords
Field Programmable Gate Array, Flight Control System, and Hardware Design.
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
