Department of Biomedical Engineering

Digital Logic Design And Computer Architecture Lab

BME (438)

Prepared By: Eng.Ruba AL.Omari Supervised by: Dr.Mashhour Bani-Amer & Dr.Hossam ElKhalil

Spring 2011

Table of Contents
EXP.# TITLE Page Introduction Exercise#1:Development of assembly program Exp#1 Exp#2 Exp#3 Exp#4 Exp#5 Exp#6 Exp#7 Exp#8 Exp#9 Appendix A Appendix B Appendix C References 73 Exercise#2: Speaker Control LED display control 7-Segment Display Control DOT Matrix LED Control Speaker Control Matrix Keyboard Control Step Motor Control Photo-Interrupter Control Output Port Expansion Pre-lab Forms Instructions Addressing Modes 13 16 20 25 27 32 39 42 49 67 71 3

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Experiment#1: Introduction

Assembly language includes:

1. A mnemonic or opcode (abbreviation easy to remember) includes: A. instructions (tell the CPU what to do) B. Directives (give directions)

2. Optionally followed by one or two operands (data items being manipulated)

For example: A. instructions: MOV, ADD, SWAP etc. B. Directives (or pseudo-instructions): ORG, JMPetc

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An assembly program consists of four fields:

[Label:]

Mnemonic

[operands]

[; Comment]

For example: Next: MOV A, #99H ; load 99H into A

Example:

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Development of Assembly Program

Flow charts of 8051 system development

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1. Write Source Program The first step for the development of 8051 program is to writing the source program in assembly language using word processing software.

Exercise#1

The following program is an example of assembly language program written in standard format. We will use this source program to demonstrate the processes of assembling and linking later. Using a word processing program (notepad), edit and save as test.txt

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2. Assembling The assembler is used to translate the assembly language program to machine language. After assembling process, an object file will be generated as well as a listing and a cross reference table if they are selected. Once the source program (test.txt) completed, the next step is to assemble it. This task is performed by X8051.exe. The monitor screen will show the following message:

N: No listing file will be generated. T: Terminal. Print the listing file on computer screen. D: disk. Save the listing file generated on disk and use LST as the extension file name. E: Error only L: LIST ON/OFF P: printer. Print the listing file generated from computer. If D is selected, the following message will appear to ask the user whether a cross reference table is to be generated or not.

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*Input filename: enter the source program filename to be assembled. (test.txt) *Output filename: Enter output filename (test), this filename will be the filename of object (.OBJ) and listing (.LST) generated (TEST.OBJ & TEST.LST)

Listing file is a text file includes line number, address, machine code, and source code as shown below

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3. Linking To link an object, load and run LINK51.EXE as shown below

*Input filename: enter the first object filename to be linked. Since OBJ is the default extension filename, therefore an extension is not necessary.

*Enter offset for 'CODE': Enter the offset value of memory fro machine code. In general press enter key to assign this task to linker.

*Input filename: Enter the second object filename to be linked. If none press the enter key.

*output filename: enter output executable filename. If same as the first object, press enter key.

*library filename: Enter the library filename to be linked. If none, press enter key.

*Options(D,P,U,A,C,M,N,R,S,Z,E,H,T,X,1,2,3 ) : These options are used to select the format of executable file to be generated. (The default is hex file (.HEX))

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4. Programming1:

Once HEX code file is generated, the next step is to write this code into the program memory of the 8051. The code will be downloaded into flash memory by ISP driver through the serial port on the PC. According to the I/O device to be controlled, set the corresponding switch of SW2 in ON position and others in off position.

Exercise #1 will sequentially and repeatedly turn on/off the 8 LEDs (LED pack D5) from the left most LED to the right most LED, so you should place the SW2-4 in ON position.

1. Turn on the power of MTS-51 and connect RS-232 cable to PC COM port as shown in Figure#1. 2. Make sure that JP5 is connected to +12V as programming voltage. 3. Press ISP button to enable the ISP function (LED D1 will light up) 4. Place 3rd (RXD3) and 8th (TXD3) switch of SW1 to ON position to enable the serial transmission function.

Figure#1: MTS-51 Programming

http://www.kandh.com.tw

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5. Launch Flash Magic (Figure#2) 6. Select Chip to 89C51RD+ (make sure that the chip model on Your MTS-51 also mark as ''89C51RD+'') 7. Select Port No. (Must match the COM port No. in your PC) 8. Input Oscillator frequency as 12.

Figure#2

9. Select [Erase all flash] to erase the old programs stored in 8051 chip. 10. Press [browse] button and browse the complied file (*.HEX) into the software buffer.

Important: DO NOT check Security bits Bit 1, 2, and 3 . Or you will not be able to program the chip in the future.

11. Press start to start programming the chip 12. Release the ISP button. 13. Use DIP switches SW1 or SW2 to enable the related I/O.
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14. Press RESET button to execute the program.

Figure#3

Exercise# 2: Speaker Control Download the following program on the MTS-51 trainer and describe the program function as you will see on the trainer.

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Experiment# 2: LED Display Control

I. Objective 1. To demonstrate that I/O port 2 controls LED pack (D5) on the MTS-51 Trainer. 2. To study the driving circuit for the LED Pack (D5) using 74LS240.

II. Circuit Description LED pack (D5) containing 8 LEDs is driven by 74LS240. If input is a one, the corresponding LED will be turned on. If input is a zero, the corresponding LED will be turned off. Resistor pack RS4 serves current limiting to LEDs. P2: used to control LED pack D5.

Exercise# 1: Functional Description: Sequentially turn on/off the 8 LEDs from the left most LED to the right most. When the right most LED is reached, the sequence is inverted. The ON time of each LED is 0.1 seconds. Return to the introduction to follow the development of assembly program procedure.

For more details about the circuit, return to 74LS240 datasheet.

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Source Program and Description

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Software delay is usually needed to hold the output data an appropriate time because CPU runs at high speed. Delay is done by executing the instructions which have no effect to output data.

Delay Calculations: Delay of the delay subroutine is equal to the product of total machine cycles and the machine cycle time as follows: Instruction MOV DL1: MOV DJNZ DJNZ RET R6, #200 R7, 249 R7, $ R6, DL1 Machine cycle 1 1 2 2 2 200 249 X 200 200 1 Execution Time (s) 1

Total Machine cycles= Total product of machine cycle and execution time =1 200 1 249 2 2 2 100,203.

Since the oscillator frequency of the MTS-51 trainer is 12 MHz, 1 s every machine cycle, therefore a total of delay is equal to 0.1 second (=100203 1s 0.1s ).

Exercise#2. will be given in the Lab (10%)

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Experiment#3: 7-Segment Display Control

I. Objective 1. Describe how to use the BCD-to-7-segment decoder/driver (74LS47). 2. To demonstrate that I/O lines of P2.3-P2.0 are the inputs of DS4 (units digits) and P2.7-p2.4 lines are the inputs of DS3 (tens digit).

II. Circuit Description

The control signals to these sections are from P2 lines. The BCD-to-7-seg decoder/driver (74LS47) decodes BCD input and shows the corresponding number on the 7-seg-display.

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Truth Table of 74LS47 BCD Inputs P2.6 P2.5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 74LS47 Outputs (Segment Inputs) Pin13 Pin12 Pin11 Pin10 Pin9 Pin15 Pin14 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 0 1 1

P2.7 0 0 0 0 0 0 0 0 1 1

P2.4 0 1 0 1 0 1 0 1 0 1

7-seg display (Common anode) Connection

Exercise#1: Functional Description: Sequentially and repeatedly show the numbers 00 through 99 on DS3 and DS4. Each number stays on 0.5 seconds.

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 Return to the introduction to follow the development of assembly program procedure:

Note: SW2-3 switch should be placed in ON position.

Source Program & Description

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Exercise#2: Embedded System (Digital Thermometer)(10%)

As portability becomes a growing trend in medical instruments, biomedical engineers are seeking

technologies that reduce the design complexity and time in developing the final medical instrument. The (P89C51RD+) microcontroller offers a platform of ultra-low-power processors with the high

integration of the complete signal chain that is required for applications such as digital thermometer.

In this exercise, we will write an assembly program that will display continuously the following human temperatures on DS3 and DS4.

42, 41, 40, 39, 38, 37, 36, 35.

Exercise# 3 will be given in the Lab

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Experiment# 4: Dot Matrix LED Control.

I. Objective 1. To demonstrate that port 2 and 0 controls 8 8 dot matrix LED on the MTS-51 trainer. 2. To understand how to use 74LS245 and 2803 for controlling the rows and columns signals respectively.

II. Circuit Description D3 is a common cathode matrix LED (all LED Cathodes are connected to the column line) as shown in Figure #1 below. When a row signal is high and a column signal is low, the corresponding LED is turned on.

The row scan signal is emitted from P2 lines through IC (74LS245) and the column scan signal is emitted from P0 through IC (2803).
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Both row and column scan signal are active-high signals. That is, all LEDs are turned on when the row and column signals are all 1s. The 2803 Darlington pairs are used to sink column currents (Return to 2803 datasheet). See Figure#2.

74LS245

The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input (pin 1). The enable input (G) can be used to disable the device so that the buses are effectively isolated.

Function Table for 74LS245

Enable L L H

DIR L H L or H

Operation B data to A bus A data to B Bus Isolation

Exercise#1 Functional Description: Sequentially turn on the column LEDs from column 1 to column 8 eight time, and then turn on the row LEDs from row 1 to row 8 eight times.

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Return to the introduction to follow the development of assembly program procedure.

Source Program

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Program Description
Command Description

CLR

P1.7

MOV

P2,#FFH

When the matrix LED is controlled by program, this command must be used to float LCM data bus to prevent the P0 signal from electrical interference P2 emits FFH to row lines

MOV MOV RR

A,#10000000B P0,A A

P0 emits a 1 to column 1(C1), then the LEDs in this column are turned on The 1 is shifted to column 2 by rotate instruction to turn on the LED in C2. To turn on the LEDs row after row, P0 emits FFH to column lines P2 emits a 1 to row 1 (R1), then the LEDs in this row are turned on The 1 is shifted to row 2 by rotate instruction to turn on the LED in R2.

MOV MOV MOV A

P0,#FFH A,#10000000B P2,A RR

Exercise#2 Now modify the above program to show a 5 7 letter A on dot matrix LED.

Source Program and Description:

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 Exercise#3. will be given in the Lab (10%)

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Experiment#5: Speaker Control

I. Objectives 1. Describe the operation of the driving circuit for SP1 speaker.

II. Circuit Description The circuit of speaker and driver is shown in figure# 1 below.

The signal to the driver input comes from (P 3.7) pin. When a high is fed to the driver input, the speaker is driven to ON. When a low is fed to the driver, the speaker is turned off.

Exercise# 1 Functional Description: Speaker sounds a 1 KHz tone.

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Source Program:

Exercise#2 We have discussed the Pulse tone generator circuit in biomedical Instrumentation Lab I (See Figure #2 below), Write an assembly program that will simulate the output pulses at Tp20

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Experiment# 6: Matrix Keyboard Control.

I. Objective 1. To demonstrate the using of the keyboard circuit KB1. 2. Evaluate the operation of 74C922.

II. Circuit Description The keyboard circuit is built by the matrix keyboard KB1 and encoder 74C922.

Referring to figure#1 shown below, if a key is pressed, the corresponding binary value will present on the outputs DOD-DOA (P1.3-P1.0) of the encoder and a high potential presents on the DA (data available) pin.

The DA signal is inverted by an inverter and then connected to the P3.2 (INT0) pin.

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Keyboard Encoder Features: 1. The output is a key value in binary. 2. It has a debouncing circuit for eliminating the noise produced by mechanical keys. 3. Tri-state output is compatible with data bus of microcomputer. 4. Pin description: 4.1. X1, X2, X3, and X4: Inputs for the column lines of the matrix keyboard. 4.2. Y1, Y2, Y3, and Y4: Inputs for the row lines of the matrix keyboard The relationship between X and Y is shown in Figure#2 below.

The binary value on the 74C9221 output is listed on Table#1. Key Location DOD X1,Y1 0 X2,Y1 0 X3,Y1 0 X4,Y1 0 X1,Y2 0 X2,Y2 0 X3,Y2 0 X4,Y2 0 X1,Y3 1 X2,Y3 1 X3,Y3 1 X4,Y3 1 X1,Y4 1 X2,Y4 1 X3,Y4 1 X4,Y4 1 Table#1 Encoded Output DOC DOB DOA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Keys in row 1

Keys in row 2

Keys in row 3

Keys in row 4

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For more details about theory of operation, return to 74C922 data sheet.

4.3. DOA, DOB, DOC, and DOD: Tri-state encoded data outputs. DOA is LSB and DOD is MSB.

4.4 OE: Output Enable. When this pin is low, the encoded value presents on the Encoded output pins. When this pin is high, the encoded outputs present high impedance.

4.5 DA: Data Available. When a key is pressed, a high presents on the DA pin.

4.6 OSC: On-Chip oscillator input. The pin can directly receive external clock pulses or externally connects a 0.1F capacitor.

4.7 KBM: when a 1- F capacitor is connected to this pin, the noise caused by mechanical keys is eliminated.

5. CMOS configuration operates in the voltage 3-15 Volts range.

6. The use of 74C922 simplifies the task of program design and improves the efficiency of execution.

7. The DA signal is an active-high signal. To communicate the microprocessor with active-low interrupt input (INT0), the DA signal should be inverted by an inverter gate.

Registers related to interrupt: 1. Interrupt Enable Register(IE) The bit diagram of the IE register is shown below.

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EA EA (IE.7):

ET2

ES

ET1

EX1

ET0

EX0

Disable all interrupts. If EA=0, no interrupt will be acknowledged.

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. The instruction CLR EA will

disable all interrupts.

EX0 (IE.0): Enable or disable external interrupt 0. ET0 (IE.1): Enable or disable timer 0 overflow interrupt. EX1 (IE.2): Enable or disable external interrupt 1. ET1 (IE.3): Enable or disable timer 1 overflow interrupt. ES (IE.4): Enable or disable serial port interrupt.

ET2 (IE.5): Enable or disable timer 2 overflow or capture interrupt (8052 only). For example, the instruction MOV IE, #10001001

Enables external interrupt 0 and timer 1 overflow interrupt, and disables other interrupts.

2. Timer/Counter Control register (TCON) The bit diagram of the IE register is shown below.

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

IT0, IT1: External interrupt 0 type control bit IT0 (bit 0) and external interrupt 1 type control bit IT1 (bit 2). These two bits must be set/ cleared by software to specify falling-edge/low- level triggering external interrupt.

IT0=0 ------------ Low-level triggering.

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IT0=1------------- Falling-edge triggering.

Exercise #1 Functional Description: It shows the key number on the 7-seg display (DS4) when a key is pressed. Place SW2_3 in ON position.

Source Program

Program Description Interrupt System Control 1. Main Program (1) The starting address of main program must leave from the interrupt vector area-----------------------(ORG 100H)

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(2) Specify IE to enable the interrupts to be used and disable unused interrupts------------------ (MOV IE, #10000001B) (3) Specify IT0 or IT1 to determine the triggering type if external interrupt are used-----------------------(CLR IT0) (4) Write main program and wait for an interrupt.

2. Interrupt service routine (ISR): It performs the function required by device. (1) Place a jump instruction in the interrupt vector and point to the starting 003H)

address of interrupt service routine-----------(ORG (2)

Reset IE to disable other interrupts during the interrupt service routine is EX0)

executing---------------------(CLR (3)

Save the contents PSW or other registers in main program onto stack

using PUSH instruction. (4) (5) (6) Write interrupt service routine--------------(MOV Enable interrupts---------------------(SETB Return from interrupt using RETI instruction. EX0) P2,P1)

Exercise#2
Write an assembly program that will do the following: 1. If key ''1'' is pressed, the speaker generates BEEP-BEEP Sound (exercise#2 in Exp#5) 2. If Key ''0'' is pressed, the speaker generates a 1KHz tone (exercise#1 in Exp#5)

Exercise# 3 will be given in the Lab

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Experiment#7: Step Motor Control.

Objective 1. This experiment demonstrate the control of the 4-phase step motor M1 on MTS-51 trainer. 2. Describe the operation and switching schemes of the step motor.

Circuit Description

74LS240 IC is used to invert the input signal and to promote the driving capability of 8051 Port 2. The enable inputs 1 G and 2 G are controlled by the switch SW2-8.

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When this switch is in off position, 1 G =2 G =1, the outputs of 74LS240 are in high impedance state so that the motor stops (according to the logic diagram of 74LS240). The port 2 lines (P2.3-P2.0) are connected to the A, B, A and B coils of step motor, respectively. Since 74LS240 is an inverter, the corresponding coil will be energized if the switching signal is 0.

The FT5457 contains four Darlington pairs act as electronic switches to switch motor coils on or off.

Step Motor Operation

1. Step Motors are electromagnetic incremental motion actuators, which convert digital pulse inputs to analog output motion. One pulse advances the rotor shaft one step increment (Step angle = 1.8) and latches it magnetically at the precise point to which it is stepped.

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2. Figure #2 shows the connection of the step motor for uni-polar drive. In practice the switches in Figure#2 are replaced by switching transistor. These power transistors receive the digital pulses to input terminals and energize motor coils.

3. Switching Schemes: There are three switching schemes: 1-Phase-on switching, 2-Phase-on switching, and 1-2-Phase-on switching.

1. One (single) Phase on Switching (Wave drive): Table#1 shows the truth table of 1-Phase-on switching scheme. In this drive method only a single phase is activated at a time. It has the same number of steps as the full step drive, but the motor will have significantly less than rated torque. It is rarely used.

Step 1 2 3 4 5

Coil Energized Direction of Rotation A B A CW CCW B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 Table#1

2. Two Phases on Switching (Full step drive): Table#2 shows the truth table of 2-Phase-on switching. This is the usual method for full step driving the motor. Two phases are always on. The motor will have full rated torque.
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Step 1 2 3 4 5

Coil Energized Direction of Rotation A B A CW CCW B 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 Table#2

3. Half stepping One pulse advances the rotor half the step angle. When half stepping, the drive alternates between two phases on and a single phase on. This increases the angular resolution, but the motor also has less torque (approx 70%) at the half step position (where only a single phase is on).

Step 1 2 3 4 5 6 7 8 9 10

Coil Energized A B A B 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0

Direction of Rotation CW CCW

0 Table#3

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Exercise#1 Functional Description: Drive the step motor to rotate CW using two phase-on switching. Source Program:

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 Exercise#2 Wheelchair . ..10% Wheelchairs (which include step motors) play an important role in helping the handicapped and the elderly people to live more independently at home and have a low cost on their healthcare.

Write an assembly program that will do the following:

1. If Key ''1'' pressed on KB1, the chair will rotate half revolution right.

2. If Key ''2'' pressed on KB1, the chair will rotate half revolution left.

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Experiment# 8: Photo-Interrupter Control

I. Objective 1. Study the schematic diagram of photo interrupter (PH1, and PH2) and the pulse generator circuit. 2. To demonstrate the control applications of photo-interrupter, for example controlling the direction of rotation of the step motor.

II. Circuit Description The MTS-51 has two photo-interrupters PH1 and PH2. When light is blocked, the photo-transistor is cut-off and a low presents on the inverter output terminal. When light is not blocked, the photo-transistor conducts in saturation and a high presents on the inverter output terminal.

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PH1 output can be connected to T1 or INT1 using a jumper cap on JP3. PH2 output can be connected to T0 using a jumper cap on JP4. The output signal of pulse generator is connected to pin 3 (OSC) of JP4. Using a jumper cap, the signal to T0 input of 8051 can be selected from PH2 output or pulse oscillator output.

T0 (P3.4): Timer/counter 0 external input T1 (P3.5): Timer/counter 1 external input INT1 (P3.3): External Interrupt input 1, the memory location for INT1 = 013H

Exercise#1 Functional Description: Use PH2 output to control the direction of rotation of the step motor. When PH2 is not blocked by an object (for example a piece of paper), the step motor rotates CW. If PH2 is blocked by an object, the step motor rotates CCW. Connect Pins 1 and 2 together using a jumper cap.

Source Program:

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Program Description

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Exercise#2

Connect jp3 pins 2 to 3 and jp4 pins 1 to 2 1. Increment the value of counter every PH2 output pulse and decrement the value every PH1 output pulse, and show the result on DS3 and DS4.

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Experiment # 9: Output Port Expansion

I. Objectives

1. Understand the serial components used in the MTS-51 trainer. 2. Demonstrates the technique of output port expansion using 8051 serial port in mode 0.

II. Circuit Description

The MTS-51 trainer contains three serial components 74164(output port expansion), 74165(input port expansion), and RS-232. DIP switch SW1 is used to select the serial components connected to RXD (P3.0) and TXD (P3.1) pins.

RXD (P3.0): Serial input port TXD (P3.1): Serial output port

The serial port can operate in four modes: mode 0, mode1, mode2 and mode3 We will study mode 0 only.

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Mode 0:
Serial data enters and exits through RXD. TXD outputs the shift clock pulses. 8 bit are transmitted: 8 data bits with LSB first. The baud rate is fixed at 1/12 the oscillator frequency.

Since mode 0 operates as a shift register, so it is usually used as an expanded I/O port.

In Figure #1 the data is transmitted through RXD to the serial in (SIN) terminal of the 74164 serial in parallel-out (SIPO) shift register. In this case, the serial port operates as an 8-bit output port. The clock pulse comes from TXD to the CK input of shift registers.

The parallel outputs of 74164 are connected to BCD-to-7-segment decoder 74LS47 to drive 7-segment display, and connected to buffer 74LS240 to drive LEDs. See Figure#2.

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8051 registers related to serial port:

Registers SBUF and SCON are the most important registers in UART operation.

1. SBUF: Serial Data Buffer

The SBUF is actually two separate registers, one transmits buffer register and one receive buffer register. When a byte data is moved to SBUF, it goes to the

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transmit buffer where it is held for serial transmission. When a byte data is moved from SBUF, it comes from the receive buffer.

2. SCON: Serial Port Control Register

The serial port control and status register SCON locates in the address 98H of SFR. Its bit diagram is shown below. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

1. SM0 (SCON.7): Serial port mode select bit 0

2. SM1 (SCON.6): Serial port mode select bit1

There are four modes in UART operation specified by the bits SM0 and SM1. A table of mode 0 is shown below.

SM0 0

SM1 0

Mode 0

Function Shift register

Baud Rate Fosc/12

Mode 0 is usually used to expand the I/O lines.

3. TI (SCON.1): Transmit interrupt flag

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Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. This flag must be cleared by software.

4. RI (SCON.0): Receive interrupt flag Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). This flag must be cleared by software.

Exercise#1 Place SW1-1 and SW1-6 in ON position. Functional Description:

1. Sequentially turn on/off LEDs from left to right 4 times. 2. Sequentially turn on/off LEDs from right to left 4 times.

Source Program: ORG MOV START: MOV MOV NR1: RR MOV JNB CLR CALL A SBUF,A TI,$ TI DELAY R5,#4 A,#00000001B ;SET COUNTER 000H SCON,#00000000B ;SET MODE 0

;SEND DATA

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JNB DJNZ MOV MOV NL1: RL MOV JNB CLR CALL JNB DJNZ DELAY: MOV DL1: MOV DJNZ DJNZ RET END

A.0,NR1 R5,NR1 R5,#4 A,#10000000B ;SET COUNTER

A SBUF,A TI,$ TI DELAY A.7,NL1 R5,NL1

;SEND DATA

R6,#200

R7,#249 R7,$ R6,DL1

Program Description a. Clear SM0, SM1, and SM2 bits in the SCON register.

MOV

SCON,#00000000B

b. Clear TI bit: clears transmit interrupt flag for next data transmission.

CLR

TI

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c. Move data to SBUF. The data in SBUF exits from the RXD pin and the Shift pulse exits from the TXD pin.

MOV

SBUF,A

d. when the 8th data bit is transmitted, the TI is set by hardware. For next data byte transmission, repeat steps b and c. JNB TI,$

(Checks to whether the 8-bit pattern data is transmitted or not.)

Exercise#2 will be given in the Lab

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Appendix A Pre-Lab Forms

Pre-lab # Page

Pre-lab # 2

51

Pre-Lab#3

53

Pre-Lab#4

55

Pre-Lab#5

57

Pre-Lab#6

59

Pre-Lab#7

61

Pre-Lab#8

63

Pre-Lab#9

65

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.2: LED Display Control Pre-lab

Name: Number:

10

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1. Complete the following table according to Exercise#1. (Return to Figures #1 and #2)

2. Describe the operation of 74LS240.

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.3 7-Segment Display Control Pre-lab

Name: Number:

10

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1. According to exercise#1 and Figure#1, complete the following table:

HINT: Loop# 2 will display 0 1 on DS3 and DS4 respectively as shown below

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.4: Dot Matrix LED Control Pre-lab

Name: Number:

10

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1. According to Exercise#1, complete the following table and color the suitable LED (column or row) for each DOT matrix in loops# 3, 65, 66 and 67.

2. Write an assembly program that will display an

X mark blinking on D3 dot

matrix. The on/off time of the blinking equals one second.

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.5: Speaker Control Pre-lab

Name: Number:

10

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1. Describe how the speaker sounds a 1 KHz tone in exercise #1?

---------------------------------------------------------------

---------------------------------------------------------------

---------------------------------------------------------------

2. Complete the following truth table of the circuit in Figure#1:

P3.7 L H

Base of Q1

Collector of Q1

SP1

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.6: Matrix Keyboard Control Pre-lab

Name: Number:

10

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1. According to exercise# 1, answer the following: 1.1 Complete the following table.

1.2 When a key is pressed as shown in the figure#3, CPU detects the external interrupt input and executes the interrupt service routine (ISR) INT0. The ISR reads the encoded outputs of 74C922 and sends to the inputs of BCD to- 7segment decoder

I. What are the value of a, b, c, d, e, f, g, and h? a b c d e f g h

II. Color the suitable numbers on DS3 and DS4.

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.7: Step Motor Control Pre-lab

Name: Number:

10

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1. According to exercise#1, complete the following Table:

Loop # 1 2 3 4

Motor Coils A 0 B 1
A B

8051 Port 2 P2.3 P2.2 P2.1 P2.0

2. Rewrite the program in exercise#1 using RR instruction.

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.8: Photo Interrupter Control Pre-lab

Name: Number:

10

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1. According to exercise #1, complete the following Table according

P3.4 Loop# 1 2 0 3 4 1 2 1 3 4

P2.0

P2.1

P2.2

P2.3

2. Write an assembly program that controls the rotation of the step motor as follows:

a. Use PH1 output to control the direction of rotation of the step motor. When PH1 is not blocked by an object, the step motor rotates CW. If PH1 is blocked by an object, the step motor will rotate one revolution CCW and then rotate CW.

b. Connect pin 2 and 3 of JP3 together using a jumper cap.

Return to Exp# 5 for more information about interrupt registers and interrupt system control.

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Faculty of Engineering

Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab BME 438

Exp.9: Output Port Expansion Pre-lab

Name: Number:

10

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Wrist Pulse Oximeter with Visual Alarm

Use the technique of Table Look-UP to repeatedly display the following pulse rate readings on DS1 and DS2

70, 75, 80, 85, 75, 70, 90, 85, 75

And when BPM reaches 90, D5 LEDPACK will blink two times. Use 1 second delay for displaying BPMs and for blinking.

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Appendix B Instructions
The number of instruction bytes is the number of memory locations required for this instruction. The execution time of an instruction is determined by its machine cycles. One machine cycle contains 12 oscillator periods. Data Transfer Instructions
Mnemonic MOV A,#data MOV A,direct MOV A,Rn MOV A,@Ri MOV direct,A MOV direct,#data MOV direct,direct MOV direct,Rn MOV direct,@Ri MOV Rn,A MOV Rn,#data MOV Rn,direct MOV @Ri,A MOV @Ri,#data MOV @Ri,direct MOV DPTR,#data16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct POP direct XCH A,direct XCH A,Rn XCH A,@Ri XCHD A,@Ri Description Move immediate data to accumulator Move direct byte to accumulator Move register to accumulator Move indirect RAM to accumulator Move accumulator to direct byte Move immediate data to direct byte Move direct byte to direct Move register to direct byte Move indirect RAM to direct byte Move accumulator to register Move immediate data to register Move direct byte to register Move accumulator to indirect RAM Move immediate data to indirect RAM Move direct byte to indirect RAM Load data pointer with a 16-bit constant Move code byte relative to DPTR to ACC Move code byte relative to PC to ACC Move external RAM (8-bit addr) to ACC Move external RAM (16-bit addr) to Acc Move Acc to external RAM (8-bit addr) Move Acc to external RAM(16-bit addr) Push direct byte into stack Pop direct byte from stack Exchange direct byte with accumulator Exchange register with accumulator Exchange indirect RAM with accumulator Exchange low order digit indirect RAM with Accumulator Byte 2 2 1 1 2 3 3 2 2 1 2 2 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 Cycle 1 1 1 1 1 2 2 2 2 1 1 2 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1

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1. 2. 3. 4.

MOV instructions are used to move data in the internal RAM. MOVX instructions are used to move data in the external RAM. MOVC instructions are used to move the code byte in ROM. Exchange instructions use A as the destination operand.

Arithmetic Operation Instructions

Mnemonic ADD A,#data ADD A,direct ADD A,Rn ADD A,@Ri ADDC A,#data ADDC A,direct ADDC A,Rn ADDC A,@Ri SUBB A,#data SUBB A,direct SUBB A,Rn SUBB A,@Ri INC A INC direct INC Rn INC @Ri INC DPTR DEC A DEC direct DEC Rn DEC @Ri MUL AB DIV AB DA A Description Add immediate data to accumulator Add direct byte to accumulator Add register to accumulator Add indirect RAM to accumulator Add immediate data to acc with carry Add direct byte to accr with carry Add register to accumulator with carry Add indirect RAM to acc with carry Subtract immediate data from acc with borrow Subtract direct byte from acc with borrow subtract register from acc with borrow Subtract indirect RAM from acc with borrow Increment Accumulator Increment direct byte Increment register Increment indirect RAM Increment data pointer decrement Accumulator decrement direct byte decrement register decrement indirect RAM Multiply A and B Divide A by B Decimal adjust acc Byte 2 2 1 1 2 2 1 1 2 2 1 1 1 2 1 1 1 1 2 1 1 1 1 1 Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 4 4 1

1. The destination operand of addition and subtraction operations is accumulator A, the source operand may be #data, Rn, and @Ri. 2. To decrement DPTR, the DEC DPL instruction is available. 3. DA A instruction is valid only if it follows an addition instruction.

Logical Operation Instructions

Mnemonic ANL A,#data ANL A,direct ANL A,Rn ANL A,@Ri ANL direct,A ANL direct,#data ORL A,#data Description AND immediate data to accumulator AND direct byte to accumulator AND register to accumulator AND indirect RAM to accumulator AND accumulator to direct byte AND immediate data to direct byte OR immediate data to accumulator Byte 2 2 1 1 2 3 2 Cycle 1 1 1 1 1 2 1 Page 68 of 73

ORL A,direct ORL A,Rn ORL A,@Ri ORL direct,A ORL direct,#data XRL A,#data XRL A,direct XRL A,Rn XRL A,@Ri XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A

OR direct byte to accumulator OR register to accumulator OR indirect RAM to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive-XOR immediate data to accumulator Exclusive-XOR direct byte to accumulator Exclusive-XOR register to accumulator Exclusive-XOR indirect RAM to accumulator Exclusive-XOR accumulator to direct byte Exclusive-XOR immediate data to direct byte Clear acc Complement acc Rotate acc leftct RAM Rotate acc left through the carry flag Rotate acc right Rotate acc right through the carry flag Swap nibbles within acc

2 1 1 2 3 2 2 1 1 2 3 1 1 1 1 1 1 1

1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1

1. All instructions use A as the destination operand except that the ANL, ORL, and XRL instructions use direct byte as the destination operand.

Boolean Variable Operation Instructions

Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit Jump if carry flag is set Jump if no carry flag Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Byte 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 Cycle 1 1 1 1 1 1 2 2 2 2 1 2 2 2 2 2 2

Branch and jump Instructions

Mnemonic ACALL addr11 Description Absolute subrou ne call,2K range Byte 2 Cycle 2 Page 69 of 73

LCALL addr16 RET RET1 AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR Jz rel JNZ rel CJNE A,#data,rel CJNE A,direct,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ Rn,rel DJNZ direct,rel NOP

Long subrou ne call, 64K range Return from subroutine Return from interrupt Absolute jump Long jump, 64K range Short jump(relative addr,-128~+127) Jump indirect relative to the DPTR Jump if acc is zero Jump if Acc is not zero Compare immediate to Acc and jump if not equal Compare direct to Acc and jump if not equal Compare immediate to register and jump if not equal Compare to indirect RAM and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation

3 1 1 2 2 2 1 2 2 3 3 3 3 2 3 1

2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 1

Contents of the SFRs after reset: Register Name PC ACC B DPTR IE IP SBUF SP TMOD TCON T2CON RCAP2H RCAP2L Reset value 0000H 00H 00H 0000H 0x000000B xx000000B xxxxxxxxB 07H 00H 00H 00H 00H 00H Register Name P0 P1 P2 P3 PCON PSW SCON TH0 TL0 TH1 TL1 TH2 TL2 Reset Value FFH FFH FFH FFH 0xxx0000B 00H 00H 00H 00H 00H 00H 00H 00H

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Appendix C Addressing Modes

Addressing Modes The 8051 is provided with five addressing modes. These are: 1. 2. 3. Immediate addressing. Register Addressing. Index Addressing. 4. Direct Addressing. 5 .Indirect Addressing.

Immediate Addressing Mode If a source operand is part of the instruction instead of the contents of a register or memory location, it represents what is called an immediate operand and is accessed using the immediate addressing mode. Typically, immediate operands represent constant data. In the instruction MOV A,#60H The source operand is an immediate constant 60H (with prefix #), and the destination operand is accumulator A. This instruction moves an immediate data 60H to A.

Direct Addressing Mode The operand in direct addressing mode is an addressable memory location which could be a numeric address or a register name in SFR. The instruction MOV A,60H

Moves the contents of memory location 60H to the accumulator A. if the contents of memory address 60H is a constant value of 50H, the contents of A is 50H after this instruction.

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Register Addressing Mode With the register addressing mode, the operand to be accessed is specified as residing in an internal register of the 8051. 8051 registers are in internal RAM, register name is actually an address of internal data RAM. The register addressing mode uses 3 bits in machine code for representing the selected register. For example, the instruction MOV A,R3

Moves the contents of the register R3 to accumulator A.

Indirect Addressing Mode In indirect addressing mode, the location of operand is pointed by the contents of an index register. 8051 internal registers R0, R1, SP, and DPTR can be used as index registers. For example the instruction: MOV A,@R0

Moves data from the address location where is pointed by the contents of R0 to accumulator.

Index addressing mode Index addressing works identically to the indirect addressing; however, it uses the contents of a base register, DPTR or PC, and the contents of an index register in the generation of the physical address. The physical memory address is obtained by adding the contents of base register (DPTR or PC) to the contents of index register (A). For example:

MOVC A,@A+DPTR Moves data from the ROM location which is addressed by the sum of the contents of A and DPTR to accumulator. MOVC is a data transfer reference to program memory (ROM)

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References

Technical Training and education (MTS51-E051101-EC) URL:http://www.kandh.com.tw URL:http://www.keil.com The 8051 Microcontroller and embedded systems using assembly and C ,Second edition, Mohammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D. McKinlary.

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