Spru 430 e

TMS320C28x CPU and Instruction Set Reference Guide
Literature Number: SPRU430E August 2001 Revised January 2009
Preface
Read This First

About This Manual
This manual describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x 32-bit fixed-point CPU. It also describes emulation features available on these devices. A summary of the chapters and appendixes follows: Chapter 1 Architectural Overview This chapter introduces the C2800 CPU that is at the heart of each TMS320C28x device. The chapter includes a memory map and a high-level description of the memory interface that connects the core with memory and peripheral devices. Central Processing Unit This chapter describes the architecture, registers, and primary functions of the CPU. The chapter includes detailed descriptions of the flag and control bits in the most important CPU registers, status registers ST0 and ST1. Interrupts and Reset This chapter describes the interrupts and how they are handled by the CPU. The chapter also explains the effects of a reset on the CPU and includes discussion of the automatic context save performed by the CPU prior to servicing an interrupt. Pipeline This chapter describes the phases and operation of the instruction pipeline. The chapter is primarily for readers interested in increasing the efficiency of their programs by preventing pipeline delays. Addressing Modes This chapter explains the modes by which the assembly language instructions accept data and access register and memory locations. The chapter includes a description of how addressing-mode information is encoded in opcodes. Assembly Language Instructions This chapter provides summaries of the instruction set and detailed descriptions (including examples) for the instructions. The chapter includes an explanation of how 32-bit accesses are aligned to even addresses.
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
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About This Manual
Chapter 7
Emulation Features This chapter describes the TMS320C28x emulation features that can be used with only a JTAG port and two additional emulation pins. Register Quick Reference This appendix is a concise central resource for information about the status and control registers of the CPU. The chapter includes figures that summarize the bit fields of the registers. C2xLP and C28x Architectural Differences This appendix describes the differences in the architecture of the C2xLP and the C28x. Migration From C2xLP This appendix explains how to migrate code from the C2xLP to the C28x. C2xLP Instruction Set Compatibility This appendix describes the instruction set compatibility with the C2xLP. Migration From C27x to C28x This appendix explains how to migrate code from the C27x to the C28x. Glossary This appendix explains abbreviations, acronyms, and special terminology used throughout this document.
Appendix A
Appendix B
Appendix C Appendix D Appendix E Appendix G
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About This Manual / Notational Conventions
Notational Conventions
This document uses the following conventions:
- The device number TMS320C28x is very often abbreviated as 28x. - Program examples are shown in a special typeface. Here is a sam-
ple line of program code:

PUSH IER
- Portions of an instruction syntax that are in bold should be entered as
shown; portions of a syntax that are in italics are variables indicating information that should be entered. Here is an example of an instruction syntax: MOV ARx, *SP[6bit] MOV is the instruction mnemonic. This instruction has two operands, indicated by ARx and *SP[6bit]. Where the variable x appears, you type a value from 0 to 5; where the 6bit appears, you type a 6-bit constant. The rest of the instruction, including the square brackets, must be entered as shown.
- When braces or brackets enclose an operand, as in {operand}, the oper-
and is optional. If you use an optional operand, you specify the information within the braces; you do not enter the braces themselves. In the following syntax, the operand << shift is optional: MOV ACC, *SP[6bit] {<< shift } MOV ACC, *SP{6bit} {<< shift } For example, you could use either of the following instructions:
MOV ACC, *SP[5] MOV ACC, *SP[5]<< 4
- In most cases, hexadecimal numbers are shown with a subscript of 16. For
example, the hexadecimal number 40 would be shown as 4016. An exception to this rule is a hexadecimal number in a code example; these hexadecimal numbers have the suffix h. For example, the number 40 in the following code is a hexadecimal 40.
MOVB AR0,#40h
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Notational Conventions
Similarly, binary numbers usually are shown with a subscript of 2. For example, the binary number 4 would be shown as 01002. Binary numbers in example code have the suffix b. For example, the following code uses a binary 4.
MOVB AR0,#0100b
- Bus signals and bits are sometimes represented with the following nota-
tions:
Notation Bus(n:m) Description Signals n through m of bus Example PRDB(31:0) represents the 32 signals of the program-read data bus (PRDB). T(3:0) represents the 4 least significant bits of the T register. IER(4) represents bit 4 of the interrupt enable register (IER).
Register(n:m)
Bits n through m of register
Register(n)
Bit n of register
- Concatenated values are represented with the following notation: Notation x:y Description x concatenated with y Example AR1:AR0 is the concatenation of the 16-bit registers AR1 and AR0. AR0 is the low word. AR1 is the high word.
- If a signal is from an active-low pin, the name of the signal is qualified with
an overbar (for example, INT1). If a signal is from an active-high pin or from hardware inside the the device (in which case, the polarity is irrelevant), the name of the signal is left unqualified (for example, DLOGINT).
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Notational Conventions / Related Documentation From Texas Instruments
Related Documentation From Texas Instruments

The following books describe the TMS320C28x DSP and related support tools. The documents are available for downloading on the Texas Instruments website (www.ti.com). TMS320F2801, TMS320F2806, TMS320F2808 Digital Signal Processors (literature number SPRS230) data sheet contains the pinout, signal descriptions, as well as electrical and timing specifications for the F280x devices. TMS320C28x Assembly Language Tools Users Guide (literature number SPRU513) describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. TMS320C28x Optimizing C Compiler Users Guide (literature number SPRU514) describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812 Digital Signal Processors (literature number SPRS174) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages. TMS320x28xx, 28xxx DSP Peripherals Reference Guide (literature number SPRU566) describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices. TMS320C28x Floating Point Unit and Instruction Set Reference Guide (literature number SPRUEO2) describes the CPU architecture, pipeline, instruction set, and interrupts of the C28x floatingpoint DSP.
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vii
Trademarks
Trademarks
320 Hotline On-line is a trademark of Texas Instruments Incorporated. HP-UX is a trademark of Hewlett-Packard Company. IBM and PC are trademarks of International Business Machines Corporation. Intel is a trademark of Intel Corporation. MS-DOS is a registered trademark of Microsoft Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. SunOS is a trademark of Sun Microsystems, Inc. C2xLP, C27x, C28x, TMS320C28x, TMS320F28x, and XDS510 are trademarks of Texas Instruments Incorporated.
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Contents
Contents
1 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Introduces the architecture and memory map of the T320C28x DSP CPU. 1.1 Introduction to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 Compatibility With Other TMS320 CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.2 Switching to C28x Mode From Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.1 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.2 Emulation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3.1 CPU Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.1 Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.2 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4.3 Alignment of 32-Bit Accesses to Even Addresses . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2
1.3 1.4
Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the architecture, registers, and primary functions of the TMS320C28x CPU. 2.1 2.2 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1 Accumulator (ACC, AH, AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.2 Multiplicand Register (XT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3 Product Register (P, PH, PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.4 Data Page Pointer (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.5 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.6 Auxiliary Registers (XAR0XAR7, AR0AR7) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.7 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.8 Return Program Counter (RPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.9 Status Registers (ST0, ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER) . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Status Register (ST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Status Register ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.5.2 Branches, Calls, and Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
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2.3 2.4 2.5
Contents
2.6
2.7 3
2.5.3 Repeating a Single Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiply Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 16-bit X 16-bit Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 32-Bit X 32-Bit Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-39 2-40 2-41 2-41 2-42 2-44
CPU Interrupts and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the TMS320C28x interrupts and how they are handled by the CPU. Also explains the effects of a hardware reset. 3.1 3.2 3.3 CPU Interrupts Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 CPU Interrupt Vectors and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Maskable Interrupts: INT1INT14, DLOGINT, and RTOSINT . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1 CPU Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.2 CPU Interrupt Enable Register (IER) and CPU Debug Interrupt Enable Register (DBGIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Standard Operation for Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.1 INTR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.2 TRAP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.5.3 Hardware Interrupt NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Illegal-Instruction Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Hardware Reset (RS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4 3.5
3.6 3.7 4
Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Describes the phases and operation of the instruction pipeline. 4.1 Pipelining of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 Decoupled Pipeline Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.2 Instruction-Fetch Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.3 Address Counters FC, IC, and PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Visualizing Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Freezes in Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.3.1 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.3.2 Instruction-Not-Available Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Pipeline Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.1 Protection During Reads and Writes to the Same Data-Space Location . . . . 4-12 4.4.2 Protection Against Register Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Avoiding Unprotected Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.5.1 Unprotected Program-Space Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.5.2 An Access to One Location That Affects Another Location . . . . . . . . . . . . . . . 4-16 4.5.3 Write Followed By Read Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.2 4.3
4.4
4.5
Contents
C28x Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Describes the addressing modes of the C28x. 5.1 5.2 5.3 5.4 5.5 5.6 Types of Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Addressing Modes Select Bit (AMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Assembler/Compiler Tracking of AMODE Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Direct Addressing Modes (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Stack Addressing Modes (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.6.1 C28x Indirect Addressing Modes (XAR0 to XAR7) . . . . . . . . . . . . . . . . . . . . . . 5-10 5.6.2 C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7) . . . . . . . . . . . . . . . . 5-12 5.6.3 Circular Indirect Addressing Modes (XAR6, XAR1) . . . . . . . . . . . . . . . . . . . . . . 5-21 Register Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.7.1 32-Bit Register Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.7.2 16-Bit Register Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Data/Program/IO Space Immediate Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Program Space Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 Byte Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Alignment of 32-Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.7
5.8 5.9 5.10 5.11 6
C28x Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Presents summaries of the instruction set, defines special symbols and notations used, and describes each instruction in detail in alphabetical order. 6.1 6.2 Instruction Set Summary (Organized by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Emulation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Explains features supported by the TC2800 CPU for testing and debugging programs. 7.1 7.2 7.3 7.4 Overview of Emulation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Debug Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Execution Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4.2 Real-Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Caution about breakpoints within time-critical interrupt service routines . . . . 7-11 7.4.3 Summary of Stop Mode and Real-Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Aborting Interrupts With the ABORTI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 DT-DMA Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Analysis Breakpoints, Watchpoints, and Counter(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7.1 Analysis Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7.2 Watchpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7.3 Benchmark Counter/Event Counter(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.7.4 Typical Analysis Unit Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
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7.5 7.6 7.7
Contents
7.8
7.9 7.10 A
Data Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 Creating a Data Logging Transfer Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 Accessing the Emulation Registers Properly . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.3 Data Log Interrupt (DLOGINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.4 Examples of Data Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sharing Analysis Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostics and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-23 7-23 7-26 7-27 7-28 7-30 7-31
Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Is a concise, central resource for information about the status and control registers of the TMS320C28x CPU. A.1 A.2 Reset Values of and Instructions for Accessing the Registers . . . . . . . . . . . . . . . . . . . . . A-2 Register Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
C2xLP and C28x Architectural Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Highlights some the architectural differences between C2xLP and C28x, with a focus on registers and memory maps. FB.1 Summary of Architecture Differences Between C2xLP and C28x . . . . . . . . . . . . . . . . . . B-2 B.1.1 Enhancements of the C28x over the C2xLP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 B.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2.1 CPU Register Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B.2.2 Data Page (DP) Pointer Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.2.3 Status Register Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 B.2.4 Register Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 B.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
C2xLP Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Provides guidelines for C2xLP code migration to a C28x device. C.1 C.2 C.3 C.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Recommended Migration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 Mixing C2xLP and C28x Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.1 Boot Code for C28x operating mode initalization . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.2 IER/IFR Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.3 Context Save/Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 Reference Tables for C2xLP Code Migration Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10
C.5 D
C2xLP Instruction Set Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Describes the instruction set compatibility between the C2xLP and the C28x. D.1 D.2 D.3 Condition Tests on Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 C2xLP vs. C28x Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Repeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
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Migration From C27x to C28x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Highlights the architectural differences between C27x and C28x and describes how to migrate your code from C27x to C28x E.1 Architecture Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 E.1.1 Changes to Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 E.1.2 Full Context Save and Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5 E.1.3 B0/B1 Memory Map Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6 E.1.4 C27x Object Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8 Moving to a C28x Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 E.2.1 Caution When Changing OJBMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 Migrating to C28x Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.3.1 Instruction Syntax Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.3.2 Repeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.3.3 Changes to the SUBCU Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14 Compiling C28x Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16
E.2 E.3
E.4 F
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
Contents
xiii
Figures
Figures
11 12 21 22 23 24 25 26 27 28 29 210 211 212 213 31 32 33 34 35 51 52 71 72 73 74 75 76 77 78 79 710 A1 A2 A3 A4
xiv
High-Level Conceptual Diagram of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 TMS320C28x High-Level Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Conceptual Block Diagram of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 C28x Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Individually Accessible Portions of the Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Individually Accessible Halves of the XT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Individually Accessible Halves of the P Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Pages of Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Address Reach of the Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 XAR0 XAR7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 XAR0 XAR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Bit Fields of Status Register (ST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Bit Fields of Status Register 1 (ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication . . . . . . . . . . . 2-42 Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication . . . . . . . . . . . 2-43 Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Debug Interrupt Enable Register (DBGIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Standard Operation for CPU Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction . . . . . . . . . . . . . 3-18 Circular Buffer with AMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Circular Buffer with AMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 JTAG Header to Interface a Target to the Scan Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Stop Mode Execution States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Real-time Mode Execution States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Stop Mode Versus Real-Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Process for Handling a DT-DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 ADDRL (at Data-Space Address 00 083816) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 ADDRH (at Data-Space Address 00 083916) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 REFL (at Data-Space Address 00 084A16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 REFH (at Data-Space Address 00 084B16 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 Valid Combinations of Analysis Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 Status register ST0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Status register ST1, Bits158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Status Register ST1, Bits 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Interrupt flag register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Figures
A5 A6 B1 B2 B3 B4 C1 E1 E2 E3 E4 E5 E6 E7 E8
Interrupt enable register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Debug interrupt enable register (DBGIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 Register Changes From C2xLP to C28x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Direct Addressing Mode Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Status Register Comparison Between C2xLP and C28x . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Memory Map Comparison (See Note A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13 Flow Chart of Recommended Migration Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 C28x Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 Full Context Save/Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5 Code for a Full Context Save/Restore for C28x vs C27x . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6 Mapping of Memory Blocks B0 and B1 on C27x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7 C27x Compatible Mapping of Blocks M0 and M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7 Building a C27x Object File From C27x Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8 Building a C28x Object File From Mixed C27x/C28x Source . . . . . . . . . . . . . . . . . . . . . . . . E-9 Compiling C28x Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16
Contents
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Tables
Tables
11 12 13 21 22 23 24 25 26 27 28 29 210 211 31 32 33 34 35 51 61 62 71 72 73 74 75 76 A1 B1 B2 B3 B4 B5 B6 C1 Compatibility Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Summary of Bus Use During Data-Space and Program-Space Accesses . . . . . . . . . . . . 1-10 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 CPU Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Available Operations for Shifting Values in the Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Product Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Instructions That Affect OVC/OVCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Instructions Affected by the PM Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Instructions Affected by V flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Negative Flag Under Overflow Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Bits Affected by the C Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Instructions That Affect the TC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Instructions Affected by SXM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 Interrupt Vectors and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Requirements for Enabling a Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Register Pairs Saved and SP Positions for Context Saves . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Register Pairs Saved and SP Positions for Context Saves . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Addressing Modes for loc16 or loc32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Instruction Set Summary (Organized by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 14-Pin Header Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Selecting Device Operating Modes By Using TRST, EMU0, and EMU1 . . . . . . . . . . . . . . . 7-5 Interrupt Handling Information By Mode and State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Start Address and DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 End-Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Analysis Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 Reset Values of the Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 C2xLP Product Mode Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 C28x Product Mode Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 Reset Conditions of Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 B0 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 Code to Save Contents Of IMR (IER) And Disabling Lower Priority Interrupts At Beginning Of ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
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Tables
C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 E1 E2 E3
Code to Disable an Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 Code to Enable an Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 Code to Clear the IFR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 Full Context Save/Restore Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 C2xLP and C28x Differences in Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 C2xLP and C28x Differences in Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 C2xLp and C28x Differences in Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12 C2xLP and C28x Differences in Instructions and Registers . . . . . . . . . . . . . . . . . . . . . . . C-13 Code Generation Tools and Syntax Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15 C28x and C2xLP Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 C2xLP Instructions and C28x Equivalent Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Repeatable Instructions for the C2xLP and C28x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9 ST0 Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3 ST1 Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4 Instruction Syntax Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12
Contents
xvii
Examples
Examples
31 41 42 43 44 45 71 72 Typical ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Relationship Between Pipeline and Address Counters FC, IC, and PC . . . . . . . . . . . . . . . 4-6 Diagramming Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Simplified Diagram of Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Conflict Between a Read From and a Write to Same Memory Location . . . . . . . . . . . . . . 4-13 Register Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Initialization Code for Data Logging With Word Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 Initialization Code for Data Logging With End Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
xviii
Chapter 1
Architectural Overview
The TMS320C28xt is one of several fixed-point CPUs in the TMS320 family. The C28xt is source-code and object-code compatible with the C27xt. In addition, much of the code written for the C2xLP CPU can be reassembled to run on a C28x device. The C2xLP CPU is used in all TMS320F24xx and TMS320C20x devices and their derivatives. This document refers to C2xLP as a generic name for the CPU used in these devices. This chapter provides an overview of the architectural structure and components of the C28x CPU.
Topic
1.1 1.2 1.3 1.4
Page
Introduction to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1-1
Introduction to the CPU
1.1 Introduction to the CPU

The CPU is a low-cost 32-bit fixed-point processor. This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The CPU features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture (usable in Von Neumann mode). The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
1.1.1
Compatibility With Other TMS320 CPUs

The C28x CPU features compatibility modes that minimize the migration effort from the C27x and C2xLP CPUs. The operating mode of the device is determined by a combination of the OBJMODE and AMODE bits in status register 1 (ST1) as shown in Table 11. The OBJMODE bit allows you to select between code compiled for a C28x (OBJMODE == 1) and code compiled for a C27x (OBJMODE == 0). The AMODE bit allows you to select between C28x/C27x instruction addressing modes (AMODE == 0) and C2xLP compatible instruction addressing modes (AMODE == 1).
Table 11. Compatibility Modes

OBJMODE C28x Mode C2xLP Source-compatible Mode C27x Object-compatible Mode
AMODE 0 1 0
1 1 0
The C28x is in C27x-compatible mode at reset.
- C28x Mode: In C28x mode, you can take advantage of all the C28x native
features, addressing modes, and instructions. To operate in C28x mode from reset, your code must first set the OBJMODE bit by using the C28OBJ (or SETC OBJMODE) instruction. This book assumes you are operating in C28x mode unless stated otherwise.
1-2
Introduction to the CPU
- C2xLP Source-Compatible Mode: C2xLP source-compatible mode al-
lows you to run C2xLP source code which has been reassembled using the C28x code-generation tools. For more information on operating in this mode and migration from a C2xLP CPU, see Appendices C, D, and E.
- C27x Object-Compatible Mode: At reset, the C28x CPU operates in C27x
object-compatible mode. In this mode, the C28x is 100% object-code and cycle-count compatible with the C27x CPU. For detailed information on operating in C27x object-compatible mode and migrating from the C27x, see Appendix F.
1.1.2
Switching to C28x Mode From Reset

At reset, the C28x CPU is in C27x Object-Compatible Mode (OBJMODE == 0, AMODE == 0) and is 100% compatible with the C27x CPU. To take advantage of the enhanced C28x instruction set, you must instead operate the device in C28x mode. To do this, after a reset your code must first set the OBJMODE bit in ST1 by using the C28OBJ (or SETC OBJMODE) instruction.
1-3
Components of the CPU
1.2 Components of the CPU

As shown in Figure 11, the CPU contains:
- A CPU for generating data- and program-memory addresses; decoding
and executing instructions; performing arithmetic, logical, and shift operations; and controlling data transfers among CPU registers, data memory, and program memory
- Emulation logic for monitoring and controlling various parts and functiona-
lities of the DSP and for testing device operation

- Signals for interfacing with memory and peripherals, clocking and control-
ling the CPU and the emulation logic, showing the status of the CPU and the emulation logic, and using interrupts The CPU does not contain memory, a clock generator, or peripheral devices. For information about interfacing to these items, see the C28x Peripheral Users Guide (literature number SPRU566) and the data sheet that corresponds to your DSP.
Figure 11. High-Level Conceptual Diagram of the CPU

C28x CPU Memory-interface signals CPU Clock and control signals Reset and interrupt signals Emulation logic Emulation signals
1.2.1
Central Processing Unit (CPU)

The CPU is discussed in more detail in Chapter 2, but following is a list of its major features:
- Protected pipeline. The CPU implements an 8-phase pipeline that pre-
vents a write to and a read from the same location from occurring out of order.
- Independent register space. The CPU contains registers that are not
mapped to data space. These registers function as system-control

1-4
registers, math registers, and data pointers. The system-control registers are accessed by special instructions. The other registers are accessed by special instructions or by a special addressing mode (register addressing mode).
- Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arith-
metic and Boolean logic operations.

- Address register arithmetic unit (ARAU). The ARAU generates data-
memory addresses and increments or decrements pointers in parallel with ALU operations.
- Barrel shifter. This shifter performs all left and right shifts of data. It can shift
data to the left by up to 16 bits and to the right by up to 16 bits.

- Multiplier. The multiplier performs 32-bit 32-bit 2s-complement multi-
plication with a 64-bit result. The multiplication can be performed with two signed numbers, two unsigned numbers, or one signed number and one unsigned number.
1.2.2
Emulation Logic
The emulation logic includes the following features. For more details about these features, see Chapter 7, Emulation Features.
- Debug-and-test direct memory access (DT-DMA). A debug host can gain
direct access to the content of registers and memory by taking control of the memory interface during unused cycles of the instruction pipeline.
- Data logging. The emulation logic enables application-initiated transfers
of memory contents between the C28x and a debug host.

- A counter for performance benchmarking - Multiple debug events. Any of the following debug events can cause a
break in program execution:

J J J
A breakpoint initiated by the ESTOP0 or ESTOP1 instruction An access to a specified program-space or data-space location A request from the debug host or other hardware
When a debug event causes the C28x to enter the debug-halt state, the event is called a break event.
- Real-time mode of operation. When the C28x is in this mode and a break
event occurs, the main body of program code comes to a halt, but time-critical interrupts can still be serviced.
Architectural Overview 1-5
1.2.3
Signals
The CPU has four main types of signals:
- Memory-interface signals. These signals transfer data among the CPU,
memory, and peripherals; indicate program-memory accesses and datamemory accesses; and differentiate between accesses of different sizes (16-bit or 32-bit).
- Clock and control signals. These provide clocking for the CPU and the
emulation logic, and they are used to control and monitor the CPU.
- Reset and interrupt signals. These are used for generating a hardware re-
set and interrupts, and for monitoring the status of interrupts.

- Emulation signals. These signals are used for testing and debugging.
1-6
Memory Map
1.3 Memory Map

The C28x uses 32-bit data addresses and 22-bit program addresses. This allows for a total address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space. Memory blocks on all C28x designs are uniformly mapped to both program and data space. Figure 12 shows a high-level view of how addresses are allocated in program space and data space. The memory map in Figure 12 has been divided into the following segments: - On-chip program/data - Reserved - CPU interrupt vectors For specific details about each of the map segments, see the data sheet for your device. See Appendix C for more information on the C2xLP compatible memory space.
1.3.1
CPU Interrupt Vectors

Sixty-four addresses in program space are set aside for a table of 32 CPU interrupt vectors. The CPU vectors can be mapped to the top or bottom of program space by way of the VMAP bit. For more information about the CPU vectors, see Section 3.2, Interrupt Vectors and Priorities on page 3-4. For devices with a peripheral interrupt expansion (PIE) block, the interrupt vectors will reside in the PIE vector table and this memory can be used as program memory.
1-7
Memory Map
Figure 12. TMS320C28x High-Level Memory Map

Program 0000 Vectors in RAM M0 (VMAP = 0) Block M0 1 K 16 3FF 400 Block M1 1 K 16 Block M1 1 K 16 Data Vectors in RAM M0 (VMAP = 0) Block M0 1 K 16 <SP (Reset) Low 64K C2xLP Compatible Data Space
7FF Reserved Reserved
800 9FF 1000
Memory or Peripherals 3F 0000
Memory or Peripherals A000
High 64K C2xLP Compatible Program Space
3F FFFF
Vectors (VMAP = 1)
FFFF FFFF
See the data sheet for your specific device for details of the exact memory map.
1-8
Memory Interface
1.4 Memory Interface

The C28x memory map is accessible outside the CPU by the memory interface, which connects the CPU logic to memories, peripherals, or other interfaces. The memory interface includes separate buses for program space and data space. This means an instruction can be fetched from program memory while data memory is being accessed. The interface also includes signals that indicate the type of read or write being requested by the CPU. These signals can select a specified memory block or peripheral for a given bus transaction. In addition to 16-bit and 32-bit accesses, the C28x supports special byte-access instructions which can access the least significant byte (LSByte) or most significant byte (MSByte) of an addressed word. Strobe signals indicate when such an access is occurring on a data bus.
1.4.1
Address and Data Buses

The memory interface has three address buses: PAB Program address bus. The PAB carries addresses for reads and writes from program space. PAB is a 22-bit bus. Data-read address bus. The 32-bit DRAB carries addresses for reads from data space.
DRAB
DWAB Data-write address bus. The 32-bit DWAB carries addresses for writes to data space. The memory interface also has three data buses: PRDB Program-read data bus. The PRDB carries instructions or data during reads from program space. PRDB is a 32-bit bus. Data-read data bus. The DRDB carries data during reads from data space. PRDB is a 32-bit bus.
DRDB
DWDB Data-/Program-write data bus. The 32-bit DWDB carries data during writes to data space or program space.
1-9
Memory Interface
Table 12 summarizes how these buses are used during accesses.
Table 12. Summary of Bus Use During Data-Space and Program-Space Accesses
Access Type Address Bus PAB

Data Bus PRDB Read from program space Read from data space DRAB PAB DRDB Write to program space Write to data space DWDB DWDB DWAB
A program-space read and a program-space write cannot happen simultaneously because both use the PAB. Similarly, a program-space write and a data-space write cannot happen simultaneously because both use the DWDB. Transactions that use different buses can happen simultaneously. For example, the CPU can read from program space (using PAB and PRDB), read from data space (using DRAB and DRDB), and write to data space (using DWAB and DWDB) at the same time.
1.4.2
Special Bus Operations

Typically, PAB and PRDB are used only for reading instructions from program space, and DWDB is used only for writing data to data space. However, the instructions in Table 13 are exceptions to this behavior. For more details about using these instructions, see Chapter 6, Assembly Language Instructions.
1-10
Memory Interface
Table 13. Special Bus Operations

Instruction PREAD
1.4.3
Alignment of 32-Bit Accesses to Even Addresses

Special Bus Operation This instruction reads a data value rather than an instruction from program space. It then transfers that value to data space or a register. For the read from program space, the CPU places the source address on the program address bus (PAB), sets the appropriate programspace select signals, and reads the data value from the program-read data bus (PRDB). This instruction writes a data value to program space. The value is read from from data space or a register. PWRITE For the write to program space, the CPU places the destination address on the program address bus (PAB), sets the appropriate program-space select signals, and writes the data value to the data-/program-write data bus (DWDB). MAC DMAC QMACL IMACL XMAC XMACD As part of their operation, these instructions multiply two data values, one of which is read from program space. For the read from program space, the CPU places the program-space source address on the program address bus (PAB), sets the appropriate program-space select signals, and reads the program data value from the program read data bus (PRDB).
The C28x CPU expects memory wrappers or peripheral-interface logic to align any 32-bit read or write to an even address. If the address-generation logic generates an odd address, the CPU must begin reading or writing at the previous even address. This alignment does not affect the address values generated by the address-generation logic. Most instruction fetches from program space are performed as 32-bit read operations and are aligned accordingly. However, alignment of instruction fetches are effectively invisible to a programmer. When instructions are stored to program space, they do not have to be aligned to even addresses. Instruction boundaries are decoded within the CPU. You need to be concerned with alignment when using instructions that perform 32-bit reads from or writes to data space.
1-11
1-12
Chapter 2
Central Processing Unit

The central processing unit (CPU) is responsible for controlling the flow of a program and the processing of instructions. It performs arithmetic, Booleanlogic, multiply, and shift operations. When performing signed math, the CPU uses 2s-complement notation. This chapter describes the architecture, registers, and primary functions of the CPU.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Page
CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Status Register ST0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Status Register ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Multiply Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2-1
CPU Architecture
2.1 CPU Architecture

All C28x devices contain a central processing unit (CPU), emulation logic, and signals for interfacing with memory and peripherals. Included with these signals are three address buses and three data buses. Figure 21 shows the major blocks and data paths of the C28x CPU. It does not reflect the actual silicon implementation. The shaded buses are memory-interface buses that are external to the CPU. The operand bus supplies the values for multiplier, shifter, and ALU operations, and the result bus carries the results to registers and memory. The main blocks of the CPU are:
- Program and data control logic. This logic stores a queue of instructions
that have been fetched from program memory.

- Real-Time emulation and visibility - Address register arithmetic unit (ARAU). The ARAU generates ad-
dresses for values that must be fetched from data memory. For a data read, it places the address on the data-read address bus (DRAB); for a data write, it loads the data-write address bus (DWAB). The ARAU also increments or decrements the stack pointer (SP) and the auxiliary registers (XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7).
- Atomic arithmetic logic unit (ALU). The 32-bit ALU performs 2s-com-
plement arithmetic and Boolean logic operations. Before doing its calculations, the ALU accepts data from registers, from data memory, or from the program control logic. The ALU saves results to a register or to data memory.
- Prefetch queue and instruction decode - Address generators for program and data - Fixed-point MPY/ALU. The multiplier performs 32-bit 32-bit 2s-comple-
ment multiplication with a 64-bit result. In conjunction with the multiplier, the 28xx uses the 32-bit multiplicand register (XT), the 32-bit product register (P), and the 32-bit accumulator (ACC). The XT register supplies one of the values to be multiplied. The result of the multiplication can be sent to the P register or to ACC.
- Interrupt processing
2-2
CPU Architecture
Figure 21. Conceptual Block Diagram of the CPU

Program-read data bus, PRDB(0:31) Program address bus, PAB(0:21) Data-read address bus, DRAB(0:31) Program-address generation logic Data-read data bus, DRDB(0:31) Data-read buffer register Address from stack Immediate address Operand bus XAR7 Immediate data Immediate data Registers XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 DP SP ST1 AH:AL PH:PL T:TL IER DBGIER IFR ST0 PC RPC Multiplier, barrel shifter, and ALU MUX MUX Program control logic
ARAU
Result bus BUS RESULT Data-write buffer register Data-/program-write data bus, DWDB(0:31)
Data-write address bus, DWAB(0:31)
2-3
CPU Registers
2.2 CPU Registers

Table 21 lists the main CPU registers and their values after reset. Sections 2.2.1 through 2.2.10 describe the registers in more detail. Figure 22 shows the registers.
Table 21. CPU Register Summary

Register ACC AH AL XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 Size 32 bits 16 bits 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits Description Accumulator High half of ACC Low half of ACC Auxiliary register 0 Auxiliary register 1 Auxiliary register 2 Auxiliary register 3 Auxiliary register 4 Auxiliary register 5 Auxiliary register 6 Auxiliary register 7 Low half of XAR0 Low half of XAR1 Low half of XAR2 Low half of XAR3 Low half of XAR4 Low half of XAR5 Low half of XAR6 Low half of XAR7 Value After Reset 0x00000000 0x0000 0x0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
2-4
CPU Registers
Table 21. CPU Register Summary (Continued)

Register DP IFR IER Size 16 bits 16 bits 16 bits Description Data-page pointer Interrupt flag register Interrupt enable register Value After Reset 0x0000 0x0000 0x0000 (INT1 to INT14, DLOGINT, RTOSINT disabled) 0x0000 (INT1 to INT14, DLOGINT, RTOSINT disabled) 0x00000000 0x0000 0x0000 0x3F FFC0 0x00000000 0x0400 0x0000 0x080B
DBGIER
16 bits
Debug interrupt enable register Product register High half of P Low half of P Program counter Return program counter Stack pointer Status register 0 Status register 1
P PH PL PC RPC SP ST0 ST1
32 bits 16 bits 16 bits 22 bits 22 bits 16 bits 16 bits 16 bits
XT T TL
32 bits 16 bits 16 bits
Multiplicand register High half of XT Low half of XT
0x00000000 0x0000 0x0000
Reset value shown is for devices without the VMAP signal and MOM1MAP signal pinned out. On these devices both of these signals are tied high internal to the device.
2-5
CPU Registers
Figure 22. C28x Registers

T[16] PH[16] AH[16] TL[16] PL[16] AL[16] XT[32] P[32] ACC[32]
SP[16]
DP[16] AR0H[16] AR1H[16] AR2H[16] AR3H[16] AR4H[16] AR5H[16] AR6H[16] AR7H[16] 6/7-bit offset AR0[16] AR1[16] AR2[16] AR3[16] AR4[16] AR5[16] AR6[16] AR7[16] PC[22] RPC[22] XAR0[32] XAR1[32] XAR2[32] XAR3[32] XAR4[32] XAR5[32] XAR6[32] XAR7[32]
ST0[16] ST1[16]
IER[16] DBGIER[16] IFR[16]
A 6-bit offset is used when operating in C28x mode or C27x object-compatible mode. A 7-bit offset is used when operating in C2xLP source-compatible mode. The least significant bit of the DP is ignored when operating in this mode.
2.2.1
Accumulator (ACC, AH, AL)

The accumulator (ACC) is the main working register for the device. It is the destination for all ALU operations except those which operate directly on memory or registers. ACC supports single-cycle move, add, subtract, and
2-6
CPU Registers
compare operations from 32-bit-wide data memory. It can also accept the 32-bit result of a multiplication operation. The halves and quarters of the ACC can also be accessed (see Figure 23). ACC can be treated as two independent 16-bit registers: AH (high 16 bits) and AL (low 16 bits). The bytes within AH and AL can also be accessed independently. Special byte-move instructions load and store the most significant byte or least significant byte of AH or AL. This enables efficient byte packing and unpacking.
Figure 23. Individually Accessible Portions of the Accumulator

AH ACC AH.MSB AH.LSB AL.MSB AL.LSB AL
AH = ACC (31:16) AH.MSB = ACC (31:24) AH.LSB = ACC (23:16)
AL = ACC (15:0) AL.MSB = ACC (15:8) AL.LSB = ACC (7:0)
The accumulator has the following associated status bits. For the details on these bits, see section 2.3, Status Register ST0.
-
Overflow mode bit (OVM) Sign-extension mode bit (SXM) Test/control flag bit (TC) Carry bit (C) Zero flag bit (Z) Negative flag bit (N) Latched overflow flag bit (V) Overflow counter bits (OVC)
Table 22 shows the ways to shift the content of AH, AL, or ACC.
2-7
CPU Registers
Table 22. Available Operations for Shifting Values in the Accumulator

Register ACC Shift Direction Left Shift Type Logical Rotation Right Arithmetic Instruction LSL or LSLL ROL SFR with SXM = 1 or ASRL SFR with SXM = 0 or LSRL ROR LSL ASR LSR
Logical
Rotation AH or AL Left Right Logical Arithmetic Logical
2.2.2
Multiplicand Register (XT)

The multiplicand register (XT register) is used primarily to store a 32-bit signed integer value prior to a 32-bit multiply operation. The lower 16-bit portion of the XT register is referred to as the TL register. This register can be loaded with a signed 16-bit value that is automatically sign-extended to fill the 32-bit XT register. The upper 16-bit portion of the XT register is referred to as the T register. The T register is mainly used to store a 16-bit integer value prior to a 16-bit multiply operation. The T register is also used to specify the shift value for some shift operations. In this case, only a portion of the T register is used, depending on the instruction. For example:
ASR AX, T performs an arithmetic shift right based on the four least significant bits of T: T(3:0) = 0...15 performs an arithmetic shift right by the five least significant bits of T: T(4:0) 0...31
ASRL ACC, T
For these operations, the most significant bits of T are ignored.

2-8
CPU Registers
Figure 24. Individually Accessible Halves of the XT Register

T = XT(16:31) XT TL = XT(15:0)
2.2.3
Product Register (P, PH, PL)

The product register (P register) is typically used to hold the 32-bit result of a multiplication. It can also be loaded directly from a 16- or 32-bit data-memory location, a 16-bit constant, the 32-bit ACC, or a 16-bit or a 32-bit addressable CPU register. The P register can be treated as a 32-bit register or as two independent 16-bit registers: PH (high 16 bits) and PL (low 16 bits); see Figure 25.
Figure 25. Individually Accessible Halves of the P Register

PH = P(31:16) P PL = P(15:0)
When some instructions access P, PH, or PL, all 32-bits are copied to the ALUshifter block, where the barrel shifter may perform a left shift, a right shift, or no shift. The action of the shifter for these instructions is determined by the product shift mode (PM) bits in status register ST0. Table 23 shows the possible PM values and the corresponding product shift modes. When the barrel shifter performs a left shift, the low order bits are filled with zeros. When the shifter performs a right shift, the P register value is sign extended. Instructions that use PH or PL as operands ignore the product shift mode. For a complete list of instructions affected by PM bits, see Table 25 on page 2-20.
2-9
CPU Registers
Table 23. Product Shift Modes

PM Value 0002 0012 0102 0112 1002 1012 1102 1112 Product Shift Mode Left shift by 1 No shift Right shift by 1 Right shift by 2 Right shift by 3 Right shift by 4 (if AMODE = 1, left 4) Right shift by 5 Right shift by 6
2.2.4
Data Page Pointer (DP)

In the direct addressing modes, data memory is addressed in blocks of 64 words called data pages. The lower 4M words of data memory consists of 65 536 data pages labeled 0 through 65 535, as shown in Figure 26. In DP direct addressing mode, the 16-bit data page pointer (DP) holds the current data page number. You change the data page by loading the DP with a new number. For information about the direct addressing modes, see section 5.4 on page 5-8.
2-10
CPU Registers
Figure 26. Pages of Data Memory

Data page 00 0000 0000 0000 00 . . . 00 0000 0000 0000 00 00 0000 0000 0000 01 . . . 00 0000 0000 0000 01 00 0000 0000 0000 10 . . . 00 0000 0000 0000 10 . . . . . . 11 1111 1111 1111 11 . . . 11 1111 1111 1111 11 Offset 00 0000 . . . 11 1111 00 0000 . . . 11 1111 00 0000 . . . 11 1111 . . . . . . 00 0000 . . . 11 1111 Page 0: Data memory 0000 00000000 003F
Page 1:
0000 00400000 007F
Page 2:
0000 00800000 00BF
. . . . . .
. . . . . .
Page 65 535: 003F FFC0003F FFFF
Data memory above 4M words is not accessible using the DP. When operating in C2xLP source-compatible mode, a 7-bit offset is used and the least significant bit of the DP register is ignored. See Appendix C for more details.
2.2.5
Stack Pointer (SP)

The stack pointer (SP) enables the use of a software stack in data memory. The stack pointer has only 16 bits and can only address the low 64K of data space (see Figure 27). When the SP is used, the upper six bits of the 32-bit address are forced to 0. (For information about addressing modes that use the SP, see section 5.5 on page 5-9.). After reset, SP points to address 0000 040016.
2-11
CPU Registers
Figure 27. Address Reach of the Stack Pointer

Data memory Range accessible by way of SP
0000 00000000 FFFF
Range not accessible by way of SP
0001 0000FFFF FFFF
The operation of the stack is as follows:

- The stack grows from low memory to high memory. - The SP always points to the next empty location in the stack. - At reset, the SP is initialized, so that it points to address 0000 040016. - When 32-bit values are saved to the stack, the least significant 16 bits are
saved first, and the most significant 16 bits are saved to the next higher address (little endian format).
- When 32-bit operations read or write a 32-bit value, the C28x CPU expects
the memory wrapper or peripheral-interface logic to align that read or write to an even address. For example, if the SP contains the odd address 0000 008316, a 32-bit read operation reads from addresses 0000 008216 and 0000 008316.
- The SP overflows if its value is increased beyond FFFF16 or decreased
below 000016. When the SP increases past FFFF16, it counts forward from 000016. For example, if SP = FFFE16 and an instruction adds 3 to the SP, the result is 000116. When the SP decreases past 000016, it counts backward from FFFF16. For example, if SP = 000216 and an instruction subtracts 4 from SP, the result is FFFE16.
- When values are being saved to the stack, the SP is not forced to align with
even or odd addresses. Alignment is forced by the memory wrapper or peripheral-interface logic.
2.2.6
Auxiliary Registers (XAR0XAR7, AR0AR7)

The CPU provides eight 32-bit registers that can be used as pointers to memory or as general-purpose registers (see Section 5.6, Indirect Addressing
2-12
CPU Registers
Modes, on page 5-10 . The auxiliary registers are: XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7. Many instructions allow you to access the 16 LSBs of XAR0XAR7. As shown in Figure 28, the 16 LSBs of the auxiliary registers are referred to as AR0AR7. AR0AR7 can be used as general purpose registers for loop control and for efficient 16-bit comparisons. When accessing AR0AR7, the upper 16 bits of the register (known as AR0H AR7H) may or may not be modified, depending on the instruction used (see Chapter 6 for information on the behavior of particular instructions). AR0H AR7H are accessed only as part of XAR0XAR7 and are not individually accessible.
Figure 28. XAR0 XAR7 Registers

ARnH = XARn(31:16) XARn(31:0)
n = number 0 through 7
ARn = XARn(15:0)
For ACC operations, all 32 bits are valid (@XARn). For 16-bit operations, the lower 16 bits are used and upper 16 bits are ignored (@ARn). XAR0 XAR7 can also be used by some instructions to point to any value in program memory; see Section 5.6, Indirect Addressing Modes. Many instructions allow you to access the 16 least significant bits (LSBs) of XAR0XAR7. As shown in Figure 29, 16 LSBs of XAR0XAR7 are known as one auxiliary register of AR0AR7.
Figure 29. XAR0 XAR7

AR0 = XAR0(15:0) XAR0(32:0)
AR7 = XAR7(15:0) XAR7(32:0)
2-13
CPU Registers
2.2.7
Program Counter (PC)

When the pipeline is full, the 22-bit program counter (PC) always points to the instruction that is currently being processed the instruction that has just reached the decode 2 phase of the pipeline. Once an instruction reaches this phase of the pipeline, it cannot be flushed from the pipeline by an interrupt. It is executed before the interrupt is taken. The pipeline is discussed in Chapter 4.
2.2.8
Return Program Counter (RPC)

When a call operation is performed using the LCR instruction, the return address is saved in the RPC register and the old value in the RPC is saved on the stack (in two 16-bit operations). When a return operation is performed using the LRETR instruction, the return address is read from the RPC register and the value on the stack is written into the RPC register (in two 16-bit operations). Other call instructions do not use the RPC register. For more information, see the instructions in Chapter 6.
2.2.9
Status Registers (ST0, ST1)

The C28x has two status registers, ST0 and ST1, which contain various flag bits and control bits. These registers can be stored into and loaded from data memory, enabling the status of the machine to be saved and restored for subroutines. The status bits have been organized according to when the bit values are modified in the pipeline. Bits in ST0 are modified in the execute phase of the pipeline; bits in ST1 are modified in the decode 2 phase. (For details about the pipeline, see Chapter 4.) The status bits are described in detail in sections 2.3 (ST0) and 2.4 (ST1). Also, ST0 and ST1 are included in Appendix A, Register Quick Reference.
2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER)

The C28x CPU has three registers dedicated to the control of interrupts:
- Interrupt flag register (IFR) - Interrupt enable register (IER) - Debug interrupt enable register (DBGIER)
These registers handle interrupts at the CPU level. Devices with a peripheral interrupt expansion (PIE) block will have additional interrupt control as part of the PIE module. The IFR contains flag bits for maskable interrupts (those that can be enabled and disabled with software). When one of these flags is set, by hardware or
2-14
CPU Registers
software, the corresponding interrupt will be serviced if it is enabled. You enable or disable a maskable interrupt with its corresponding bit in the IER. The DBGIER indicates the time-critical interrupts that will be serviced (if enabled) while the DSP is in real-time emulation mode and the CPU is halted. The C28x CPU interrupts and the interrupt-control registers are described in detail in Chapter 3, Interrupts. Also, the IFR, IER, and DBGIER are included in Appendix A, Register Quick Reference.
2-15
Status Register (ST0)
2.3 Status Register (ST0)

The following figure shows the bit fields of status register (ST0). All of these bit fields are modified in the execute phase of the pipeline. Detailed descriptions of these bits follow the figure.
Figure 210. Bit Fields of Status Register (ST0)

15 OVC/OVCU
R/W-00 0000
10
9 PM
R/W0
6 V
RW0
5 N
RW0
4 Z
RW0
3 C
RW0
2 TC
RW0
1 OVM
RW0
0 SXM
RW0

Note: R = Read access; W = Write access; value following dash () is value after reset.
OVC/OVCU Bits1510
Overflow counter. The overflow counter behaves differently for signed and unsigned operations.
For signed operations, the overflow counter is a 6-bit signed counter with a range of 32 to 31. When overflow mode is off (OVM = 0), ACC overflows normally, and OVC keeps track of overflows. When overflow mode is on (OVM = 1) and an overflow occurs in ACC, the OVC is not affected. Instead, the CPU automatically fills ACC with a positive or negative saturation value (see the description for OVM on page 2-32). When ACC overflows in the positive direction (from 7FFF FFFF16 to 8000 000016 ), the OVC is incremented by 1. When ACC overflows in the negative direction (from 8000 000016 to 7FFF FFFF16 ) the OVC is decremented by 1. The increment or decrement is performed as the overflow affects the V flag. For unsigned operations (OVCU), the counter increments for ADD when a Carry is generated and decrements for a SUB when a Borrow is generated (similar to a carry counter). If OVC increments past its most positive value, 31, the counter wraps around to 32. If OVC decrements past its most negative value, 32, the counter wraps around to 31. At reset, OVC is cleared. OVC is not affected by overflows in registers other than ACC and is not affected by compare instructions (CMP and CMPL). The table that follows explains how OVC may be affected by the saturate accumulator (SAT ACC) instruction.
Table 24 lists the instructions affecting OVC/OVCU. See the instruction set in Chapter 6 for a complete description of each instruction.
2-16
Table 24. Instructions That Affect OVC/OVCU

Signed Addition Instructions ADD ADD ADD ADD ACC,loc16 << shift ACC,#16bit << shift ACC,loc16 << T loc16,#16bitSigned Effect on OVC/OVCU if(OVM == 0) Inc OVC on +ve signed overflow
ADDB ACC,#8bit ADDCL ACC,loc32 ADDCU ACC,loc16 ADDL ACC,loc32 ADDL loc32,ACC ADDU ACC,loc16 DMAC ACC:P,loc32,*XAR7/++ INC MAC MAC loc16 P,loc16,*XAR7/++ P,loc16,0:pma
MOVA T,loc16 MOVAD T,loc16 MPYA P,loc16,#16bit MPYA P,T,loc16 QMACL P,loc32,*XAR7/++ QMPYAL P,XT,loc32 SQRA loc16 XMAC P,loc16,*(pma) XMACD P,loc16,*(pma) Signed Subtraction Instructions DEC loc16 Effect on OVC/OVCU if(OVM == 0) overflow Dec OVC on ve signed
MOVS T,loc16
2-17
Table 24. Instructions That Affect OVC/OVCU (Continued)

Signed Addition Instructions MPYS P,T,loc16 QMPYSL P,XT,loc32 SBBU ACC,loc16 SQRS loc16 SUB SUB SUB ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T Effect on OVC/OVCU
SUBB ACC,#8bit SUBBL ACC,loc32 SUBL ACC,loc32 SUBL loc32,ACC SUBRL loc32,ACC SUBU ACC,loc16 SUBUL ACC,loc32 SUBUL P,loc32 Unsigned Instructions ADDUL ACC,loc32 ADDUL P,loc32 IMPYAL P,XT,loc32 IMACL P,loc32,*XAR7/++ Misc Instructions SAT ACC Effect on OVC/OVCU if(OVC > 0) Saturate +ve if(OVC < 0) Saturate ve OVC = 0 SAT64 ACC:P ZAPA ZAP MOV OVC OVC,loc16 OVC = [loc16(15:10)] OVC = 0 Effect on OVC/OVCU Inc OVC/OVCU on unsigned carry
2-18
Table 24. Instructions That Affect OVC/OVCU (Continued)

Signed Addition Instructions MOVU OVC,loc16 Condition OVC = 0 OVC > 0 OVC < 0 Operation Performed by SAT ACC Instruction Leave ACC and OVC unchanged. Saturate ACC in the positive direction (fill ACC with 7FFF FFFF16), and clear OVC. Saturate ACC in the negative direction (fill ACC with 8000 000016), and clear OVC. Product shift mode bits. This 3-bit value determines the shift mode for any output operation from the product (P) register. The shift modes are shown in the following table. The output can be to the ALU or to memory. All instructions that are affected by the product shift mode will sign extend the P register value during a right shift operation. At reset, PM is cleared (left shift by 1 bit is the default). PM is summarized as follows: 000 001 010 011 100 101 Left shift by 1. During the shift, the low-order bit is zero filled. At reset, this mode is selected. No shift Right shift by 1. During the shift, the lower bits are lost, and the shifted value is sign extended. Right shift by 2. During the shift, the lower bits are lost, and the shifted value is sign extended. Right shift by 3. During the shift, the lower bits are lost, and the shifted value is sign extended. Right shift by 4. During the shift, the lower bits are lost, and the shifted value is sign extended. Note, if AMODE = 1, then 101 is a left shift by 4. Right shift by 5. During the shift, the lower bits are lost, and the shifted value is sign extended. Right shift by 6. During the shift, the lower bits are lost, and the shifted value is sign extended. Effect on OVC/OVCU OVC = [loc16(5:0)]
PM Bits 97
110 111
Note:
For performing unsigned arithmetic, you must use a product shift of 0 (PM = 001) to avoid sign extension and generation of incorrect results.
Table 25 lists instructions that are affected by the PM bits. See the instruction set in chapter 6 for a complete description of each instruction.
Central Processing Unit 2-19
Table 25. Instructions Affected by the PM Bits

Instruction
CMPL ACC,P << PM DMAC ACC:P,loc32,*XAR7/++
Effect of PM
flags set on(ACC P << PM) ACC = ACC + MSW*MSW << PM P = P + LSW*LSW << PM
IMACL P,loc32,*XAR7/++ IMPYAL P,XT,loc32 IMPYL P,XT,loc32 IMPYSL P,XT,loc32
P = ([loc32] * Prog[*XAR7/++]) << PM P = (XT * [loc32]) << PM P = (XT *[loc32]) << PM ACC = ACC P unsigned P = (XT * [loc32]) << PM
IMPYXUL P,XT,loc32 MAC MAC MOV P,loc16,*XAR7/++ P,loc16,0:pma loc16,P
P = (XT sign * [loc32]uns) << PM ACC = ACC + P << PM ACC = ACC + P << PM [loc16] = low(P << PM) ACC = ACC + P << PM ACC = ACC + P << PM [loc16] = high(P << PM) ACC = P << PM ACC = ACC P << PM ACC = ACC + P << PM ACC = ACC + P << PM ACC = ACC P << PM ACC = ACC + P << PM ACC = ACC + P << PM ACC = ACC + P << PM ACC = ACC P << PM ACC = ACC + P << PM ACC = ACC P << PM ACC = ACC + P << PM ACC = ACC + P << PM
MOVA T,loc16 MOVAD T,loc16 MOVH loc16,P MOVP T,loc16 MOVS T,loc16 MPYA P,loc16,#16bit MPYA P,T,loc16 MPYS P,T,loc16 QMACL P,loc32,*XAR7 QMACL P,loc32,*XAR7++ QMPYAL P,XT,loc32 QMPYSL P,XT,loc32 SQRA loc16 SQRS loc16 XMAC P,loc16,*(pma) XMACD P,loc16,*(pma)
2-20
V Bit 6
Overflow flag. If the result of an operation causes an overflow in the register holding the result, V is set and latched. If no overflow occurs, V is not modified. Once V is latched, it remains set until it is cleared by reset or by a conditional branch instruction that tests V. Such a conditional branch clears V regardless of whether the tested condition (V = 0 or V = 1) is true. An overflow occurs in ACC (and V is set) if the result of an addition or subtraction does not fit within the signed numerical range 231 to (+231 1), or 8000 000016 to 7FFF FFFF16. An overflow occurs in AH, AL, or another 16-bit register or data-memory location if the result of an addition or subtraction does not fit within the signed numerical range 215 to (+215 1), or 800016 to 7FFF16. The instructions CMP, CMPB and CMPL do not affect the state of the V flag. Table 26 lists the instructions that are affected by V flag. See Chapter 6 for more details on instructions.
V can be summarized as follows: 0 V has been cleared.

1 An overflow has been detected, or V has been set.
Table 26. Instructions Affected by V flag

Instruction ABS ACC Description if(ACC == 0x8000 0000) V = 1 if(ACC == 0x8000 0000) V = 1 V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow
ABSTC ACC ADD ADD ADD ADD ADD ADD ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T AX,loc16 loc16,#16bitSigned loc16,AX
ADDB ACC,#8bit ADDB AX,#8bitSigned ADDCL ACC,loc32 ADDCU ACC,loc16 ADDL ACC,loc32 ADDL loc32,ACC ADDU ACC,loc16 ADDUL ACC,loc32
2-21
Table 26. Instructions Affected by V flag (Continued)

Instruction ADDUL P,loc32 B BF DEC 16bitOff,COND 16bitOff,COND loc16 Description V = 1 on signed overflow V = 0 if tested V = 0 if tested V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow if((AX [loc16]) < 0) V = 1 if((ACC [loc32]) < 0) V = 1 if((AX [loc16]) > 0) V = 1 if((ACC [loc32]) > 0) V = 1 V = 0 if tested V = 1 on signed overflow V = 1 on signed overflow V = 0 if tested V = 0 if tested V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow if(ACC == 0x8000 0000) V = 1 if(AX == 0x8000) V = 1 if(ACC:P == 0x80....00) V = 1
DMAC ACC:P,loc32,*XAR7/++ IMACL P,loc32,*XAR7/++ IMPYAL P,XT,loc32 IMPYSL P,XT,loc32 INC MAC MAC MAX loc16 P,loc16,*XAR7/++ P,loc16,0:pma AX,loc16
MAXL ACC,loc32 MIN AX,loc16
MINL ACC,loc32 MOV loc16,AX,COND
MOVA T,loc16 MOVAD T,loc16 MOVB loc16,#8bit,COND MOVL loc32,ACC,COND MOVS T,loc16 MPYA P,loc16,#16bit MPYA P,T,loc16 MPYS P,T,loc16 NEG NEG ACC AX
NEG64 ACC:P
2-22

Instruction NEGTC ACC Description if(TC == 1) if(ACC == 0x8000 0000) V = 1 QMACL P,loc32,*XAR7/++ QMPYAL P,XT,loc32 QMPYSL P,XT,loc32 SAT ACC V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow if(OVC == 0) V = 0 else V = 1 if(OVC == 0) V = 0 else V = 1 V = 0 if tested V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 1 on signed overflow V = 0 if tested V = 0 if tested V = 1 on signed overflow
SAT64 ACC:P SB 8bitOff,COND
SBBU ACC,loc16 SQRA loc16 SQRS loc16 SUB SUB SUB SUB SUB ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T AX,loc16 loc16,AX
SUBB ACC,#8bit SUBBL ACC,loc32 SUBL ACC,loc32 SUBL loc32,ACC SUBR loc16,AX SUBRL loc32,ACC SUBU ACC,loc16 SUBUL ACC,loc32 SUBUL P,loc32 XB pma,COND
XCALL pma,COND XMAC P,loc16,*(pma)
2-23

Instruction XMACD P,loc16,*(pma) XRETC COND Description
V = 1 on signed overflow
V = 0 if tested
N Bit 5
Negative flag. During certain operations, N is set if the result of the operation is a negative number or cleared if the result is a positive number. At reset, N is cleared. Results in ACC are tested for the negative condition. Bit 31 of ACC is the sign bit. If bit 31 is a 0, ACC is positive; if bit 31 is a 1, ACC is negative. N is set if a result in ACC is negative or cleared if a result is positive. Results in AH, AL, and other 16-bit registers or data-memory locations are also tested for the negative condition. In these cases bit 15 of the value is the sign bit (1 indicates negative, 0 indicates positive). N is set if the value is negative or cleared if the value is positive. The TEST ACC instruction sets N if the value in ACC is negative. Otherwise the instruction clears N. As shown in Table 27, under overflow conditions, the way the N flag is set for compare operations is different from the way it is set for addition or subtraction operations. For addition or subtraction operations, the N flag is set to match the most significant bit of the truncated result. For compare operations, the N flag assumes infinite precision. This applies to operations whose result is loaded to ACC, AH, AL, another register, or a data-memory location.

Table 27. Negative Flag Under Overflow Conditions
A B (A B) Subtraction N=1 Compare N=0 Pos Neg Neg (due to overflow in positive direction)

Neg Pos Pos (due to overflow in negative direction) N=0 N=1
For 32-bit data: Pos = Positive number from 0000 000016 to 7FFF FFFF16 Neg = Negative number from 8000 000016 to FFFF FFFF16 For 16-bit data: Pos = Positive number from 000016 to 7FFF16 Neg = Negative number from 800016 to FFFF16 The compare instructions are CMP, CMPB, CMPL, MIN, MAX, MINL, and MAXL.
N can be summarized as follows: 0 The tested number is positive, or N has been cleared.
1 The tested number is negative, or N has been set.
2-24
Z Bit 4
Zero flag. Z is set if the result of certain operations is 0 or is cleared if the result is nonzero. This applies to results that are loaded into ACC, AH, AL, another register, or a data-memory location. At reset, Z is cleared. The TEST ACC instruction sets Z if the value in ACC is 0. Otherwise, it clears Z.
Z can be summarized as follows: 0 The tested number is nonzero, or Z has been cleared.
1 The tested number is 0, or Z has been set.
C Bit 3
Carry bit. This bit indicates when an addition or increment generates a carry or when a subtraction, compare, or decrement generates a borrow. It is also affected by rotate operations on ACC and barrel shifts on ACC, AH, and AL. During additions/increments, C is set if the addition generates a carry; otherwise C is cleared. There is one exception: If you are using the ADD instruction with a shift of 16, the ADD instruction can set C but cannot clear C. During subtractions/decrements/compares, C is cleared if the subtraction generates a carry; otherwise C is set. There is one exception: if you are using the SUB instruction with a shift of 16, the SUB instruction can clear C but cannot set C. This bit can be individually set and cleared by the SETC C instruction and CLRC C instruction, respectively. At reset, C is cleared.
C can be summarized as follows: 0 A subtraction generated a borrow, an addition did not generate a carry, or C has
1 been cleared. Exception: An ADD instruction with a shift of 16 cannot clear C. An addition generated a carry, a subtraction did not generate a borrow, or C has been set. Exception: A SUB instruction with a shift of 16 cannot set C.
Table 28 lists the bits that are affected by the C bit. For more information on instructions, see Chapter 6.
Table 28. Bits Affected by the C Bit

Instruction ABS ACC Affect of or Affect on C C=0 C=0 C = 1 on carry else C = 0 if(shift == 16) C = 1 on carry if(shift != 16) C = 1 on carry else C = 0
ABSTC ACC ADD ADD ACC,#16bit << shift ACC,loc16 << shift
2-25
Table 28. Bits Affected by the C Bit (Continued)

Instruction ADD ADD ADD ADD ACC,loc16 << T AX,loc16 loc16,#16bitSigned loc16,AX Affect of or Affect on C C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 ACC = ACC + [loc32] + C C = 1 on carry else C = 0 ADDCU ACC,loc16 ACC = ACC + [loc16] + C C = 1 on carry else C = 0 ADDL ACC,loc32 ADDL loc32,ACC ADDU ACC,loc16 ADDUL ACC,loc32 ADDUL P,loc32 ASR ASR AX,1..16 AX,T C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = AX(bit(shift1)) if(T == 0) C = 0 else C = AX(bit(T1)) ASR64 ACC:P,1..16 ASR64 ACC:P,T C = P(bit(shift1)) if(T == 0) C = 0 else C = P(bit(T1)) ASRL ACC,T if(T == 0) C = 0 else C = ACC(bit(T1)) B BF 16bitOff,COND 16bitOff,COND C bit used as test condition C bit used as test condition C=0 C = 0 on borrow else C = 1
ADDB ACC,#8bit ADDB AX,#8bitSigned ADDCL ACC,loc32
CLRC C CMP AX,loc16
2-26

Instruction CMP loc16,#16bitSigned Affect of or Affect on C for([loc16] 16bitSigned) C = 0 on borrow else C = 1 CMPB AX,#8bit CMPL ACC,loc32
C = 0 on borrow else C = 1
for(ACC [loc32]) C = 0 on borrow else C = 1
CMPL ACC,P << PM
for(ACC P << PM) C = 0 on borrow else C = 1
DEC
loc16+
C = 0 on borrow else C = 1 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 0 on borrow else C = 1 C = 1 on carry else C = 0 C = ACC(bit(32shift)) if(T == 0) C = 0 else C = ACC(bit(32T))
DMAC ACC:P,loc32,*XAR7/++ IMACL P,loc32,*XAR7/++ IMPYAL P,XT,loc32 IMPYSL P,XT,loc32 INC LSL LSL loc16 ACC,1..16 ACC,T
LSL LSL
AX,1..16 AX,T
C = AX(bit(16shift)) if(T == 0) C = 0 else C = AX(bit(16T))
LSL64 ACC:P,1..16 LSL64 ACC:P,T
C = ACC(bit(32shift)) if(T == 0) C = 0 else C = ACC(bit(32T))
LSLL ACC,T
if(T == 0) C = 0 else C = ACC(bit(32T))
LSR LSR
AX,1..16 AX,T
C = AX(bit(shift1)) if(T == 0) C = 0 else C = AX(bit(T1))
LSR64 ACC:P,1..16
C = P(bit(shift1))
2-27

Instruction LSR64 ACC:P,T Affect of or Affect on C if(T == 0) C = 0 else C = P(bit(T1)) LSRL ACC,T if(T == 0) C = 0 else C = ACC(bit(T1)) MAC MAC MAX P,loc16,*XAR7/++ P,loc16,0:pma AX,loc16 C = 1 on carry else C = 0 C = 1 on carry else C = 0 for(AX [loc16]) C = 0 on borrow else C = 1 MAXL ACC,loc32 for(ACC [loc32]) C = 0 on borrow else C = 1 MIN AX,loc16 for(AX [loc16]) C = 0 on borrow else C = 1 MINL ACC,loc32 for(ACC [loc32]) C = 0 on borrow else C = 1 MOV loc16,AX,COND C bit used as test condition C = 1 on carry else C = 0 C = 1 on carry else C = 0 C bit used as test condition C bit used as test condition C = 0 on borrow else C = 1 C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 0 on borrow else C = 1 if( ACC == 0) C = 1 else C = 0 NEG AX if(AX == 0) C = 1 else C = 0 NEG64 ACC:P if( ACC:P == 0) C = 1 else C = 0
MOVA T,loc16 MOVAD T,loc16 MOVB loc16,#8bit,COND MOVL loc32,ACC,COND MOVS T,loc16 MPYA P,loc16,#16bit MPYA P,T,loc16 MPYS P,T,loc16 NEG ACC
2-28

Instruction NEGTC ACC Affect of or Affect on C if(TC == 1) if( ACC == 0) C = 1 else C = 0 QMACL P,loc32,*XAR7/++ QMPYAL P,XT,loc32 QMPYSL P,XT,loc32 ROL ROR SAT ACC ACC ACC C = 1 on carry else C = 0 C = 1 on carry else C = 0 C = 0 on borrow else C = 1 C < (ACC << 1) < C(before) C(before) > (ACC >> 1) > C C=0 C=0 C bit used as test condition ACC = ACC ([loc16] + ~C) C = 0 on borrow else C = 1 SETC C SFR SFR ACC,1..16 ACC,T C=1 C = ACC(bit(shift1)) if(T == 0) C = 0 else C = ACC(bit(T1)) SQRA loc16 SQRS loc16 SUB SUB ACC,#16bit << shift ACC,loc16 << shift C = 1 on carry else C = 0 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 if(shift == 16) C = 0 on borrow if(shift != 16) C = 0 on borrow else C = 1 SUB SUB SUB ACC,loc16 << T AX,loc16 loc16,AX C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1
SAT64 ACC:P SB 8bitOff,COND
SBBU ACC,loc16
SUBB ACC,#8bit
2-29

Instruction SUBBL ACC,loc32 Affect of or Affect on C ACC = ACC ([loc32] + ~C) C = 0 on borrow else C = 1 SUBCU ACC,loc16 for(ACC [loc16]<<15) C = 0 on borrow else C = 1 SUBCUL ACC,loc32 for(ACC<<1 + P(31) [loc32]) C = 0 on borrow else C = 1 SUBL ACC,loc32 SUBL loc32,ACC SUBR loc16,AX SUBRL loc32,ACC SUBU ACC,loc16 SUBUL ACC,loc32 SUBUL P,loc32 XB pma,COND C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C = 0 on borrow else C = 1 C bit used as test condition C bit used as test condition C = 1 on carry else C = 0 C = 1 on carry else C = 0 C bit used as test condition
XCALL pma,COND XMAC P,loc16,*(pma) XMACD P,loc16,*(pma) XRETC COND
TC Bit 2
Test/control flag. This bit shows the result of a test performed by either the TBIT (test bit) instruction or the NORM (normalize) instruction. The TBIT instruction tests a specified bit. When TBIT is executed, the TC bit is set if the tested bit is 1 or cleared if the tested bit is 0. When a NORM instruction is executed, TC is modified as follows: If ACC holds 0, TC is set. If ACC does not hold 0, the CPU calculates the exclusive-OR of ACC bits 31 and 30, and then loads TC with the result. This bit can be individually set and cleared by the SETC TC instruction and CLRC TC instruction, respectively. At reset, TC is cleared.
Table 29 lists the instructions that affect the TC bit. See the instruction set in Chapter 6 for a complete description of each instruction.
2-30
Table 29. Instructions That Affect the TC Bit

Instruction ABSTC ACC B BF 16bitOff,COND 16bitOff,COND Affect on the TC bit if( ACC < 0 ) TC = TC ^ 1 TC bit used as test condition TC bit used as test condition TC = 0 TC = 0 0: if(AR(ARP) == AR0) TC = 1 1: if(AR(ARP) < AR0) TC = 1 2: if(AR(ARP) > AR0) TC = 1 3: if(AR(ARP) != AR0) TC = 1 CSB MOV ACC loc16,AX,COND TC = N flag TC bit used as test condition TC bit used as test condition TC bit used as test condition TC bit used as test condition if(ACC |= 0) TC = ACC(31) ^ ACC(30) else TC = 1 SB SBF 8bitOff,COND 8bitOff,TC/NTC TC bit used as test condition TC bit used as test condition TC = 1 TC = [loc16(bit)] TC = [loc16(15T)] TC = [loc16(bit)] TC = [loc16(bit)] TC bit used as test condition TC bit used as test condition TC bit used as test condition
CLRC TC CMPR 0/1/2/3
MOVB loc16,#8bit,COND MOVL loc32,ACC,COND NEGTC ACC NORM ACC,XARn++/ NORM ACC,*ind
SETC TC TBIT loc16,#bit TBIT loc16,T TCLR loc16,#bit TSET loc16,#bit XB pma,COND
XCALL pma,COND XRETC COND
2-31
OVM Bit 1
Overflow mode bit. When ACC accepts the result of an addition or subtraction and the result causes an overflow, OVM determines how the CPU handles the overflow as follows:. 0 1 Results overflow normally in ACC. The OVC reflects the overflow (see the description for the OVC on page 2-16) ACC is filled with either its most positive or most negative value as follows: If ACC overflows in the positive direction (from 7FFF FFFF16 to 8000 000016 ), ACC is then filled with 7FFF FFFF16. If ACC overflows in the negative direction (from 8000 000016 to 7FFF FFFF16 ), ACC is then filled with 8000 000016. This bit can be individually set and cleared by the SETC OVM instruction and CLRC OVM instruction, respectively. At reset, OVM is cleared.
SXM Bit 0
Sign-extension mode bit. SXM affects the MOV, ADD, and SUB instructions that use a 16-bit value in an operation on the 32-bit accumulator. When the 16-bit value is loaded into (MOV), added to (ADD), or subtracted from (SUB) the accumulator, SXM determines whether the 16-bit value is sign extended during the operation as follows: 0 1 Sign extension is suppressed. (The 16-bit value is treated as unsigned.) Sign extension is enabled. (The 16-bit value is treated as signed.)
For example: ADD ACC, loc16 << shift
if SXM = 0, do not sign extend loc16 before adding to the 32-bit ACC. if SXM = 1, sign extend loc16 before adding to the 32-bit ACC. SXM also determines whether the accumulator is sign extended when it is shifted right by the SFR instruction. SXM does not affect instructions that shift the product register value; all right shifts of the product register value use sign extension. This bit can be individually set and cleared by the SETC SXM instruction and CLRC SXM instruction, respectively. At reset, SXM is cleared. Table 210 lists the instructions that are affected by SXM. See Chapter 6 for more details on instructions.
2-32
Table 210. Instructions Affected by SXM

Instruction ADD ADD ADD ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T Description Affected By SXM Affected By SXM Affected By SXM SXM = 0 Affected By SXM Affected By SXM Affected By SXM SXM = 1 Affected By SXM Affected By SXM Affected By SXM Affected By SXM Affected By SXM
CLRC SXM MOV MOV MOV ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T
SETC SXM SFR SFR SUB SUB SUB ACC,1..16 ACC,T ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T
2-33
Status Register ST1
2.4 Status Register ST1

The following figure shows the bit fields of status register ST1. All of these bit fields are modified in the decode 2 phase of the pipeline. Detailed descriptions of these bits follow the figure.
Figure 211.Bit Fields of Status Register 1 (ST1)

15 ARP
R/W-000
13
12 XF
R/W0
11 M0M1MAP
R/W1
10 Reserved
R/W0
9 OBJMODE
R/W0
8 AMODE
R/W0
7 IDLESTAT
R0
6 EALLOW
R/W0
5 LOOP
R0
4 SPA
R/W0
3 VMAP
R/W1
2 PAGE0
R/W0
1 DBGM
R/W1
0 INTM
R/W1
ARP Bits 1513
Auxiliary register pointer. This 3-bit field points to the current auxiliary register. This is one of the 32-bit auxiliary registers (XAR0XAR7). The mapping of ARP values to auxiliary registers is as follows: ARP 000 001 010 011 100 101 110 111 Selected Auxiliary Register XAR0 (selected at reset) XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7
XF Bit 12
XF status bit. This bit reflects the current state of the XFS output signal, which is compatible to the C2XLP CPU. This bit is set by the SETC XF instruction. This bit is cleared by the CLRC XF instruction. The pipeline is not flushed when setting or clearing this bit using the given instructions. This bit can be saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset. M0 and M1 mapping mode bit. The M0M1MAP bit should always remain set to 1 in the C28x object mode. This is the default value at reset. The M0M1MAP bit may be set low when operating in C27x-compatible mode. The effect of this bit, when low, is to swap the location of blocks M0 and M1 only in program space and to set the stack pointer default reset value to 0x000. C28x mode users should never set this bit to 0.
M0M1MAP Bit 11
2-34
Status Register ST1
Reserved Bit 10 OBJMODE Bit 9
Reserved. This bit is reserved. Writes to this bit have no effect.
Object compatibility mode bit. This mode is used to select between C27x object mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1) compatibility. This bit is set by the C28OBJ (or SETC OBJMODE) instructions. This bit is cleared by the C27OBJ (or CLRC OBJMODE) instructions. The pipeline is flushed when setting or clearing this bit using the given instructions. This bit is saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset. Address mode bit. This mode, in conjunction with the PAGE0 mode bit, is used to select the appropriate addressing mode decodes. This bit is set by the LPADDR (SETC AMODE) instructions. This bit is cleared by the C28ADDR (or CLRC AMODE) instructions. The pipeline is not flushed when setting or clearing this bit using the given instructions. This bit is saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset. Note: Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap ONLY for instructions that decode a memory or register addressing mode field (loc16 or loc32).
AMODE Bit 8
IDLESTAT Bit 7
IDLE status bit. This read-only bit is set when the IDLE instruction is executed. It is cleared by any one of the following events: - An interrupt is serviced. - An interrupt is not serviced but takes the CPU out of the IDLE state. - A valid instruction enters the instruction register (the register that holds the instruction currently being decoded). - A device reset occurs. When the CPU services an interrupt, the current value of IDLESTAT is saved on the stack (when ST1 is saved on the stack), and then IDLESTAT is cleared. Upon return from the interrupt, IDLESTAT is not restored from the stack.
EALLOW Bit 6
Emulation access enable bit. This bit, when set, enables access to emulation and other protected registers. Set this bit by using the EALLOW instruction and clear this bit by using the EDIS instruction. See the data sheet for a particular device to determine the registers that are protected. When the CPU services an interrupt, the current value of EALLOW is saved on the stack (when ST1 is saved on the stack), and then EALLOW is cleared. Therefore, at the start of an interrupt service routine (ISR), access to protected registers is disabled. If the ISR must access protected registers, it must include an EALLOW instruction. At the end of the ISR, EALLOW can be restored by the IRET instruction.
LOOP Bit 5
Loop instruction status bit. LOOP is set when a loop instruction (LOOPNZ or LOOPZ) reaches the decode 2 phase of the pipeline. The loop instruction does not end until a specified condition is met. When the condition is met, LOOP is cleared. LOOP is a read-only bit; it is not affected by any instruction except a loop instruction.
2-35
Status Register ST1
When the CPU services an interrupt, the current value of LOOP is saved on the stack (when ST1 is saved on the stack), and then LOOP is cleared. Upon return from the interrupt, LOOP is not restored from the stack.
SPA Bits 4
Stack pointer alignment bit. SPA indicates whether the CPU has previously aligned the stack pointer to an even address by the ASP instruction: 0 The stack pointer has not been aligned to an even address. 1 The stack pointer has been aligned to an even address. When the ASP (align stack pointer) instruction is executed, if the stack pointer (SP) points to an odd address, SP is incremented by 1 so that it points to an even address, and SPA is set. If SP already points to an even address, SP is not changed, but SPA is cleared. When the NASP (unalign stack pointer) instruction is executed, if SPA is 1, SP is decremented by 1 and SPA is cleared. If SPA is 0, SP is not changed. At reset, SPA is cleared.
VMAP Bit 3
Vector map bit. VMAP determines whether the CPU interrupt vectors (including the reset vector) are mapped to the lowest or highest addresses in program memory: 0 CPU interrupt vectors are mapped to the bottom of program memory, addresses 00 00001600 003F16. 1 CPU interrupt vectors are mapped to the top of program memory, addresses 3F FFC0163F FFFF16. On C28x designs, the VMAP signal is tied high internally, forcing the VMAP bit to be set high on a reset. This bit can be individually set and cleared by the SETC VMAP instruction and CLRC VMAP instruction, respectively.
PAGE0 Bit 2
PAGE0 addressing mode configuration bit. PAGE0 selects between two mutually-exclusive addressing modes: PAGE0 direct addressing mode and PAGE0 stack addressing mode. Selection of the modes is as follows: 0 PAGE0 stack addressing mode 1 PAGE0 direct addressing mode
Note: Illegal Instruction Trap Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap.
PAGE0 = 1 is included for compatibility with the C27x. the recommended operating mode for C28x is PAGE0 = 0. This bit can be individually set and cleared by the SETC PAGE0 instruction and CLRC PAGE0 instruction, respectively. At reset, the PAGE0 bit is cleared (PAGE0 stack addressing mode is selected). For details about the above addressing modes, see Chapter 5, Addressing Modes.
2-36
Status Register ST1
DBGM Bit 1
Debug enable mask bit. When DBGM is set, the emulator cannot accesss memory or registers in real time. The debugger cannot update its windows. In the real-time emulation mode, if DBGM = 1, the CPU ignores halt requests or hardware breakpoints until DBGM is cleared. DBGM does not prevent the CPU from halting at a software breakpoint. One effect of this may be seen in real-time emulation mode. If you single-step an instruction in real time emulation mode and that instruction sets DBGM, the CPU continues to execute instructions until DBGM is cleared. When you give the TI debugger the REALTIME command (to enter real-time mode), DBGM is forced to 0. Having DBGM = 0 ensures that debug and test direct memory accesses (DT-DMAs) are allowed; memory and register values can be passed to the host processor for updating debugger windows. Before the CPU executes an interrupt service routine (ISR), it sets DBGM. When DBGM = 1, halt requests from the host processor and hardware breakpoints are ignored. If you want to single-step through or set breakpoints in a non-time-critical ISR, you must add a CLRC DBGM instruction at the beginning of the ISR. DBGM is primarily used in emulation to block debug events in time-critical portions of program code. DBGM enables or disables debug events as follows: 0 1 Debug events are enabled. Debug events are disabled.
When the CPU services an interrupt, the current value of DBGM is saved on the stack (when ST1 is saved on the stack), and then DBGM is set. Upon return from the interrupt, DBGM is restored from the stack. This bit can be individually set and cleared by the SETC DBGM instruction and CLRC DBGM instruction, respectively. DBGM is also set automatically during interrupt operations. At reset, DBGM is set. Executing the ABORTI (abort interrupt) instruction also sets DBGM.
INTM Bit 0
Interrupt global mask bit. This bit globally enables or disables all maskable CPU interrupts (those that can be blocked by software): 0 Maskable interrupts are globally enabled. To be acknowledged by the CPU, a maskable interrupt must also be locally enabled by the interrupt enable register (IER). Maskable interrupts are globally disabled. Even if a maskable interrupt is locally enabled by the IER, it is not acknowledged by the CPU.
INTM has no effect on the nonmaskable interrupts, including a hardware reset or the hardware interrupt NMI. In addition, when the CPU is halted in real-time emulation mode, an interrupt enabled by the IER and the DBGIER will be serviced even if INTM is set to disable maskable interrupts.
2-37
Status Register ST1
When the CPU services an interrupt, the current value of INTM is saved on the stack (when ST1 is saved on the stack), and then INTM is set. Upon return from the interrupt, INTM is restored from the stack. This bit can be individually set and cleared by the SETC INTM instruction and CLRC INTM instruction, respectively. At reset, INTM is set. The value in INTM does not cause modification to the interrupt flag register (IFR), the interrupt enable register (IER), or the debug interrupt enable register (DBGIER).
2-38
Program Flow
2.5 Program Flow

The program control logic and program-address generation logic work together to provide proper program flow. Normally, the flow of a program is sequential: the CPU executes instructions at consecutive program-memory addresses. At times, a discontinuity is required; that is, a program must branch to a nonsequential address and then execute instructions sequentially at that new location. For this purpose, the 28x supports interrupts, branches, calls, returns, and repeats. Proper program flow also requires smooth flow at the instruction level. To meet this need, the 28x has a protected pipeline and an instruction-fetch mechanism that attempts to keep the pipeline full.
2.5.1
Interrupts
Interrupts are hardware- or software-driven events that cause the CPU to suspend its current program sequence and execute a subroutine called an interrupt service routine. Interrupts are described in detail in Chapter 3.
2.5.2
Branches, Calls, and Returns

Branches, calls, and returns break the sequential flow of instructions by transferring control to another location in program memory. A branch only transfers control to the new location. A call also saves the return address (the address of the instruction following the call). Called subroutines or interrupt service routines are each concluded with a return instruction, which takes the return address from the stack or from XAR7 or RPC and places it into the program counter (PC). The following branch instructions are conditional: B, BANZ, BAR, BF, SB, SBF, XBANZ, XCALL, and XRETC. They are executed only if a certain specified or predefined condition is met. For detailed descriptions of these instructions, see Chapter 6, Assembly Language Instructions.
2.5.3
Repeating a Single Instruction

The repeat (RPT) instruction allows the execution of a single instruction (N + 1) times, where N is specified as an operand of the RPT instruction. The instruction is executed once and then repeated N times. When RPT is executed, the repeat counter (RPTC) is loaded with N. RPTC is then decremented every time the repeated instruction is executed, until RPTC equals 0. For a description of RPT and a list of repeatable instructions, see Chapter 6, Assembly Language Instructions.
Central Processing Unit 2-39
Program Flow
2.5.4
Instruction Pipeline
Each instruction passes through eight independent phases that form an instruction pipeline. At any given time, up to eight instructions may be active, each in a different phase of completion. Not all reads and writes happen in the same phases, but a pipeline-protection mechanism stalls instructions as needed to ensure that reads and writes to the same location happen in the order in which they are programmed. To maximize pipeline efficiency, an instruction-fetch mechanism attempts to keep the pipeline full. Its role is to fill an instruction-fetch queue, which holds instructions in preparation for decoding and execution. The instruction-fetch mechanism fetches 32-bits at a time from program memory; it fetches one 32-bit instruction or two 16-bit instructions. The instruction-fetch mechanism uses three program-address counters: the program counter (PC), the instruction counter (IC), and the fetch counter (FC). When the pipeline is full the PC will always point to the instruction in its decode 2 pipeline phase. The IC points to the next instruction to be processed. When the PC points to a 1-word instruction, IC = (PC+1); when the PC points to a 2-word instruction, IC = (PC+2). The value in the FC is the address from which the next fetch is to be made. The pipeline and the instruction-fetch mechanism are described in more detail in Chapter 4, Pipeline.
2-40
Multiply Operations
2.6 Multiply Operations

The C28x features a hardware multiplier that can perform 16-bit X 16-bit or 32-bit X 32-bit fixed-point multiplication. This functionality is enhanced by 16-bit X 16-bit multiply and accumulate (MAC), 32 X 32 MAC, and 16-bit X 16-bit dual MAC (DMAC) instructions. This section describes the components involved in each type of multiplication.
2.6.1
16-bit X 16-bit Multiplication

The C28x multiplier can perform a 16-bit X 16-bit multiplication to produce a signed or unsigned 32-bit product. Figure 212 shows the CPU components involved in this multiplication. The multiplier accepts two 16-bit inputs:
- One input is from the upper 16 bits of the multiplicand register (T). Most
16 X 16 multiplication instructions require that you load T from a datamemory location or a register before you execute the instruction. However, the MAC and some versions of the MPY and MPYA instructions load T for you before the multiplication.
- The other input is from one of the following: J J
A data-memory location or a register (depending on which you specify in the multiply instruction). An instruction opcode. Some C28x multiply instructions allow you to include a constant as an operation.
After the value has been multiplied by the second value, the 32-bit result is stored in one of two places, depending on the particular multiply instruction: the 32-bit product register (P) or the 32-bit accumulator (ACC). One special 16-bit X 16-bit multiplication instruction takes two 32-bit input values as its operands. This instruction is the 16 X 16 DMAC instruction, which performs dual 16 X 16 MAC operations in one instruction. In this case, the ACC contains the result of multiplying and adding the upper word of the 32-bit operands. The P register contains the result of multiplying and adding the results of the lower word of the 32-bit operands.
2-41
Multiply Operations
Figure 212. Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication

From data memory or a register From data memory or a register From an instruction opcode 16 16
16
T 16 Multiplier
MUX 16
32 MUX
32 P
32 ACC
2.6.2
32-Bit X 32-Bit Multiplication The C28x multiplier can also perform 32-bit by 32-bit multiplication. Figure 213 shows the CPU components involved n this multiplication. In this case, the multiplier accepts two 32-bit inputs:
- The first input is from one of the following: J
A program memory location. Some C28x 32 X 32 multiply MAC-type instructions such as IMACL and QMACL take one data value directly from memory using the program-address bus. The 32-bit multiplicand register (XT). Most 32 X 32-bit multiplication instructions require that you load XT from data memory or a register before you execute the instruction.
- A data-memory location or a register (depending on which you specify in
the multiply instruction). After the two values have ben multiplied, 32 bits of the 64-bit result are stored in the product register (P). You can control which half is stored (upper 32 bits or lower 32 Bits) and whether the multiplication is signed or unsigned by the instruction used.
2-42
Multiply Operations
If you need support for larger data values, the 32 X 32 multiplication instructions can be combined to implement 32 X 32 = 64-bit or 64 X 64 = 128-bit math.
Figure 213. Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication

32 XT From program memory 32 MUX 32 Multiplier 32 From data memory or register 32 From data memory or register
upper 32 MUX 32
lower 32
2-43
Shift Operations
2.7 Shift Operations

The shifter holds 64 bits and accepts either a 16-bit, 32-bit, or 64-bit input value. When the input value has 16 bits, the value is loaded into the 16 least significant bits (LSBs) of the shifter. When the input value has 32 bits, the value is loaded into the 32 LSBs of the shifter. Depending on the instruction that uses the shifter, the output of the shifter may be all of its 64 bits or just its 16 LSBs. When a value is shifted right by an amount N, the N LSBs of the value are lost and the bits to the left of the value are filled with all 0s or all 1s. If sign extension is specified, the bits to the left are filled with copies of the sign bit. If sign extension is not specified, the bits to the left are filled with 0s, or zero filled. When a value is shifted left by an amount N, the bits to the right of the shifted value are zero filled. If the value has 16 bits and sign extension is specified, the bits to the left are filled with copies of the sign bit. If the value has 16 bits and sign extension is not specified, the bits to the left are zero filled. If the value has 32 bits, the N MSBs of the value are lost, and sign extension is irrelevant. Table 211 lists the instructions that use the shifter and provides an illustration of the corresponding shifter operation. The table uses the following graphical symbols:
Shift left This symbol represents the 32-bit shifter. The text inside the box indicates the direction of the shift. This symbol indicates zero filling. This symbol indicates sign extending. This symbol indicates that the MSBs of the shifter depend on the sign-extension mode bit (SXM). If SXM = 0, the MSBs are zero filled after the shift. If SXM = 1, the MSBs are filled with the sign of the shifted value. This symbol indicates the carry bit (C).
0 Sign SXM 0/Sign
For explanations of the instruction syntaxes listed in Table 211, see Chapter 6, Assembly Language Instructions.
2-44
Shift Operations
Table 211. Shift Operations

Operation Type Left shift of 16-bit value for ACC operation. Syntaxes: ADD ACC, loc16 << 0...16 ADD ACC, #16Bit <<0...15 ADD ACC, loc16 <<T SUB ACC, loc16 << 0...16 SUB ACC, #16Bit <<0 ...15 SUB ACC, loc16<<T MOV ACC, loc16 << 0...16 MOV ACC, #16Bit << 0...15 MOV ACC, loc16, <<T Store 16 LSBs of left-shifted ACC. Syntax: MOV loc16, ACC << 1...8 Discard ACC 32 bits to ALU Illustration 16-bit value to 16 LSBs SXM 0/Sign Shift left 0
Shift left
16 LSBs to ALU Store 16 MSBs of left-shifted ACC. Syntax: MOVH loc16, ACC <<1...8 Note: This instruction performs a single right shift by (16shift1), where shift1 is a value from 0 to 8. Logical left shift of ACC. The last bit to be shifted out fills the carry bit (C). Syntaxes: LSL ACC, 1...16 LSL ACC, T (shift = T(3:0)) LSL ACC, T (shift = T(4:0)) Note: If T(3:0) = 0 or T(4:0) = 0, indicating a shift of 0, C is cleared. ACC
Shift right
Discard
16 LSBs to ALU ACC Last bit out C Shift left Discard other bits 32 bits to ACC 0
2-45
Shift Operations
Table 211. Shift Operations (Continued)

Operation Type Logical left shift of AH or AL. The last bit to be shifted out fills the carry bit (C). Syntaxes: LSL AX, 1...16 LSL AX, T (shift = T(3:0)) Note: If T(3:0) = 0, indicating a shift of 0, C is cleared. Right shift of ACC. If SXM = 0, a logical shift is performed. If SXM = 1, an arithmetic shift is performed. The last bit to be shifted out fills the carry bit (C). Syntaxes: SFR ACC, 1...16 SFR ACC, T Note: If T(3:0) = 0, indicating a shift of 0, C is cleared. Logical right shift of AH or AL. The last bit to be shifted out fills the carry bit (C). Syntaxes: LSR AX, shift LSR AX, T (shift = T(3:0)) ARLACC, T (shift = T(4:0) Note: If T(4:0) = 0, indicating a shift of 0, C is cleared. Arithmetic right shift of AH or AL. The last bit to be shifted out fills the carry bit (C). Syntaxes: ASR AX, shift ASR AX, T Note: If T(4:0) = 0, indicating a shift of 0, C is cleared. Rotate ACC left by 1 bit. Bit 31 of ACC fills the carry bit (C). C fills bit 0 of ACC. Syntax: ROL ACC C Sign 0 AH/AL to 16 LSBs C Shift right Last bit out Illustration Last bit out AH/AL to 16 LSBs C Shift left 0
16 LSBs to AH/AL ACC SXM 0/Sign Shift right C Last bit out
Discard other bits 32 bits to ACC
Discard other bits 16 LSBs to AH/AL
AH/AL to 16 LSBs C Shift right Last bit out
Discard other bits 16 LSBs to AH/AL ACC
Rotate left
32 bits to ACC
2-46
Shift Operations

Operation Type Rotate ACC right by 1 bit. Bit 0 of ACC fills the carry bit (C). C fills bit 31 of ACC. Syntax: ROR ACC Illustration ACC
Rotate right
32 bits to ACC Logical right shift of ACC:P. Syntaxes: LSR64 ACC:P, 1...16 LSR64, ACC:P, T shift = T(5:0) 0 ACC:P C Shift right Last bit out
Discard other bits 64 bits to ACC:P ACC:P Last bit out C Shift left Discard other bits 64 bits to ACC:P 0
Logical left shift of ACC:P. Syntaxes: LSL64 ACC:P, 1...16 LSL64 ACC:P, T shift = T(5:0)
Arithmetic right shift of ACC:P. Syntaxes: ASR64 ACC:P, 1...16 ASR64, ACC:P, T shift = T(5:0) Sign
ACC:P C Shift right Last bit out
Discard other bits 64 bits to ACC:P ACC
Conditional shift of ACC by 1 bit. Syntaxes: NORM ACC, aux++ NORM ACC, aux SUBCU ACC, loc Discard
Shift left
32 bits to ACC
2-47
Shift Operations

Operation Type Shift of P as per PM bits. Syntaxes: ADD ACC, P SUB ACC, P CMP ACC, P MAC P, loc, 0:pmem MOV ACC, P MOVA T, loc MOVP T, loc MOVS T, loc MPYA P, loc, #16BitSigned MPYA P, T, loc MPYS P, T, loc 32 bits to ALU Sign Shift right Discard For PM from 27: P For PM = 1: No shift 32 bits to ALU Discard Shift left 0 Illustration For PM = 0: P
2-48
Shift Operations

Operation Type Store 16 LSBs of shifted P. P is shifted as per the PM bits. The 16 LSBs of shifter are stored. Syntax: MOV loc16, P Illustration For PM = 0: P
Discard
Shift left
16 LSBs to ALU For PM = 1: No shift
For PM from 27:
Sign
Shift right
Discard
16 LSBs to ALU
Store 16 MSBs of shifted P. P is shifted as per the PM bits. The result is shifted right by 16 so that its 16 MSBs are in the 16 LSBs of the shifter. 16 LSBs of shifter are stored. Syntax: MOVH loc16, P
For PM = 0:
1)
Discard
Shift left
2)
Shift right by 16
Discard
16 LSBs to ALU For PM = 1: No shift
For PM from 27:
1)
Sign
Shift right
Discard
2)
Shift right by 16
Discard
16 LSBs to ALU
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2-50
Chapter 3
CPU Interrupts and Reset

This chapter describes the available CPU interrupts and how they are handled by the CPU. It also explains how to control those interrupts that can be controlled through software. Finally, it describes how a hardware reset affects the CPU.
Topic
3.1 3.2 3.3 3.4 3.5 3.6 3.7
Page
CPU Interrupts Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 CPU Interrupt Vectors and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Maskable Interrupts: INT1INT14, DLOGINT, and RTOSINT . . . . . . . 3-6 Standard Operation for Maskable Interrupts . . . . . . . . . . . . . . . . . . . . 3-11 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Illegal-Instruction Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Hardware Reset (RS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3-1
CPU Interrupts Overview
3.1 CPU Interrupts Overview

Interrupts are hardware- or software-driven signals that cause the C28x CPU to suspend its current program sequence and execute a subroutine. Typically, interrupts are generated by peripherals or hardware devices that need to give data to or take data from the C28x (for example, A/D and D/A converters and other processors). Interrupts can also signal that a particular event has taken place (for example, a timer has finished counting). On the C28x, interrupts can be triggered by software (the INTR, OR IFR, or TRAP instruction) or by hardware (a pin, an external peripheral, or on-chip peripheral/logic). If hardware interrupts are triggered at the same time, the C28x services them according to a set priority ranking. Some 28x devices include a peripheral interrupt expansion (PIE) module that multiplexes interrupts from a number of peripherals into a single CPU interrupt. The PIE module provides additional control before an interrupt reaches the C28x CPU. See the TMS320C8x System and Interrupts Reference Guide (literature number SPRU078) for more details. At the CPU level, each of the C28x interrupts, whether hardware or software, can be placed in one of the following two categories:
- Maskable interrupts.These are interrupts that can be blocked (masked)
or enabled (unmasked) through software.

- Nonmaskable interrupts. These interrupts cannot be blocked. The C28x
will immediately approve this type of interrupt and branch to the corresponding subroutine. All software-initiated interrupts are in this category. The C28x handles interrupts in four main phases: 1) Receive the interrupt request. Suspension of the current program sequence must be requested by a software interrupt (from program code) or a hardware interrupt (from a pin or an on-chip device). 2) Approve the interrupt. The C28x must approve the interrupt request. If the interrupt is maskable, certain conditions must be met in order for the C28x to approve it. For nonmaskable hardware interrupts and for software interrupts, approval is immediate. 3) Prepare for the interrupt service routine and save register values. The main tasks performed in this phase are:
- Complete execution of the current instruction and flush from the pipe-
line any instructions that have not reached the decode 2 phase.
- Automatically save most of the current program context by saving the
following registers to the stack: ST0, T, AL, AH, PL, PH, AR0, AR1, DP, ST1, DBGSTAT, PC, and IER.
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CPU Interrupts Overview
- Fetch the interrupt vector and load it into the program counter (PC).
For devices with a PIE module, the vector fetched will depend on the setting of the PIE enable and flag registers. 4) Execute the interrupt service routine. The C28x branches to its corresponding subroutine called an interrupt service routine (ISR). The C28x branches to the address (vector) you store at a predetermined vector location and executes the ISR you have written.
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CPU Interrupt Vectors and Priorities
3.2 CPU Interrupt Vectors and Priorities

The C28x supports 32 CPU interrupt vectors, including the reset vector. Each vector is a 22-bit address that is the start address for the corresponding interrupt service routine (ISR). Each vector is stored in 32 bits at two consecutive addresses. The location at the lower address holds the 16 least significant bits (LSBs) of the vector. The location at the higher address holds the 6 most significant bits (MSBs) right-justified. When an interrupt is approved, the 22-bit vector is fetched, and the 10 MSBs at the higher address are ignored. For devices with a PIE module, this table is re-mapped and expanded into the PIE vector table. Table 31 lists the available CPU interrupt vectors and their locations. The addresses are shown in hexadecimal form. The table also shows the priority of each of the hardware interrupts.

Table 31. Interrupt Vectors and Priorities
VMAP = 0 00 0000 00 0002 00 0004 00 0006 00 0008 VMAP = 1 3F FFC0 3F FFC2 3F FFC4 3F FFC6 3F FFC8 Absolute Address (hexadecimal) Vector Hardware Priority Description Reset RESET INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 1 (highest) 5 6 7 8 9 Maskable interrupt 1 Maskable interrupt 2 Maskable interrupt 3 Maskable interrupt 4 Maskable interrupt 5 Maskable interrupt 6 Maskable interrupt 7 Maskable interrupt 8 Maskable interrupt 9 00 000A 3F FFCA 00 000C 00 000E 00 0010 00 0012 00 0014 00 0016 00 0018 3F FFCC 3F FFCE 3F FFD0 3F FFD2 3F FFD4 3F FFD6 3F FFD8 10 11 12 13 14 15 16 17 18 INT10 INT11 Maskable interrupt 10 Maskable interrupt 11 INT12 INT13 INT14

Maskable interrupt 12 Maskable interrupt 13 Maskable interrupt 14
00 001A
3F FFDA
00 001C
3F FFDC
For C28x catalog devices, VMAP = 1 at reset. Interrupts DLOGINT and RTOSINT are generated by the emulation logic internal to the CPU.
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CPU Interrupt Vectors and Priorities

Table 31. Interrupt Vectors and Priorities (Continued)
Absolute Address (hexadecimal) VMAP = 0 00 001E 00 0020 00 0022 00 0024 00 0026 00 0028 VMAP = 1 3F FFDE 3F FFE0 3F FFE2 3F FFE4 3F FFE6 3F FFE8 Vector Hardware Priority Description DLOGINT RTOSINT Reserved NMI 19 (lowest) 4 2 3 Maskable data log interrupt Maskable real-time operating system interrupt Reserved Nonmaskable interrupt Illegal-instruction trap ILLEGAL USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt User-defined software interrupt 00 002A 3F FFEA 00 002C 00 002E 00 0030 00 0032 00 0034 00 0036 00 0038 3F FFEC 3F FFEE 3F FFF0 3F FFF2 3F FFF4 3F FFF6 3F FFF8 USER10 USER11 00 003A 3F FFFA 00 003C 00 003E 3F FFFC 3F FFFE USER12

For C28x catalog devices, VMAP = 1 at reset. Interrupts DLOGINT and RTOSINT are generated by the emulation logic internal to the CPU.
The vector table can be mapped to the top or bottom of program space, depending on the value of the vector map bit (VMAP) in status register ST1. (ST1 is described in section 2.4 on page 2-34.) If the VMAP bit is 0, the vectors are mapped beginning at address 00 000016. If the VMAP bit is 1, the vectors are mapped beginning at address 3F FFC016. Table 31 lists the absolute addresses for VMAP = 0 and VMAP = 1. The VMAP bit can be set by the SETC VMAP instruction and cleared by the CLRC VMAP instruction. The reset value of VMAP is 1.
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Maskable Interrupts: INT1INT14, DLOGINT, and RTOSINT
3.3 Maskable Interrupts: INT1INT14, DLOGINT, and RTOSINT

INT1INT14 are 14 general-purpose interrupts. DLOGINT (the data log interrupt) and RTOSINT (the real-time operating system interrupt) are available for emulation purposes. These interrupts are supported by three dedicated registers: the CPU interrupt flag register (IFR), the CPU interrupt enable register (IER), and the CPU debug interrupt enable register (DBGIER). The 16-bit IFR contains flag bits that indicate which of the corresponding interrupts are pending (waiting for approval from the CPU). The external input lines INT1INT14 are sampled at every CPU clock cycle. If an interrupt signal is recognized, the corresponding bit in the IFR is set and latched. For DLOGINT or RTOSINT, a signal sent by the CPU on-chip analysis logic causes the corresponding flag bit to be set and latched. You can set one or more of the IFR bits at the same time by using the OR IFR instruction. More details about the IFR are given in section 3.3.1. The on-chip analysis resources are introduced in Chapter 7. The interrupt enable register (IER) and the debug interrupt enable register (DBGIER) each contain bits for individually enabling or disabling the maskable interrupts. To enable one of the interrupts in the IER, you set the corresponding bit in the IER; to enable the same interrupt in the DBGIER, you set the corresponding bit in the DBGIER. The DBGIER indicates which interrupts can be serviced when the CPU is in the real-time emulation mode. The IER and the DBGIER are discussed more in section 3.3.2. Real-time mode is discussed in section 7.4.2 on page 7-9. The maskable interrupts also share bit 0 in status register ST1. This bit, the interrupt global mask bit (INTM), is used to globally enable or globally disable these interrupts. When INTM = 0, these interrupts are globally enabled. When INTM = 1, these interrupts are globally disabled. You can set and clear INTM with the SETC INTM and CLRC INTM instructions, respectively. ST1 is described in section 2.4 on page 2-34. After a flag has been latched in the IFR, the corresponding interrupt is not serviced until it is appropriately enabled by two of the following: the IER, the DBGIER, and the INTM bit. As shown in Table 32, the requirements for enabling the maskable interrupts depend on the interrupt-handling process used. In the standard process, which occurs in most circumstances, the DBGIER is ignored. When the C28x is in real-time emulation mode and the CPU is halted, a different process is used. In this special case, the DBGIER is used and the INTM bit is ignored. (If the DSP is in real-time mode and the CPU is running, the standard interrupt-handling process applies.)
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Once an interrupt has been requested and properly enabled, the CPU prepares for and then executes the corresponding interrupt service routine. For a detailed description of this process, see section 3.4.
Table 32. Requirements for Enabling a Maskable Interrupt

Interrupt-Handling Process Standard DSP in real-time mode and CPU halted Interrupt Enabled If ... INTM = 0 and bit in IER is 1 Bit in IER is 1 and bit in DBGIER is 1
As an example of varying interrupt-enable requirements, suppose you want interrupt INT5 enabled. This corresponds to bit 4 in the IER and bit 4 in the DBGIER. Usually, INT5 is enabled if INTM = 0 and IER(4) = 1. In real-time emulation mode with the CPU halted, INT5 is enabled if IER(4) = 1 and DBGIER(4) = 1.
3.3.1
CPU Interrupt Flag Register (IFR)

Figure 31 shows the IFR. If a maskable interrupt is pending (waiting for approval from the CPU), the corresponding IFR bit is 1; otherwise, the IFR bit is 0. To identify pending interrupts, use the PUSH IFR instruction and then test the value on the stack. Use the OR IFR instruction to set IFR bits, and use the AND IFR instruction to clear pending interrupts. When a hardware interrupt is serviced, or when an INTR instruction is executed, the corresponding IFR bit is cleared. All pending interrupts are cleared by the AND IFR, #0 instruction or by a hardware reset. Notes: When an interrupt is requested by the TRAP instruction, if the corresponding IFR bit is set, the CPU does not clear it automatically. If an application requires that the IFR bit be cleared, the bit must be cleared in the interrupt service routine.

Figure 31. Interrupt Flag Register (IFR)
15 14 13 12 11 10 9 8
RTOSINT
R/W0 7
DLOGINT
R/W0 6
INT14
INT13
INT12
INT11
INT10
INT9
R/W0 5
R/W0 4
R/W0 3
R/W0 2
R/W0 1
R/W0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Note:
R = Read access; W = Write access; value following dash () is value after reset.
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Bits 15 and 14 of the IFR correspond to the interrupts RTOSINT and DLOGINT: RTOSINT Bit 15 Real-time operating system interrupt flag RTOSINT = 0 RTOSINT = 1 DLOGINT Bit 14 RTOSINT is not pending. RTOSINT is pending.
Data log interrupt flag DLOGINT = 0 DLOGINT = 1 DLOGINT is not pending. DLOGINT is pending.
For bits INT1INT14, the following general description applies: INTx Bit (x1) Interrupt x flag (x = 1, 2, 3, ..., or 14) INTx = 0 INTx = 1 INTx is not pending. INTx is pending.
3.3.2
CPU Interrupt Enable Register (IER) and CPU Debug Interrupt Enable Register (DBGIER)
Figure 32 shows the IER. To enable an interrupt, set its corresponding bit to 1. To disable an interrupt, clear its corresponding bit to 0. Two syntaxes of the MOV instruction allow you to read from the IER and write to the IER. In addition, the OR IER instruction enables you to set IER bits, and the AND IER instruction enables you to clear IER bits. When a hardware interrupt is serviced, or when an INTR instruction is executed, the corresponding IER bit is cleared. At reset, all the IER bits are cleared to 0, disabling all the corresponding interrupts. Note: When an interrupt is requested by the TRAP instruction, if the corresponding IER bit is set, the CPU does not clear it automatically. If an application requires that the IER bit be cleared, the bit must be cleared in the interrupt service routine.
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Figure 32. Interrupt Enable Register (IER)
15 14 13 12 11 10 9 8
RTOSINT
R/W0 7
DLOGINT
R/W0 6
INT14
INT13
INT12
INT11
INT10
INT9
R/W0 5
R/W0 4
R/W0 3
R/W0 2
R/W0 1
R/W0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Note:
Note: When using the AND IER and OR IER instructions, make sure that they do not modify the state of bit 15 (RTOSINT) unless a real-time operating system is present. Bits 15 and 14 of the IER enable or disable the interrupts RTOSINT and DLOGINT: RTOSINT Bit 15 Real-time operating system interrupt enable bit RTOSINT = 0 RTOSINT = 1 DLOGINT Bit 14 RTOSINT is disabled. RTOSINT is enabled.
Data log interrupt enable bit DLOGINT = 0 DLOGINT = 1 DLOGINT is disabled. DLOGINT is enabled.
For bits INT1INT14, the following general description applies: INTx Bit (x1) Interrupt x enable bit (x = 1, 2, 3, ..., or 14) INTx = 0 INTx = 1 INTx is disabled. INTx is enabled.
Figure 33 shows the DBGIER, which is used only when the CPU is halted in real-time emulation mode. An interrupt enabled in the DBGIER is defined as a time-critical interrupt. When the CPU is halted in real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in the IER. If the CPU is running in real-time emulation mode, the standard interrupt-handling process is used and the DBGIER is ignored.
CPU Interrupts and Reset 3-9
As with the IER, you can read the DBGIER to identify enabled or disabled interrupts and write to the DBGIER to enable or disable interrupts. To enable an interrupt, set its corresponding bit to 1. To disable an interrupt, set its corresponding bit to 0. Use the PUSH DBGIER instruction to read from the DBGIER and the POP DBGIER instruction to write to the DBGIER. At reset, all the DBGIER bits are set to 0.

Figure 33. Debug Interrupt Enable Register (DBGIER)
15 14 13 12 11 10 9 8
RTOSINT
R/W0 7
DLOGINT
R/W0 6
INT14
INT13
INT12
INT11
INT10
INT9
R/W0 5
R/W0 4
R/W0 3
R/W0 2
R/W0 1
R/W0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Note:
Bits 15 and 14 of the DBGIER enable or disable the interrupts RTOSINT and DLOGINT: RTOSINT Bit 15 Real-time operating system interrupt debug enable bit RTOSINT = 0 RTOSINT = 1 DLOGINT Bit 14 RTOSINT is disabled. RTOSINT is enabled.
Data log interrupt debug enable bit DLOGINT = 0 DLOGINT = 1 DLOGINT is disabled. DLOGINT is enabled.
For bits INT1INT14, the following general description applies: INTx Bit (x1) Interrupt x debug enable bit (x = 1, 2, 3, ..., or 14) INTx = 0 INTx = 1 INTx is disabled. INTx is enabled.
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Standard Operation for Maskable Interrupts
3.4 Standard Operation for Maskable Interrupts

The flow chart in Figure 34 shows the standard process for handling interrupts. Section 7.4.2 on page 7-9 contains information on handling interrupts when the DSP is in real-time mode and the CPU is halted. When more than one interrupt is requested at the same time, the C28x services them one after another according to their set priority ranking. See the priorities in Table 31 on page 3-4. Figure 34 is not meant to be an exact representation of how an interrupt is handled. It is a conceptual model of the important events.
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Figure 34. Standard Operation for CPU Maskable Interrupts

Interrupt request sent to CPU
Set corresponding IFR flag bit.
No Interrupt enabled in IER? Yes No Interrupt enabled by INTM bit? Yes Clear corresponding IFR bit. Empty pipeline. Increment and temporarily store PC. Fetch interrupt vector. Increment SP by 1. Perform automatic context save. Clear corresponding IER bit. Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. Load PC with fetched vector.
This sequence protected from interrupts
Execute interrupt service routine.
Program continues
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What following list explains the steps shown in Figure 34: 1) Interrupt request sent to CPU. One of the following events occurs:
- One of the pins INT1INT14 is driven low by an external event, periph-
eral or PIE interrupt request..

- The CPU emulation logic sends to the CPU a signal for DLOGINT or
RTOSINT.
- One of the interrupts INT1INT14, DLOGINT, and RTOSINT is initi-
ated by way of the OR IFR instruction. 2) Set corresponding IFR flag bit. When the CPU detects a valid interrupt in step 1, it sets and latches the corresponding flag in the interrupt flag register (IFR). This flag stays latched even if the interrupt is not approved by the CPU in step 3. The IFR is explained in detail in section 3.3.1. 3) Is the interrupt enabled in IER? Is the interrupt enabled by INTM bit? The CPU approves the interrupt only if the following conditions are true:
- The corresponding bit in the IER is 1. - The INTM bit in ST1 is 0.
Once an interrupt has been enabled and then approved by the CPU, no other interrupts can be serviced until the CPU has begun executing the interrupt service routine for the approved interrupt (step 13). The IER is described in section 3.3.2. ST1 is described in section 2.4 on page 2-34. 4) Clear corresponding IFR bit. Immediately after the interrupt is approved, its IFR bit is cleared. If the interrupt signal is kept low, the IFR register bit will be set again. However, the interrupt is not immediately serviced again. The CPU blocks new hardware interrupts until the interrupt service routine (ISR) begins. In addition, the IER bit is cleared (in step 10) before the ISR begins; therefore, an interrupt from the same source cannot disturb the ISR until the IER bit is set again by the ISR. 5) Empty the pipeline. The CPU completes any instructions that have reached or passed their decode 2 phase in the instruction pipeline. Any instructions that have not reached this phase are flushed from the pipeline. 6) Increment and temporarily store PC. The PC is incremented by 1 or 2, depending on the size of the current instruction. The result is the return address, which is temporarily saved in an internal hold register. During the automatic context save (step 9), the return address is pushed onto the stack.
7) Fetch interrupt vector. The PC is filled with the address of the appropriate interrupt vector, and the vector is fetched from that location. To determine which vector address has been assigned to each of the interrupts, see section 3.2, Interrupt Vectors, on page 3-4 or, if your device uses a PIE module, see the System and Interrupts Reference Guide for your specific device. 8) Increment SP by 1. The stack pointer (SP) is incremented by 1 in preparation for the automatic context save (step 9). During the automatic context save, the CPU performs 32-bit accesses, and the CPU expects 32-bit accesses to be aligned to even addresses by the memory wrapper. Incrementing SP by 1 ensures that the first 32-bit access does not overwrite the previous stack value. 9) Perform automatic context save. A number of register values are saved automatically to the stack. These registers are saved in pairs; each pair is saved in a single 32-bit operation. At the end of each 32-bit save operation, the SP is incremented by 2. Table 33 shows the register pairs and the order in which they are saved. The CPU expects all 32-bit saves to be even-word aligned by the memory wrapper. As shown in the table, the SP is not affected by this alignment.

Table 33. Register Pairs Saved and SP Positions for Context Saves
Save Operation Register Pairs SP Starts at Odd Address Bit 0 of Storage Address SP Starts at Even Address 1 1 SP position before step 8 0 1 0 1 0 1 0 1 0 1 1st ST0 T 0 SP position before step 8 1 0 1 0 1 0 1 0 1

2nd AL AH 3rd PL PH 4th AR0 AR1 5th ST1 DP
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Table 33. Register Pairs Saved and SP Positions for Context Saves (Continued)
Save Operation 6th Register Pairs IER Bit 0 of Storage Address SP Starts at Odd Address 0 1 0 SP Starts at Even Address 0 1 0 DBGSTAT 7th Return address (low half) Return address (high half) 1 0 SP position after save 1

0 1 SP position after save
All registers are saved as pairs, as shown. The P register is saved with 0 shift (CPU ignores current state of the product shift mode bits, PM, in status register 0). The DBGSTAT register contains special emulation information.
10) Clear corresponding IER bit. After the IER register is saved on the stack in step 9, the CPU clears the IER bit that corresponds to the interrupt being handled. This prevents reentry into the same interrupt. If you want to nest occurrences of the interrupt, have the ISR set that IER bit again. 11) Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. All these bits are in status register ST1. By setting INTM to 1, the CPU prevents maskable interrupts from disturbing the ISR. If you wish to nest interrupts, have the ISR clear the INTM bit. By setting DBGM to 1, the CPU prevents debug events from disturbing time-critical code in the ISR. If you do not want debug events blocked, have the ISR clear DBGM. The CPU clears LOOP, EALLOW, and IDLESTAT so that the ISR operates within a new context. 12) Load PC with fetched vector. The PC is loaded with the interrupt vector that was fetched in step 7. The vector forces program control to the ISR. 13) Execute interrupt service routine. Here is where the CPU executes the program code you have prepared to handle the interrupt. A typical ISR is shown in Example 31. Although a number of register values are saved automatically in step 10, if the ISR uses other registers, you may need to save the contents of these registers at the beginning of the ISR. These values must then be restored before the return from the ISR. The ISR in Example 31 saves and restores auxiliary registers AR1H:AR0H, XAR2XAR7, and the temporary register XT.
If you want the ISR to inform a peripheral that the interrupt is being serviced, you can use the IACK instruction to send an interrupt acknowledge signal. The IACK instruction accepts a 16-bit constant as an operand. For a detailed description of the IACK instruction, see Chapter 6, C28x Assembly Language Instructions. 14) Program continues. If the interrupt is not approved by the CPU, the interrupt is ignored, and the program continues uninterrupted. If the interrupt is approved, its interrupt service routine is executed and the program continues where it left off (at the return address).
Example 31. Typical ISR

C28x Full Context Save/Restore INTX: ; PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH ; +8 = 16 cycles . . . POP POP POP POP POP POP POP POP IRET ; 16 cycles 8 cycles AR1H:AR0H XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 XT
; ; ; ; ; ; ; ;
32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit
XT XAR7 XAR6 XAR5 XAR4 XAR3 XAR2 XAR1H:AR0H
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Nonmaskable Interrupts
3.5 Nonmaskable Interrupts

Nonmaskable interrupts cannot be blocked by any of the enable bits (the INTM bit, the DBGM bit, and enable bits in the IFR, IER, or DBGIER). The C28x immediately approves this type of interrupt and branches to the corresponding interrupt service routine. There is one exception to this rule: When the CPU is halted in stop mode (an emulation mode), no interrupts are serviced. Stop mode is described in section 7.4.1 on page 7-7. The C28x nonmaskable interrupts include:
-
Software interrupts (the INTR and TRAP instructions). Hardware interrupt NMI Illegal-instruction trap Hardware reset interrupt (RS)
The software interrupt instructions and NMI are described in this section. The illegal-instruction trap and reset are described in sections 3.6 and 3.7, respectively.
3.5.1
INTR Instruction
You can use the INTR instruction to initiate one of the following interrupts by name: INT1INT14, DLOGINT, RTOSINT and NMI. For example, you can execute the interrupt service routine for INT1 by using the following instruction:
INTR INT1
Once an interrupt is initiated by the INTR instruction, how it is handled depends on which interrupt is specified:
- INT1INT14, DLOGINT, and RTOSINT. These maskable interrupts have
corresponding flag bits in the IFR. When a request for one of these interrupts is received at an external pin, the corresponding IFR bit is set and the interrupt must be enabled to be serviced. In contrast, when one of these interrupts is initiated by the INTR instruction, the IFR flag is not set, and the interrupt is serviced regardless of the value of any enable bits. However, in other respects, the INTR instruction and the hardware request are the same. For example, both clear the IFR bit that corresponds to the requested interrupt. For more details, see section 3.4 on page 3-11.
- NMI. Because this interrupt is nonmaskable, a hardware request at a pin
and a software request with the INTR instruction lead to the same events. These events are identical to those that take place during a TRAP instruction (see section 3.5.2). Chapter 6, C28x Assembly Language Instructions, contains a detailed description of the INTR instruction.
3.5.2
TRAP Instruction
You can use the TRAP instruction to initiate any interrupt, including one of the user-defined software interrupts (see USER1USER12 in Table 31 on page 3-4). The TRAP instruction refers to one of the 32 interrupts by a number from 0 to 31. For example, you can execute the interrupt service routine for INT1 by using the following instruction:
TRAP #1
Regardless of whether the interrupt has bits set in the IFR and IER, neither the IFR nor the IER is affected by this instruction. Figure 35 shows a functional flow chart for an interrupt initiated by the TRAP instruction. For more details about the TRAP instruction, see Chapter 6, C28x Assembly Language Instructions. Note: The TRAP #0 instruction does not initiate a full reset. It only forces execution of the interrupt service routine that corresponds to the RESET interrupt vector.
Figure 35. Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction
INTM bit, IFR, IER, and DBGIER ignored and not affected TRAP instruction fetched
Empty the pipeline. Increment and temporarily store PC. Fetch interrupt vector. Increment SP by 1. Perform automatic context save. Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. Load PC with fetched vector.
This sequence protected from interrupts
Execute interrupt service routine.
Program continues
3-18
The following lists explains the steps shown in Figure 35: 1) TRAP instruction fetched. The CPU fetches the TRAP instruction from program memory. The desired interrupt vector has been specified as an operand and is now encoded in the instruction word. At this stage, no other interrupts can be serviced until the CPU begins executing the interrupt service routine (step 9). 2) Empty the pipeline. The CPU completes any instructions that have reached or passed the decode 2 phase of the pipeline. Any instructions that have not reached this phase are flushed from the pipeline. 3) Increment and temporarily store PC. The PC is incremented by 1. This value is the return address, which is temporarily saved in an internal hold register. During the automatic context save (step 6), the return address is pushed onto the stack. 4) Fetch interrupt vector. The PC is set to point to the appropriate vector location (based on the VMAP bit and the interrupt), and the vector located at the PC address is loaded into the PC. (To determine which vector address has been assigned to each of the interrupts, see section 3.2, Interrupt Vectors, on page 3-4.) 5) Increment SP by 1. The stack pointer (SP) is incremented by 1 in preparation for the automatic context save (step 6). During the automatic context save, the CPU performs 32-bit accesses, which are aligned to even addresses. Incrementing SP by 1 ensures that the first 32-bit access will not overwrite the previous stack value. 6) Perform automatic context save. A number of register values are saved automatically to the stack. These registers are saved in pairs; each pair is saved in a single 32-bit operation. At the end of each 32-bit operation, the SP is incremented by 2. Table 33 shows the register pairs and the order in which they are saved. All 32-bit saves are even-word aligned. As shown in the table, the SP is not affected by this alignment.
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Table 34. Register Pairs Saved and SP Positions for Context Saves
Save Operation Register Pairs SP Starts at Odd Address Bit 0 of Storage Address SP Starts at Even Address 1 1 SP position before step 5 0 1 0 1 0 1 0 1 0 1 0 1 0 1st ST0 T 0 SP position before step 5 1 0 1 0 1 0 1 0 1 0 1 0

2nd AL AH 3rd PL PH 4th AR0 AR1 5th ST1 DP

6th IER DBGSTAT 7th Return address (low half) Return address (high half) 1 0 SP position after save 1

0 1 SP position after save
All registers are saved as pairs, as shown. The P register is saved with 0 shift (CPU ignores current state of the product shift mode bits, PM, in status register 0). The DBGSTAT register contains special emulation information.
7) Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. All these bits are in status register ST1 (described in section 2.4 on page 2-34). By setting INTM to 1, the CPU prevents maskable interrupts from disturbing the ISR. If you wish to nest interrupts, have the ISR clear the INTM bit. By setting DBGM to 1, the CPU prevents debug events from disturbing timecritical code in the ISR. If you do not want debug events blocked, have the ISR clear DBGM.
3-20
The CPU clears LOOP, EALLOW, and IDLESTAT so that the ISR operates within a new context. 8) Load PC with fetched vector. The PC is loaded with the interrupt vector that was fetched in step 4. The vector forces program control to the ISR. 9) Execute interrupt service routine. The CPU executes the program code you have prepared to handle the interrupt. You may wish to have the interrupt service routine (ISR) save register values in addition to those saved in step 6. A typical ISR is shown in Example 31 on page 3-16. If you want the ISR to inform external hardware that the interrupt is being serviced, you can use the IACK instruction to send an interrupt acknowledge signal. The IACK instruction accepts a 16-bit constant as an operand and drives this 16-bit value on the 16 least significant lines of the data-write bus, DWDB(15:0). For a detailed description of the IACK instruction, see Chapter 6, C28x Assembly Language Instructions. 10) Program continues. After the interrupt service routine is completed, the program continues where it left off (at the return address).
3.5.3
Hardware Interrupt NMI

An interrupt can be requested by way the NMI input pin, which must be driven low to initiate the interrupt. Although NMI cannot be masked, there are some debug execution states in which NMI is not serviced (see section 7.4, Execution Control Modes, on page 7-7). For more details on real-time mode, see section 7.4.2 on page 7-9. Once a valid request is detected on the NMI pin, the CPU handles the interrupt in the same manner as shown for the TRAP instruction (see section 3.5.2).
3-21
Illegal-Instruction Trap
3.6 Illegal-Instruction Trap

Any one of the following events causes an illegal-instruction trap:
- An invalid instruction is decoded (this includes invalid addressing modes). - The opcode value 000016 is decoded. This opcode corresponds to the
ITRAP0 instruction.
- The opcode value FFFF16 is decoded. This opcode corresponds to the
ITRAP1 instruction.
- A 32-bit operation attempts to use the @SP register addressing mode. - Address mode setting AMODE=1 and PAGE0=1
An illegal-instruction trap cannot be blocked, not even during emulation. Once initiated, an illegal-instruction trap operates the same as a TRAP #19 instruction. The handling of an interrupt initiated by the TRAP instruction is described in section 3.5.2. As part of its operation, the illegal-instruction trap saves the return address on the stack. Thus, you can detect the offending address by examining this saved value. For more information about the TRAP instruction, see Chapter 6, C28x Assembly Language Instructions.
3-22
Hardware Reset (RS)
3.7 Hardware Reset (RS)

When asserted, the reset input signal (RS) places the CPU into a known state. As part of a hardware reset, all current operations are aborted, the pipeline is flushed, and the CPU registers are reset as shown in Table 35. Then the RESET interrupt vector is fetched and the corresponding interrupt service routine is executed. For the reset condition of signals, see the data sheet for your particular C28x DSP. Also see the your data sheet for specific information on the process for resetting your DSP. Although RS cannot be masked, there are some debug execution states in which RS is not serviced (see section 7.4, Execution Control Modes, on page 7-7).
Table 35. Registers After Reset
Register ACC XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 DP IFR
Bit(s) all all all all all all all all all all 16 bits
Value After Reset 0000 000016 0000 000016 0000 000016 0000 000016 0000 000016 0000 000016 0000 000016 0000 000016 0000 000016 000016 000016
Comments
DP points to data page 0. There are no pending interrupts. All interrupts pending at the time of reset have been cleared. Maskable interrupts are disabled in the IER. Maskable interrupts are disabled in the DBGIER.
IER
16 bits
000016 000016
DBGIER
all
Note:
The registers listed in this table are introduced in section 2.2, CPU Registers, on page 2-4.
3-23
Hardware Reset (RS)
Table 35. Registers After Reset (Continued)

Register P PC Bit(s) all all Value After Reset 0000 000016 3F FFC016 PC is loaded with the reset interrupt vector at program-space address 00 000016 or 3F FFC016. Comments
RPC SP
all all
000016 SP = 0x400 SP points to address 0400. Sign extension is suppressed. Overflow mode is off.
ST0
0: SXM
1: OVM 2: TC 3: C 4: Z 5: N 6: V 79: PM
0 0 0 0 0 0 0002 00 00002
The product shift mode is set to left-shift-by-1.
1015: OVC
Note:
3-24
Hardware Reset (RS)

Register ST1 Bit(s) 0: INTM Value After Reset 1 Comments Maskable interrupts are globally disabled. They cannot be serviced unless the C28x is in real-time mode with the CPU halted. Emulation accesses and events are disabled. PAGE0 stack addressing mode is enabled. PAGE0 direct addressing mode is disabled. The interrupt vectors are mapped to programmemory addresses 3F FFC0163F FFFF16.
1: DBGM
2: PAGE0
3: VMAP
4: SPA 5: LOOP 6: EALLOW
0 0 0 Access to emulation registers is disabled.
7: IDLESTAT 8: AMODE
0 0 C27x/C28x mode addressing
9: OBJMODE 10: Reserved 11: M0M1MAP

Note:
0 0 1
C27x object mode
3-25
Hardware Reset (RS)

Register Bit(s) 12: XF 1315: ARP XT
Note:
Value After Reset 0 0002 0000 000032
Comments XFS output signal is low ARP points to AR0.
all
3-26
Chapter 4
Pipeline
This chapter explains the operation of the C28x instruction pipeline. The pipeline contains hardware that prevents reads and writes at the same register or data-memory location from happening out of order. However, you can increase the efficiency of your programs if you take into account the operation of the pipeline. In addition, you should be aware of two types of pipeline conflicts the pipeline does not protect against and how you can avoid them (see section 4.5). For more information about the instructions shown in examples throughout this chapter, see Chapter 6, C28x Assembly Language Instructions.
Topic
4.1 4.2 4.3 4.4 4.5
Page
Pipelining of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Visualizing Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Freezes in Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Pipeline Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Avoiding Unprotected Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4-1
Pipelining of Instructions
4.1 Pipelining of Instructions

When executing a program, the C28x CPU performs these basic operations:
-
Fetches instructions from program memory Decodes instructions Reads data values from memory or from CPU registers Executes instructions Writes results to memory or to CPU registers
For efficiency, the C28x performs these operations in eight independent phases. Reads from memory are designed to be pipelined in two stages, which correspond to the two pipeline phases used by the CPU for each memory-read operation. At any time, there can be up to eight instructions being carried out, each in a different phase of completion. Following are descriptions of the eight phases in the order they occur. The address and data buses mentioned in these descriptions are introduced in section 1.4.1 on page 1-9. Fetch 1 (F1) Fetch 2 (F2) In the fetch 1 (F1) phase, the CPU drives a program-memory address on the 22-bit program address bus, PAB(21:0). In the fetch 2 (F2) phase, the CPU reads from program memory by way of the program-read data bus, PRDB (31:0), and loads the instruction(s) into an instruction-fetch queue.
Decode 1 The C28x supports both 32-bit and 16-bit instructions and an (D1) instruction can be aligned to an even or odd address. The decode 1 (D1) hardware identifies instruction boundaries in the instruction-fetch queue and determines the size of the next instruction to be executed. It also determines whether the instruction is a legal instruction.
4-2
Decode 2 The decode 2 (D2) hardware requests an instruction from the (D2) instruction-fetch queue. The requested instruction is loaded into the instruction register, where decoding is completed. Once an instruction reaches the D2 phase, it runs to completion. In this pipeline phase, the following tasks are performed:
- If data is to be read from memory, the CPU generates the
source address or addresses.

- If data is to be written to memory, the CPU generates the
destination address.
- The address register arithmetic unit (ARAU) performs any
required modifications to the stack pointer (SP) or to an auxiliary register and/or the auxiliary register pointer (ARP).
- If a program-flow discontinuity (such as a branch or an
illegal-instruction trap) is required, it is taken. Read 1 (R1) Read 2 (R2) Execute (E) If data is to be read from memory, the read 1 (R1) hardware drives the address(es) on the appropriate address bus(es). If data was addressed in the R1 phase, the read 2 (R2) hardware fetches that data by way of the appropriate data bus(es). In the execute (E) phase, the CPU performs all multiplier, shifter, and ALU operations. This includes all the prime arithmetic and logic operations involving the accumulator and product register. For operations that involve reading a value, modifying it, and writing it back to the original location, the modification (typically an arithmetic or a logical operation) is performed during the E phase of the pipeline. Any CPU register values used by the multiplier, shifter, and ALU are read from the registers at the beginning of the E phase. A result that is to be written to a CPU register is written to the register at the end of the E phase. If a transferred value or result is to be written to memory, the write occurs in the write (W) phase. The CPU drives the destination address, the appropriate write strobes, and the data to be written. The actual storing, which takes at least one more clock cycle, is handled by memory wrappers or peripheral interface logic and is not visible as a part of the CPU pipeline.
Write (W)
Pipeline
4-3
Although every instruction passes through the eight phases, not every phase is active for a given instruction. Some instructions complete their operations in the decode 2 phase, others in the execute phase, and still others in the write phase. For example, instructions that do not read from memory perform no operations in the read phases, and instructions that do not write to memory perform no operation in the write phase. Because different instructions perform modifications to memory and registers during different phases of their completion, an unprotected pipeline could lead to reads and writes at the same location happening out of the intended order. The CPU automatically adds inactive cycles to ensure that these reads and writes happen as intended. For more details about pipeline protection, see section 4.4 on page 4-12.
4.1.1
Decoupled Pipeline Segments

The fetch 1 through decode 1 (F1D1) hardware acts independently of the decode 2 through write (D2W) hardware. This allows the CPU to continue fetching instructions when the D2W phases are halted. It also allows fetched instructions to continue through their D2W phases when fetching of new instructions is delayed. Events that cause portions of the pipeline to halt are described in section 4.3. Instructions in their fetch 1, fetch 2, and decode 1 phases are discarded if an interrupt or other program-flow discontinuity occurs. An instruction that reaches its decode 2 phase always runs to completion before any program-flow discontinuity is taken.
4.1.2
Instruction-Fetch Mechanism
Certain branch instructions perform prefetching. The first few instructions of the branch destination will be fetched but not allowed to reach D2 until it is known whether the discontinuity will be taken. The instruction-fetch mechanism is the hardware for the F1 and F2 pipeline phases. During the F1 phase, the mechanism drives an address on the program address bus (PAB). During the F2 phase, it reads from the program-read data bus (PRDB). While an instruction is read from program memory in the F2 phase, the address for the next fetch is placed on the program address bus (during the next F1 phase). The instruction-fetch mechanism contains an instruction-fetch queue of four 32-bit registers. During the F2 phase, the fetched instruction is added to the queue, which behaves like a first-in, first-out (FIFO) buffer. The first instruction in the queue is the first to be executed. The instruction-fetch mechanism performs 32-bit fetches until the queue is full. When a program-flow discontinuity
4-4
(such as a branch or an interrupt) occurs, the queue is emptied. When the instruction at the bottom of the queue reaches its D2 phase, that instruction is passed to the instruction register for further decoding.
4.1.3
Address Counters FC, IC, and PC

Three program-address counters are involved in the fetching and execution of instructions:
- Fetch counter (FC). The fetch counter contains the address that is driven
on the program address bus (PAB) in the F1 pipeline phase. The CPU continually increments the FC until the queue is full or the queue is emptied by a program-flow discontinuity. Generally, the FC holds an even address and is incremented by 2, to accommodate 32-bit fetches. The only exception to this is when the code after a discontinuity begins at an odd address. In this case, the FC holds the odd address. After performing a16-bit fetch at the odd address, the CPU increments the FC by 1 and resumes 32-bit fetching at even addresses.
- Instruction counter (IC). After the D1 hardware determines the instruc-
tion size (16-bit or 32-bit), it fills the instruction counter (IC) with the address of the next instruction to undergo D2 decoding. On an interrupt or call operation, the IC value represents the return address, which is saved to the stack, to auxiliary register XAR7, or to RPC.
- Program counter (PC). When a new address is loaded into the IC, the
previous IC value is loaded into the PC. The program counter (PC) always contains the address of the instruction that has reached its D2 phase. Example 41 shows the relationship between the pipeline and the address counters. Instruction 1 has reached its D2 phase (it has been passed to the instruction register). The PC points to the address from which instruction 1 was taken (00 005016). Instruction 2 has reached its D1 phase and will be executed next (assuming no program-flow discontinuity flushes the instruction-fetch queue). The IC points to the address from which instruction 2 was taken (00 005116). Instruction 3 is in its F2 phase. It has been transferred to the instruction-fetch queue but has not been decoded. Instructions 4 and 5 are each in their F1 phase. The FC address (00 005416) is being driven on the PAB. During the next 32-bit fetch, Instructions 4 and 5 will be transferred from addresses 00 005416 and 00 005516 to the queue.
Pipeline 4-5
Example 41. Relationship Between Pipeline and Address Counters FC, IC, and PC
Program memory (32 bits wide)
IC
00 005116 00 005316 00 005516 00 005716 00 005916 00 005B16 00 005D16
Instruction 2 Instruction 5
Instruction 1 Instruction 3 Instruction 4
00 005016 00 005216 00 005416 00 005616 00 005816 00 005A16 00 005C16
IC FC
Instruction 7 Instruction 6 Instruction 8 Instruction 9 Instruction 11 . . . Instruction 10 . . .
Instruction-fetch queue (32 bits wide)
F1: Instructions 4 and 5 F2: Instruction 3 D1: Instruction 2 Instruction 2 Instruction register (32 bits wide) D2: Instruction 1 Instruction 1 Instruction 3
The remainder of this document refers almost exclusively to the PC. The FC and the IC are visible in only limited ways. For example, when a call is executed or an interrupt is initiated, the IC value is saved to the stack or to auxiliary register XAR7.
4-6
Visualizing Pipeline Activity
4.2 Visualizing Pipeline Activity

Consider Example 42, which lists eight instructions, I1I8, and shows a diagram of the pipeline activity for those instructions. The F1 column shows addresses and the F2 column shows the instruction opcodes read at those addresses. During an instruction fetch, 32 bits are read, 16 bits from the specified address and 16 bits from the following address. The D1 column shows instructions being isolated in the instruction-fetch queue, and the D2 column indicates address generation and modification of address registers. The Instruction column shows the instructions that have reached the D2 phase. The R1 column shows addresses, and the R2 column shows the data values being read from those addresses. In the E column, the diagram shows results being written to the low half of the accumulator (AL). In the W column, address and a data values are driven simultaneously on the appropriate memory buses. For example, in the last active W phase of the diagram, the address 00 020516 is driven on the data-write address bus (DWAB), and the data value 123416 is driven on the data-write data bus (DWDB). The highlighted blocks in Example 42 indicate the path taken by the instruction ADD AL,*AR0++. That path can be summarized as follows:
Phase F1 F2 Activity Shown Drive address 00 004216 on the program address bus (PAB). Read the opcodes F347 and F348 from addresses 00 004216 and 00 004316, respectively. Isolate F348 in the instruction-fetch queue. Use XAR0 = 006616 to generate source address 0000 006616 and then increment XAR0 to 006716. Drive address 00 006616 on the data-read data bus (DRDB). Read the data value 1 from address 0000 006616. Add 1 to content of AL (123016) and store result (123116) to AL. No activity
D1 D2
R1 R2 E W
Pipeline
4-7
Example 42. Diagramming Pipeline Activity

Address 00 0040 00 0041 00 0042 00 0043 00 0044 00 0045 00 0046 00 0047 Opcode F345 F346 F347 F348 F349 F34A F34B F34C Instruction I1: I2: I3: I4: I5: I6: I7: I8: MOV MOV MOVB ADD MOV ADD MOV ADD DP,#VarA ; DP = page that has VarA. AL,@VarA ; Move content of VarA to AL. AR0,#VarB ; AR0 points to VarB. AL,*XAR0++ ; Add content of VarB to ; AL, and add 1 to XAR0. @VarC,AL ; Replace content of VarC ; with content of AL. AL,*XAR0++ ; Add content of (VarB + 1) ; to AL, and add 1 to XAR0. @VarD,AL ; Replace content of VarD ; with content of AL. AL,*XAR0 ; Add content of (VarB + 2) ; to AL. Initial Values VarA address VarA = 1230 VarB address VarB = 0001 (VarB + 1) = (VarB + 2) = VarC address VarD address = 00 0203 = 00 0066 0003 0005 = 00 0204 = 00 0205
F1
00 0040
F2
D1
Instruction
D2
R1
R2
F346:F345 00 0042 F348:F347 00 0044 F345 F346 F347 I1: MOV I2: MOV DP,#VarA AL,@VarA DP = 8 Generate VarA address XAR0 = 66
F34A:F349
F348 B
I3: MOVB XAR0,#Var
00 0203
00 0046
F349 + F34C:F34B F34A
I4: ADD
AL,*XAR0+
XAR0 = 67
1230
I5: MOV
@VarC,AL
Generate VarC address XAR0 = 68
00 0066
AL = 1230
F34B + F34C
I6: ADD
AL,*XAR0+
0001
I7: MOV
@VarD,AL
Generate VarD address XAR0 = 68
00 0067
AL = 1231
I8: ADD
AL,*XAR0
00 0068
0003
AL = 1234
00 0204 1231
0005
AL = 1239
00 0205 1234
4-8
F1
F2
D1
Instruction
D2
R1
R2
Note:
The opcodes shown in the F2 and D1 columns were chosen for illustrative purposes; they are not the actual opcodes of the instructions shown.
The pipeline activity in Example 42 can also be represented by the simplified diagram in Example 43. This type of diagram is useful if your focus is on the path of each instruction rather than on specific pipeline events. In cycle 8, the pipeline is full: there is an instruction in every pipeline phase. Also, the effective execution time for each of these instructions is one cycle. Some instructions finish their activity at the D2 phase, some at the E phase, and some at the W phase. However, if you choose one phase as a reference, you can see that each instruction is in that phase for one cycle.
Example 43. Simplified Diagram of Pipeline Activity

F1 F2 D1 D2 R1 R2 E W Cycle
I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8 I1 I2 I3 I4 I5 I6 I7 I8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pipeline
4-9
Freezes in Pipeline Activity
4.3 Freezes in Pipeline Activity

This section describes the two causes for freezes in pipeline activity:
- Wait states - An instruction-not-available condition
4.3.1
Wait States
When the CPU requests a read from or write to a memory device or peripheral device, that device may take more time to finish the data transfer than the CPU allots by default. Each device must use one of the CPU ready signals to insert wait states into the data transfer when it needs more time. The CPU has three independent sets of ready signals: one set for reads from and writes to program space, a second set for reads from data space, and a third set for writes to data space. Wait-state requests freeze a portion of the pipeline if they are received during the F1, R1, or W phase of an instruction:
- Wait states in the F1 phase. The instruction-fetch mechanism halts until
the wait states are completed. This halt effectively freezes activity for instructions in their F1, F2, and D1 phases. However, because the F1D1 hardware and the D2W hardware are decoupled, instructions that are in their D2W phases continue to execute.
- Wait states in the R1 phase. All D2W activities of the pipeline freeze.
This is necessary because subsequent instructions can depend on the data-read taking place. Instruction fetching continues until the instructionfetch queue is full or a wait-state request is received during an F1 phase.
- Wait states in the W phase. All D2W activity in the pipeline freezes. This
is necessary because subsequent instructions may depend on the write operation happening first. Instruction fetching continues until the instruction-fetch queue is full or a wait-state request is received during an F1 phase.
4.3.2
Instruction-Not-Available Condition
The D2 hardware requests an instruction from the instruction-fetch queue. If a new instruction has been fetched and has completed its D1 phase, the instruction is loaded into the instruction register for more decoding. However, if a new instruction is not waiting in the queue, an instruction-not-available condition exists. Activity in the F1D1 hardware continues. However, the activity in the D2W hardware ceases until a new instruction is available.
4-10
Freezes in Pipeline Activity
One time that an instruction-not-available condition will occur is when the first instruction after a discontinuity is at an odd address and has 32 bits. A discontinuity is a break in sequential program flow, generally caused by a branch, a call, a return, or an interrupt. When a discontinuity occurs, the instruction-fetch queue is emptied, and the CPU branches to a specified address. If the specified address is an odd address, a 16-bit fetch is performed at the odd address, followed by 32-bit fetches at subsequent even addresses. Thus, if the first instruction after a discontinuity is at an odd address and has 32 bits, two fetches are required to get the entire instruction. The D2W hardware ceases until the instruction is ready to enter the D2 phase. To avoid the delay where possible, you can begin each block of code with one or two (preferably two) 16-bit instructions:
FunctionA: 16-bit instruction 16-bit instruction 32-bit instruction . . . ; First instruction ; Second instruction ; 32-bit instructions can start here
If you choose to use a 32-bit instruction as the first instruction of a function or subroutine, you can prevent a pipeline delay only by making sure the instruction begins at an even address.
Pipeline
4-11
Pipeline Protection
4.4 Pipeline Protection

Instructions are being executed in parallel in the pipeline, and different instructions perform modifications to memory and registers during different phases of completion. In an unprotected pipeline, this could lead to pipeline conflicts reads and writes at the same location happening out of the intended order. However, the C28x pipeline has a mechanism that automatically protects against pipeline conflicts. There are two types of pipeline conflicts that can occur on the C28x:
- Conflicts during reads and writes to the same data-space location - Register conflicts
The pipeline prevents these conflicts by adding inactive cycles between instructions that would cause the conflicts. Sections 4.4.1 and 4.4.2 explain the circumstances under which these pipeline-protection cycles are added and tells how to avoid them, so that you can reduce the number of inactive cycles in your programs.
4.4.1
Protection During Reads and Writes to the Same Data-Space Location

Consider two instructions, A and B. Instruction A writes a value to a memory location during its W phase. Instruction B must read that value from the same location during its R1 and R2 phases. Because the instructions are being executed in parallel, it is possible that the R1 phase of instruction B could occur before the W phase of instruction A. Without pipeline protection, instruction B could read too early and fetch the wrong value. The C28x pipeline prevents that read by holding instruction B in its D2 phase until instruction A is finished writing. Example 44 shows a conflict between two instructions that are accessing the same data-memory location. The pipeline activity shown is for an unprotected pipeline. For convenience, the F1D1 phases are not shown. I1 writes to VarA during cycle 5. Data memory completes the store in cycle 6. I2 should not read the data-memory location any sooner than cycle 7. However, I2 performs the read during cycle 4 (three cycles too early). To prevent this kind of conflict, the pipeline-protection mechanism would hold I2 in the D2 phase for 3 cycles. During these pipeline-protection cycles, no new operations occur.
4-12
Pipeline Protection
Example 44. Conflict Between a Read From and a Write to Same Memory Location
I1: I2: DZ MOV @VarA,AL ; Write AL to datamemory location MOV AH,@VarA ; Read same location, store value in AH Kl RZ E W Cycle
I1 I2 I2 I2 I2 I2 I2 I2 I1 I1 I1 I1
1 2 3 4 5 6 7 8
You can reduce or eliminate these types of pipeline-protection cycles if you can take other instructions in your program and insert them between the instructions that conflict. Of course, the inserted instructions must not cause conflicts of their own or cause improper execution of the instructions that follow them. For example, the code in Example 44 could be improved by moving a CLRC instruction to the position between the MOV instructions (assume that the instructions following CLRC SXM operate correctly with SXM = 0):
I1: I2: MOV @VarA,AL ; Write AL to datamemory location CLRC SXM ; SXM = 0 (sign extension off) MOV AH,@VarA ; Read same location, store value in AH
Inserting the CLRC instruction between I1 and I2 reduces the number of pipeline-protection cycles to two. Inserting two more instructions would remove the need for pipeline protection. As a general rule, if a read operation occurs within three instructions from a write operation to the same memory location, the pipeline protection mechanism adds at least one inactive cycle.
4.4.2
Protection Against Register Conflicts

All reads from and writes to CPU registers occur in either the D2 phase or the E phase of an instruction. A register conflict arises when an instruction attempts to read and/or modify the content of a register (in the D2 phase) before a previous instruction has written to that register (in the E phase). The pipeline-protection mechanism resolves register conflicts by holding the later instruction in its D2 phase for as many cycles as needed (one to three). You do not have to consider register conflicts unless you wish to achieve maximum pipeline efficiency. If you choose to reduce the number of pipeline-protection cycles, you can identify the pipeline phases in which registers are accessed and try to move conflicting instructions away from each other.
Pipeline 4-13
Pipeline Protection
Generally, a register conflict involves one of the address registers:

-
16-bit auxiliary registers AR0AR7 32-bit auxiliary registers XAR0XAR7 16-bit data page pointer (DP) 16-bit stack pointer (SP)
Example 45 shows a register conflict involving auxiliary register XAR0. The pipeline activity shown is for an unprotected pipeline, and for convenience, the F1D1 phases are not shown. I1 writes to XAR0 at the end of cycle 4. I2 should not attempt to read XAR0 until cycle 5. However, I2 reads XAR0 (to generate an address) during cycle 2. To prevent this conflict, the pipeline-protection mechanism would hold I2 in the D2 phase for three cycles. During these cycles, no new operations occur.
Example 45. Register Conflict

I1: MOVB AR0,@7 ; Load AR0 with the value addressed by ; the operand @7 and clear the upper ; half of XAR0. ; Load AH with the value pointed to by ; XAR0. R2 E W Cycle
I2: MOV AH,*XAR0 D2 R1
I1 I2 I2 I2 I2 I2 I2 I1 I1 I1 I1
1 2 3 4 5 6 7
You can reduce or eliminate pipeline-protection cycles due to a register conflict by inserting other instructions between the instructions that cause the conflict. For example, the code in Example 45 could be improved by moving two other instructions from elsewhere in the program (assume that the instructions following SETC SXM operate correctly with PM = 1 and SXM = 1):
I1: MOVB AR0,@7 ; ; ; ; ; Load AR0 with the value addressed by the operand @7 and clear the upper half of XAR0. PM = 1 (no product shift) SXM = 1 (sign extension on) ; Load AH with the value pointed to by ; AR0.
SPM 0 SETC SXM I2: MOV AH,*XAR0
Inserting the SPM and SETC instructions reduces the number of pipelineprotection cycles to one. Inserting one more instruction would remove the
4-14
Pipeline Protection
need for pipeline protection. As a general rule, if a read operation occurs within three instructions from a write operation to the same register, the pipelineprotection mechanism adds at least one inactive cycle.
Pipeline
4-15
Avoiding Unprotected Operations
4.5 Avoiding Unprotected Operations

This section describes pipeline conflicts that the pipeline-protection mechanism does not protect against. These conflicts are avoidable, and this section offers suggestions for avoiding them.
4.5.1
Unprotected Program-Space Reads and Writes

The pipeline protects only register and data-space reads and writes. It does not protect the program-space reads done by the PREAD and MAC instructions or the program-space write done by the PWRITE instruction. Be careful with these instructions when using them to access a memory block that is shared by data space and program space. As an example, suppose a memory location can be accessed at address 00 0D5016 in program space and address 0000 0D5016 in data space. Consider the following lines of code:
; XAR7 = 000D50 in program space ; Data1 = 000D50 in data space ADD @Data1,AH ; Store AH to datamemory location ; Data1. PREAD @AR1,*XAR7 ; Load AR1 from programmemory ; location given by XAR7.
The operands @Data1 and *XAR7 are referencing the same location, but the pipeline cannot interpret this fact. The PREAD instruction reads from the memory location (in the R2 phase) before the ADD writes to the memory location (in the W phase). However, the PREAD is not necessary in this program. Because the location can be accessed by an instruction that reads from data space, you can use another instruction, such as a MOV instruction:
ADD MOV @Data1,AH AR1,*XAR7 ; Store AH to memory location Data1. ; Load AR1 from memory location ; given by XAR7.
4.5.2
An Access to One Location That Affects Another Location

If an access to one location affects another location, you may need to correct your program to prevent a pipeline conflict. You only need to be concerned about this kind of pipeline conflict if you are addressing a location outside of a protected address range. (See section 4.5.3.). Consider the following example:
; ; $10: TBIT @DataB,#15 ; SB $10,NTC ; MOV @DataA,#4 This write to DataA causes a peripheral to clear bit 15 of DataB. Test bit 15 of DataB. Loop until bit 15 is set.
4-16
This program causes a misread. The TBIT instruction reads bit 15 (in the R2 phase) before the MOV instruction writes to bit 15 (in the W phase). If the TBIT instruction reads a 1, the code prematurely ends the loop. Because DataA and DataB reference different data-memory locations, the pipeline does not identify this conflict. However, you can correct this type of error by inserting two or more NOP (no operation) instructions to allow for the delay between the write to DataA and the change to bit 15 of DataB. For example, if a 2-cycle delay is sufficient, you can fix the previous code as follows:
; ; NOP ; NOP ; $10: TBIT @DataB,#15 ; SB $10,NTC ; MOV @DataA,#4 This write to DataA causes a peripheral to clear bit 15 of DataB. Delay by 1 cycle. Delay by 1 cycle. Test bit 15 of DataB. Loop until bit 15 is set.
4.5.3
Write Followed By Read Protection Mode

The CPU contains a write followed by read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated. See your device data sheet for device-specific information about which memory region is write-followed-by-read protected. The PROTSTART(15:0) and PROTRANGE(15:0) input signals set the protection range. The PROTRANGE(15:0) value is a binary multiple with the smallest block size being 64 words, and the largest being 4M words (64 words, 128 words, 256 words ...1M words, 2M words, 4M words). The PROTSTART address must always be a multiple of the chosen range. For example, if a 4K block size is selected, then the start address must be a multiple of 4K. The ENPROT signal enables this feature (when set high), it disables this feature (when set low) All of the above signals are latched on every cycle. The above signals are connected to registers and can be changed within the application program. The above mechanism only works for reads that follow writes to the protected area. Reads and write sequences to unprotected areas are not affected, as shown in the following examples.
Pipeline
4-17
Example 1: write protected_area write protected_area write protected_area < pipe protection (3 cycles) read protected_area Example 2: write protected_area write protected_area write protected_area < no pipe protection invoked read non_protected_area < pipe protection (2 cycles) read protected_area read protected_area Example 3: write non_protected_area write non_protected_area write non_protected_area < no pipe protection invoked read protected_area
4-18
Chapter 5
C28x Addressing Modes

This chapter describes the addressing modes of the C28x and provides examples.
Topic
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Page
Types of Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Addressing Modes Select Bit (AMODE) . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Assembler/Compiler Tracking of AMODE Bit . . . . . . . . . . . . . . . . . . . . 5-7 Direct Addressing Modes (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Stack Addressing Modes (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Register Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Data/Program/IO space Immediate Addressing Modes . . . . . . . . . . 5-28 Program Space Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . 5-30
5.10 Byte Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.11 Alignment of 32-Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5-1
Types of Addressing Modes
5.1 Types of Addressing Modes

The C28x CPU supports four basic types of addressing modes:
- Direct Addressing Mode
DP (data page pointer): In this mode, the 16-bit DP register behaves like a fixed page pointer. The instruction supplies a 6-bit or 7-bit offset field, which is concatenated with the value in the DP register. This type of addressing is useful for accessing fixed address data structures, such as peripheral registers and global or static variables in C/C++.
- Stack Addressing Mode
SP (stack pointer): In this mode, the 16-bit SP pointer is used to access information on the software stack. The software stack grows from low to high memory on the C28x and the stack pointer always points to the next empty location. The instruction supplies a 6-bit offset field that is subtracted from the current stack pointer value for accessing data on the stack or the stack pointer can be post-incremented or pre-decremented when pushing and popping data from the stack, respectively.
- Indirect Addressing Mode
XAR0 to XAR7 (auxiliary register pointers): In this mode, the 32-bit XARn registers behave as generic data pointers. The instruction can direct to post-increment, pre/post-decrement, or index from the current register contents with either a 3-bit immediate offset field or with the contents of another 16-bit register.
- Register Addressing Mode
In this mode, another register can be the source or destination operand of an access. This enables register-to-register operations in the C28x architecture. On most C28x instructions, an 8-bit field in the instruction op-code selects the addressing mode to use and what modification to make to that mode. In the C28x instruction set, this field is referred to as:
- loc16
Selects Direct/Stack/Indirect/Register addressing mode for 16-bit data access.

- loc32
Selects Direct/Stack/Indirect/Register addressing mode for 32-bit data access.

5-2
Types of Addressing Modes
An example C28x instruction description, which uses the above, would be:
- ADD
AL,loc16
Take the 16-bit contents of AL register, add the contents of 16-bit location specified by the loc16 field and store the contents in AL register.
- ADDL
loc32,ACC
Take the 32-bit contents of the location pointed to by the loc32 field, add the contents of the 32-bit ACC register, and store the result back into the location specified by the loc32 field. Other types of addressing modes supported are:
- Data/Program/IO Space Immediate Addressing Modes:
In this mode, the address of the memory operand is embedded in the instruction.
- Program Space Indirect Addressing Modes:
Some instructions can access a memory operand located in program space using an indirect pointer. Since memory is unified on the C28x CPU, this enables the reading of two operands in a single cycle. Only a small number of instructions use the above modes and typically they are in combination with the loc16/loc32 modes. The following sections contain detailed descriptions of the addressing modes with example instructions. For more information about the instructions shown in examples throughout this chapter, see Chapter 6, Assembly Language Instructions.
5-3
Addressing Modes Select Bit (AMODE)
5.2 Addressing Modes Select Bit (AMODE)

To accommodate various types of addressing modes, an addressing mode bit (AMODE) selects the decoding of the 8-bit field (loc16/loc32). This bit is found in Status Register 1 (ST1). The addressing modes have been broadly classified as follows:
- AMODE = 0
This is the default mode on reset and is the mode used by the C28x C/C++ compiler. This mode is not fully compatible to the C2xLP CPU addressing modes. The data page pointer offset is 6-bits (it is 7-bits on the C2xLP) and not all of the indirect addressing modes are supported.
- AMODE = 1
This mode contains addressing modes that are fully compatible to the C2xLP device. The data page pointer offset is increased to 7-bits and all of the indirect addressing modes available on the C2xLP are supported. The available addressing modes, for the loc16 or loc32 field, are summarized in Table 51.
Table 51. Addressing Modes for loc16 or loc32

AMODE = 0 8-Bit Decode loc16/loc32 Syntax 8-Bit Decode AMODE = 1 loc16/loc32 Syntax
Direct Addressing Modes (DP): 0 0 III III @6bit 0 I III III @@7bit
Stack Addressing Modes (SP): 0 1 III III 1 0 111 101 1 0 111 110 *SP[6bit] *SP++ *SP 1 0 111 101 1 0 111 110 *SP++ *SP
C28x Indirect Addressing Modes (XAR0 to XAR7): 1 0 000 AAA 1 0 001 AAA 1 0 010 AAA 1 0 011 AAA 1 1 III AAA *XARn++ *XARn *+XARn[AR0] *+XARn[AR1] *+XARn[3bit] 1 0 000 AAA 1 0 001 AAA 1 0 010 AAA 1 0 011 AAA *XARn++ *XARn *+XARn[AR0] *+XARn[AR1]
5-4

C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7): 1 0 111 000 1 0 111 001 1 0 111 010 1 0 111 011 1 0 111 100 1 0 101 110 1 0 101 111 1 0 110 RRR * *++ * *0++ *0 *BR0++ *BR0 *,ARPn 1 0 111 000 1 0 111 001 1 0 111 010 1 0 111 011 1 0 111 100 1 0 101 110 1 0 101 111 1 0 110 RRR 1 1 000 RRR 1 1 001 RRR 1 1 010 RRR 1 1 011 RRR 1 1 100 RRR 1 1 101 RRR Circular Indirect Addressing Modes (XAR6, XAR1): 1 0 111 111 *AR6%++ 1 0 111 111 *+XAR6[AR1%++] * *++ * *0++ *0 *BR0++ *BR0 *,ARPn *++,ARPn *,ARPn *0++,ARPn *0,ARPn *BR0++,ARPn *BR0,ARPn
32-Bit Register Addressing Modes (XAR0 to XAR7, ACC, P, XT): 1 0 100 AAA 1 0 101 001 1 0 101 011 1 0 101 100 @XARn @ACC @P @XT 1 0 100 AAA 1 0 101 001 1 0 101 011 1 0 101 100 @XARn @ACC @P @XT
5-5

16-Bit Register Addressing Modes (AR0 to AR7, AH, AL, PH, PL, TH, SP): 1 0 100 AAA 1 0 101 000 1 0 101 001 1 0 101 010 1 0 101 011 1 0 101 100 1 0 101 101 @ARn @AH @AL @PH @PL @TH @SP 1 0 100 AAA 1 0 101 000 1 0 101 001 1 0 101 010 1 0 101 011 1 0 101 100 1 0 101 101 @ARn @AH @AL @PH @PL @TH
@SP
In the C28x Indirect addressing modes, the auxiliary register pointer used in the addressing mode is implicitly specified. In the C2xLP Indirect addressing modes, a 3-bit pointer called the auxiliary register pointer (ARP) is used to select which of the auxiliary registers is currently used and which pointer is used in the next operation. The examples below illustrate the differences between the C28x Indirect and C2xLP Indirect addressing modes:
- ADD
AL,*XAR4++
Read the contents of 16-bit memory location pointed to by register XAR4, add the contents to AL register. Post-increment the contents of XAR4 by 1.
- ADD
AL,*++
Assume ARP pointer in ST1 contains the value 4. Read the contents of 16-bit memory location pointed to by register XAR4, add the contents to AL register. Post-increment the contents of XAR4 by 1.
- ADD
AL,*++,ARP5
Assume ARP pointer in ST1 contains the value 4. Read the contents of 16-bit memory location pointed to by register XAR4, add the contents to AL register. Post-increment the contents of XAR4 by 1. Set the ARP pointer to 5. Now it points to XAR5. On the C28x instruction syntax, the destination operand is always on the left and the source operands are always on the right.
5-6
Assembler/Compiler Tracking of AMODE Bit
5.3 Assembler/Compiler Tracking of AMODE Bit

The compiler will always assume the addressing mode is set to AMODE = 0 and therefore will only use addressing modes that are valid for AMODE = 0. The assembler can be instructed, via the command line options, to default to either AMODE = 0 or AMODE = 1. The command line options are: v28 v28 m20 Assumes AMODE = 0 (C28x addressing modes). Assumes AMODE = 1 (full C2xLP compatible addressing modes.
Additionally, the assembler allows directives to be embedded within a file to instruct the assembler to override the default mode and change syntax checking to the new address mode setting: .c28_amode .lp_amode Tells assembler that any code that follows assumes AMODE = 0 (C28x addressing modes). Tells assembler that any code that follows assumes AMODE = 1 (full C2xLP compatible addressing modes)
The above directives cannot be nested. The above directives can be used as follows within an assembly program:
; File assembled using v28 option (assume AMODE . ; This section of code can only use ; addressing modes . . . . SETC AMODE ; Change to AMODE = 1 .lp_amode ; Tell assembler to check for AMODE . ; This section of code can only use ; addressing modes . . . . CLRC AMODE ; Revert back to AMODE = 0 .c28_amode ; Tell assembler to check for AMODE . ; This section of code can only use ; addressing modes . . . . ; End of file. = 0): AMODE = 0
= 1 syntax AMODE = 1
= 1 syntax AMODE = 0
5-7
Direct Addressing Modes (DP)
5.4 Direct Addressing Modes (DP)

AMODE 0 loc16/loc32 Syntax @6bit Description 32bitDataAddr(31:22) = 0 32bitDataAddr(21:6) = DP(15:0) 32bitDataAddr(5:0)
Note:
= 6bit
The 6-bit offset value is concatenated with the 16-bit DP register. The offset value enables 0 to 63 words to be addressed relative to the current DP register value.
Example(s): MOVW DP,#VarA ADD AL,@VarA MOV @VarB,AL MOVW SUB MOV DP,#VarC AL,@VarC @VarD,AL
; ; ; ; ; ; ; ; ;
Load DP pointer with page value containing VarA Add memory location VarA to register AL Store AL into memory location VarB VarB is located in the same 64word page as VarA Load DP pointer with page value containing VarC Subtract memory location VarC from register AL Store AL into memory location VarD VarC is located in the same 64word page as VarD VarC & D are in different pages than VarA & B Description 32bitDataAddr(31:22) = 0 32bitDataAddr(21:7) = DP(15:1) 32bitDataAddr(6:0)
Note:
AMODE 1
loc16/loc32 Syntax @@7bit
= 7bit
The 7-bit offset value is concatenated with the upper 15-bits of the DP register. Bit 0 of DP register is ignored and is not affected by the operation. The offset value enables 0 to 127 words to be addressed relative to the current DP register value.
Example(s): SETC AMODE .lp_amode MOVW DP,#VarA ADD AL,@@VarA MOV @@VarB,AL MOVW SUB MOV DP,#VarC AL,@@VarC @@VarD,AL
; ; ; ; ; ; ; ; ; ; ;
Make sure AMODE = 1 Tell assembler that AMODE = 1 Load DP pointer with page value containing VarA Add memory location VarA to register AL Store AL into memory location VarB VarB is located in the same 128word page as VarA Load DP pointer with page value containing VarC Subtract memory location VarC from register AL Store AL into memory location VarD VarC is located in the same 128word page as VarD VarC & D are in different pages than VarA & B
Note:
The direct addressing mode can access only the lower 4M of data address space on the C28x device.
5-8
Stack Addressing Modes (SP)
5.5 Stack Addressing Modes (SP)

AMODE 0 loc16/loc32 Syntax Description 32bitDataAddr(31:16) = 0x0000 32bitDataAddr(15:0) = SP 6bit
Note: The 6-bit offset value is subtracted from the current 16-bit SP register value. The offset value enables 0 to 63 words to be addressed relative to the current SP register value.
*SP[6bit]
Example(s): ADD AL,*SP[5] MOV ADDL MOVL *-SP[8],AL ACC,*SP[12] *-SP[34],ACC
; ; ; ; ; ; ; ;
Add 16-bit contents from stack location 5 words from top of stack to AL register Store 16-bit AL register to stack location -8 words from top of stack Add 32-bit contents from stack location 12 words from top of stack to ACC register. Store 32-bit ACC register to stack location 34 words from top of stack Description 32bitDataAddr(31:16) = 0x0000 32bitDataAddr(15:0) = SP if(loc16), SP = SP + 1 if(loc32), SP = SP + 2
AMODE X
loc16/loc32 Syntax *SP++
Example(s): MOV *SP++,AL MOVL *SP++,P
; ; ; ;
Push contents of 16-bit AL register onto top of stack Push contents of 32-bit P register onto top of stack Description if(loc16), SP = SP 1 if(loc32), SP = SP 2 32bitDataAddr(31:16) = 0x0000 32bitDataAddr(15:0) = SP
AMODE X
loc16/loc32 Syntax *SP
Example(s): ADD AL,*SP MOVL

Note:
ACC,*SP
; ; ; ;
Pop contents from top of stack and add to 16-bit AL register Pop contents from top of stack and store in 32-bit ACC register
This addressing mode can only access the lower 64K of data address space on the C28x device.
5-9
Indirect Addressing Modes
5.6 Indirect Addressing Modes

This section includes indirect addressing modes for the 28x and 2xLP devices. It also includes circular indirect addressing modes.
5.6.1
C28x Indirect Addressing Modes (XAR0 to XAR7)

loc16/loc32 Syntax *XARn++ Description ARP = n 32bitDataAddr(31:0) = XARn if(loc16), XARn = XARn + 1 if(loc32), XARn = XARn + 2
AMODE X
Example(s): MOVL MOVL MOV Loop: MOVL MOVL BANZ
XAR2,#Array1 XAR3,#Array2 @AR0,#N1 ACC,*XAR2++ *XAR3++,ACC Loop,AR0
; Load XAR2 with start address of Array1 ; Load XAR3 with start address of Array2 ; Load AR0 with loop count N ; ; ; ; ; Load ACC with location pointed to by XAR2, postincrement XAR2 Store ACC into location pointed to by XAR3, postincrement XAR3 Loop until AR0 == 0, postdecrement AR0
AMODE X
loc16/loc32 Syntax *XARn
Description ARP = n if(loc16), XARn = XARn 1 if(loc32), XARn = XARn 2 32bitDataAddr(31:0) = XARn
Example(s): MOVL MOVL MOV Loop: MOVL MOVL BANZ
XAR2,#Array1+N*2 ; Load XAR2 with end address of Array1 XAR3,#Array2+N*2 ; Load XAR3 with end address of Array2 @AR0,#N1 ; Load AR0 with loop count N ACC,*XAR2 *XAR3,ACC Loop,AR0 ; ; ; ; ; Predecrement XAR2, load ACC with location pointed to by XAR2 Predecrement XAR3, store ACC into location pointed to by XAR3, Loop until AR0 == 0, postdecrement AR0
5-10
AMODE X
loc16/loc32 Syntax *+XARn[AR0]
Description ARP = n 32bitDataAddr(31:0) = XARn + AR0

Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 are ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XARn can occur.
Example(s): MOVW MOVL MOVB MOVB MOVL MOVL MOVL MOVL AMODE X
DP,#Array1Ptr XAR2,@Array1Ptr XAR0,#16 XAR1,#68 ACC,*+XAR2[AR0] P,*+XAR2[AR1] *+XAR2[AR1],ACC *+XAR2[AR0],P
; Point to Array1 Pointer location ; Load XAR2 with pointer to Array1 ; AR0 = 16, AR0H = 0 ; AR1 = 68, AR1H = 0 ;; Swap contents of location Array1[16] ;; with the contents of location Array1[68] ;; ;; Description ARP = n 32bitDataAddr(31:0) = XARn + AR1
Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 are ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XARn can occur.
loc16/loc32 Syntax *+XARn[AR1]
Example(s): MOVW MOVL MOVB MOVB MOVL MOVL MOVL MOVL
DP,#Array1Ptr XAR2,@Array1Ptr XAR0,#16 XAR1,#68 ACC,*+XAR2[AR0] P,*+XAR2[AR1] *+XAR2[AR1],ACC *+XAR2[AR0],P
; Point to Array1 Pointer location ; Load XAR2 with pointer to Array1 ; AR0 = 16, AR0H = 0 ; AR1 = 68, AR1H = 0 ;; Swap contents of location Array1[16] ;; with the contents of location Array1[68] ;; ;;
AMODE X
loc16/loc32 Syntax *+XARn[3bit]
Description ARP = n 32bitDataAddr(31:0) = XARn + 3bit

Note: The immediate value is treated as an unsigned 3-bit value.
Example(s): MOVW MOVL MOVL MOVL MOVL MOVL

Note:
DP,#Array1Ptr XAR2,@Array1Ptr ACC,*+XAR2[2] P,*+XAR2[5] *+XAR2[5],ACC *+XAR2[2],P
; Point to Array1 Pointer location ; Load XAR2 with pointer to Array1 ;; Swap contents of location Array1[2] ;; with the contents of location Array1[5] ;; ;;
The assembler also accepts *XARn as an addressing mode. This is the same encoding as the *+XARn[0] mode.
5-11
5.6.2
C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7)

loc16/loc32 Syntax * Description 32bitDataAddr(31:0) = XAR(ARP)
Note: The XARn register used is the register pointed to by the current value in the ARP pointer. ARP = 0, points to XAR0, ARP = 1, points to XAR1 and so on.
AMODE X
Example(s): MOVZ DP,#RegAPtr MOVZ AR2,@RegAPtr MOVZ AR3,@RegBPtr
NOP MOV NOP MOV
*,ARP2 *,#0x0404 *,ARP3 *,#0x8000
; ; ; ; ; ; ; ; ; ;
Load DP with page address containing RegAPtr Load AR2 with contents of RegAPtr, AR2H = 0 Load AR3 with contents of RegBPtr, AR3H = 0 RegAPtr and RegBPtr are located in the same 128 word data page. Both are located in the low 64K of data memory space. Set ARP pointer to point to XAR2 Store 0x0404 into location pointed by XAR2 Set ARP pointer to point to XAR3 Store 0x8000 into location pointed by XAR3
AMODE X
loc16/loc32 Syntax *,ARPn
Description 32bitDataAddr(31:0) = XAR(ARP) ARP = n
Example(s): MOVZ DP,#RegAPtr MOVZ AR2,@RegAPtr MOVZ AR3,@RegBPtr
NOP MOV MOV
*,ARP2 *,#0x0404,ARP3 *,#0x8000
; ; ; ; ; ; ; ; ; ;
Load DP with page address containing RegAPtr Load AR2 with contents of RegAPtr, AR2H = 0 Load AR3 with contents of RegBPtr, AR3H = 0 RegAPtr and RegBPtr are located in the same 128 word data page. Both are located in the low 64K of data memory space. Set ARP pointer to point to XAR2 Store 0x0404 into location pointed by XAR2, Set ARP pointer to point to XAR3 Store 0x8000 into location pointed by XAR3
5-12
AMODE X
loc16/loc32 Syntax *++
Description 32bitDataAddr(31:0) = XAR(ARP) if(loc16), XAR(ARP) = XAR(ARP) + 1 if(loc32), XAR(ARP) = XAR(ARP) + 2
Example(s): MOVL MOVL MOV Loop: NOP MOVL NOP MOVL
XAR2,#Array1 XAR3,#Array2 @AR0,#N1 *,ARP2 ACC,*++ *,ARP3 *++,ACC
; Load XAR2 with start address of Array1 ; Load XAR3 with start address of Array2 ; Load AR0 with loop count N ; ; ; ; ; ; ; ; Set ARP pointer to point to XAR2 Load ACC with location pointed to by XAR2, postincrement XAR2 Set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3 Set ARP pointer to point to XAR0 Loop until AR0 == 0, postdecrement AR0
NOP *,ARP0 XBANZ Loop,* AMODE X loc16/loc32 Syntax *++,ARPn
Example(s): MOVL XAR2,#Array1 MOVL XAR3,#Array2 MOV @AR0,#N1 NOP *,ARP2 SETC AMODE .lp_amode Loop: MOVL ACC,*++,ARP3 MOVL XBANZ *++,ACC,ARP0 Loop,*,ARP2
; ; ; ; ; ; ; ; ; ; ; ;
Load XAR2 with start address of Array1 Load XAR3 with start address of Array2 Load AR0 with loop count N Set ARP pointer to point to XAR2 Make sure AMODE = 1 Tell assembler that AMODE = 1 Load ACC with location pointed to by XAR2, postincrement XAR2, set ARP to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3, set ARP to point to XAR0 Loop until AR0 == 0, postdecrement AR0, set ARP pointer to point to XAR2
5-13
AMODE X
loc16/loc32 Syntax *
Example(s): MOVL XAR2,#Array1+(N1)*2 MOVL XAR3,#Array2+(N1)*2 MOV @AR0,#N1 Loop: NOP *,ARP2 MOVL ACC,* NOP MOVL *,ARP3 *,ACC
; Load XAR2 with end address of Array1 ; Load XAR3 with end address of Array2 ; Load AR0 with loop count N ; ; ; ; ; ; ; ; Set ARP pointer to point to XAR2 Load ACC with location pointed to by XAR2, postdecrement XAR2 Set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postdecrement XAR3 Set ARP pointer to point to XAR0 Loop until AR0 == 0, postdecrement AR0
NOP *,ARP0 XBANZ Loop,*
AMODE 1
loc16/loc32 Syntax *,ARPn
Description 32bitDataAddr(31:0) = XAR(ARP) if(loc16), XAR(ARP) = XAR(ARP) + 1 if(loc32), XAR(ARP) = XAR(ARP) + 2 ARP = n
MOVL XAR2,#Array1+(N1)*2 MOVL XAR3,#Array2+(N1)*2 MOV @AR0,#N1 NOP *,ARP2 SETC AMODE .lp_amode Loop: MOVL ACC,*,ARP3
; ; ; ; ; ; ; ; ; ; ; ; ; ;
Load XAR2 with end address of Array1 Load XAR3 with end address of Array2 Load AR0 with loop count N Set ARP pointer to point to XAR2 Make sure AMODE = 1 Tell assembler that AMODE = 1 Load ACC with location pointed to by XAR2, postincrement XAR2, set ARP to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3, set ARP to point to XAR0 Loop until AR0 == 0, postdecrement AR0, set ARP pointer to point to XAR2
MOVL
*,ACC,ARP0
XBANZ
Loop,*,ARP2
5-14
AMODE X
loc16/loc32 Syntax *0++
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP) = XAR(ARP) + AR0

Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XAR(ARP) can occur.
Example(s): MOVL XAR2,#Array1 MOVL XAR3,#Array2 MOV @AR0,#4 MOV Loop: NOP MOVL NOP MOVL *,ARP2 ACC,*0++ *,ARP3 *++,ACC @AR1,#N1
; ; ; ; ; ; ; ; ; ; ; ; ;
Load XAR2 with start address of Array1 Load XAR3 with start address of Array2 Set AR0 to copy every fourth value from Array1 to Array2 Load AR1 with loop count N Set ARP pointer to point to XAR2 Load ACC with location pointed to by XAR2, postincrement XAR2 by AR0 Set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3 Set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1 Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP) = XAR(ARP) + AR0 ARP = n
Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XAR(ARP) can occur.
NOP *,ARP1 XBANZ Loop,* AMODE 1 loc16/loc32 Syntax *0++,ARPn
Example(s): MOVL XAR2,#Array1 MOVL XAR3,#Array2 MOV @AR0,#4 MOV @AR1,#N1 NOP *,ARP2 SETC AMODE .lp_amode Loop: MOVL ACC,*0++,ARP3
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
Load XAR2 with start address of Array1 Load XAR3 with start address of Array2 Set AR0 to copy every fourth value from Array1 to Array2 Load AR1 with loop count N Set ARP pointer to point to XAR2 Make sure AMODE = 1 Tell assembler that AMODE = 1 Load ACC with location pointed to by XAR2, postincrement XAR2 by AR0, set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3, set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1, set ARP to point to XAR2
MOVL
*++,ACC,ARP1
XBANZ
Loop,*,ARP2
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AMODE X
loc16/loc32 Syntax *0
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP) = XAR(ARP) AR0

Note: The lower 16-bits of XAR0 are subtracted from the selected 32-bit register. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value. Underflow into the upper 16-bits of XAR(ARP) can occur.
Example(s): MOVL XAR2,#Array1+(N1)*8 ; Load XAR2 with end address of Array1 MOVL XAR3,#Array2+(N1)*2 ; Load XAR3 with end address of Array2 MOV @AR0,#4 ; Set AR0 to copy every fourth value from ; Array1 to Array2 MOV @AR1,#N1 ; Load AR1 with loop count N Loop: NOP *,ARP2 ; Set ARP pointer to point to XAR2 MOVL ACC,*0 ; Load ACC with location pointed to by ; XAR2, postdecrement XAR2 by AR0 NOP *,ARP3 ; Set ARP pointer to point to XAR3 MOVL *,ACC ; Store ACC into location pointed to by ; XAR3, postdecrement XAR3 NOP *,ARP1 ; Set ARP pointer to point to XAR1 XBANZ Loop,* ; Loop until AR1 == 0, postdecrement AR1
AMODE 1
loc16/loc32 Syntax *0,ARPn
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP) = XAR(ARP) AR0 ARP = n

Note: The lower 16-bits of XAR0 are subtracted from the selected 32-bit register. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value. Underflow into the upper 16-bits of XAR(ARP) can occur.
Example(s): MOVL XAR2,#Array1+(N1)*8 ; Load XAR2 with end address of Array1 MOVL XAR3,#Array2+(N1)*2 ; Load XAR3 with end address of Array2 MOV @AR0,#4 ; Set AR0 to copy every fourth value from ; Array1 to Array2 MOV @AR1,#N1 ; Load AR1 with loop count N NOP *,ARP2 ; Set ARP pointer to point to XAR2 SETC AMODE ; Make sure AMODE = 1 .lp_amode ; Tell assembler that AMODE = 1 Loop: MOVL ACC,*0,ARP3 ; Load ACC with location pointed to by ; XAR2, postdecrement XAR2 by AR0, set ARP ; pointer to point to XAR3 MOVL *,ACC,ARP1 ; Store ACC into location pointed to by ; XAR3, postdecrement XAR3, set ARP ; pointer to point to XAR1 XBANZ Loop,*,ARP2 ; Loop until AR1 == 0, postdecrement AR1, ; set ARP to point to XAR2 5-16
AMODE X
loc16/loc32 Syntax *BR0++
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP)(15:0) = AR(ARP) rcadd AR0 XAR(ARP)(31:16) = unchanged

Note: The lower 16-bits of XAR0 are reverse carry added (rcadd) to the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Upper 16-bits of the selected register unchanged by the operation.
Example(s): ; Transfer contents of Array1 MOVL XAR2,#Array1 ; MOVL XAR3,#Array2 ; MOV @AR0,#N ; ; MOV @AR1,#N1 ; Loop: NOP *,ARP2 ; MOVL ACC,*++ ; ; NOP *,ARP3 ; MOVL *BR0++,ACC ; ; NOP *,ARP1 ; XBANZ Loop,* ;
to Array2 in bit reverse order: Load XAR2 with start address of Array1 Load XAR3 with start address of Array2 Load AR0 with size of array, N must be a multiple of 2 (2,4,8,16,...) Load AR1 with loop count N Set ARP pointer to point to XAR2 Load ACC with location pointed to by XAR2, postincrement XAR2 Set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postincrement XAR3 with AR0 reverse carry add Set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1
AMODE 1
loc16/loc32 Syntax *BR0++,ARPn
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP)(15:0) = AR(ARP) rcadd AR0 XAR(ARP)(31:16) = unchanged ARP = n
Note: The lower 16-bits of XAR0 are reverse carry added (rcadd) to the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Upper 16-bits of the selected register unchanged by the operation.
Example(s): ; Transfer contents of Array1 MOVL XAR2,#Array1 ; MOVL XAR3,#Array2 ; MOV @AR0,#N ; ; MOV @AR1,#N1 ; NOP *,ARP2 ; SETC AMODE ; .lp_amode ; Loop: MOVL ACC,*++,ARP3 ; ; ;
to Array2 in bit reverse order: Load XAR2 with start address of Array1 Load XAR3 with start address of Array2 Load AR0 with size of array, N must be a multiple of 2 (2,4,8,16,...) Load AR1 with loop count N Set ARP pointer to point to XAR2 Make sure AMODE = 1 Tell assembler that AMODE = 1 Load ACC with location pointed to by XAR2, postincrement XAR2, set ARP pointer to point to XAR3
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MOVL
*BR0++,ACC,ARP1 ; ; ; XBANZ Loop,*,ARP2 ; ;
Store ACC into location pointed to by XAR3, postincrement XAR3 with AR0 reverse carry add, set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1, set ARP to point to XAR2
AMODE X
loc16/loc32 Syntax *BR0
Description Address Generation: 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP)(15:0) = AR(ARP) rbsub AR0 {see note [1]} XAR(ARP)(31:16) = unchanged
Note: The lower 16-bits of XAR0 are reverse borrow subtracted (rbsub) from the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Upper 16-bits of the selected register unchanged by the operation.
Example(s): ; Transfer contents of Array1 to MOVL XAR2,#Array1+(N1)*2 MOVL XAR3,#Array2+(N1)*2 MOV @AR0,#N MOV Loop: NOP MOVL NOP MOVL *,ARP2 ACC,* *,ARP3 *BR0,ACC @AR1,#N1
Array2 in bit reverse order: ; Load XAR2 with end address of Array1 ; Load XAR3 with end address of Array2 ; Load AR0 with size of array, ; N must be a multiple of 2 (2,4,8,16,...) ; Load AR1 with loop count N ; ; ; ; ; ; ; ; ; Set ARP pointer to point to XAR2 Load ACC with location pointed to by XAR2, postdecrement XAR2 Set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postdecrement XAR3 with AR0 reverse borrow subtract Set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1
NOP *,ARP1 XBANZ Loop,*
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AMODE 1
loc16/loc32 Syntax *BR0,ARPn
Description 32bitDataAddr(31:0) = XAR(ARP) XAR(ARP)(15:0) = AR(ARP) rbsub AR0 XAR(ARP)(31:16) = unchanged ARP = n
Note: The lower 16-bits of XAR0 are reverse borrow subtracted (rbsub) from the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Upper 16-bits of the selected register unchanged by the operation.
Example(s): ; Transfer contents of Array1 to MOVL XAR2,#Array1+(N1)*2 MOVL XAR3,#Array2+(N1)*2 MOV @AR0,#N MOV @AR1,#N1 NOP *,ARP2 SETC AMODE .lp_amode Loop: MOVL ACC,*,ARP3
Array2 in bit reverse order: ; Load XAR2 with end address of Array1 ; Load XAR3 with end address of Array2 ; Load AR0 with size of array, ; N must be a multiple of 2 (2,4,8,16,...) ; Load AR1 with loop count N ; Set ARP pointer to point to XAR2 ; Make sure AMODE = 1 ; Tell assembler that AMODE = 1 ; ; ; ; ; ; ; ; ; Load ACC with location pointed to by XAR2, postdecrement XAR2, set ARP pointer to point to XAR3 Store ACC into location pointed to by XAR3, postdecrement XAR3 with AR0 reverse borrow subtract, set ARP pointer to point to XAR1 Loop until AR1 == 0, postdecrement AR1, set ARP pointer to point to XAR2
MOVL
*BR0,ACC,ARP1
XBANZ
Loop,*,ARP2
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Reverse carry addition or reverse carry subtraction is used to implement bit reversed addressing as used in the reordering of data elements in FFT algorithms. Typically, AR0 is initialized with the (FFT size) /2. The value of AR0 is then added or subtracted, with reverse carry addition or subtraction, to generate the bit reversed address: Reverse Carry Addition Example Is Shown Below (FFT size = 16):
XAR(ARP)(15:0) + AR0 XAR(ARP)(15:0) + AR0 XAR(ARP)(15:0) + AR0 XAR(ARP)(15:0) + AR0 XAR(ARP)(15:0) + AR0 XAR(ARP)(15:0) ...... = 0000 0000 0000 0000 = 0000 0000 0000 1000 = 0000 0000 0000 1000 = 0000 0000 0000 1000 = 0000 0000 0000 0100 = 0000 0000 0000 1000 = 0000 0000 0000 1100 = 0000 0000 0000 1000 = 0000 0000 0000 0010 = 0000 0000 0000 1000 = 0000 0000 0000 1010
Reverse Borrow Subtraction Example Is Shown Below (FFT size = 16):

XAR(ARP)(15:0) AR0 XAR(ARP)(15:0) AR0 XAR(ARP)(15:0) AR0 XAR(ARP)(15:0) AR0 XAR(ARP)(15:0) AR0 XAR(ARP)(15:0) ...... = 0000 0000 0000 0000 = 0000 0000 0000 1000 = 0000 0000 0000 1111 = 0000 0000 0000 1000 = 0000 0000 0000 0111 = 0000 0000 0000 1000 = 0000 0000 0000 1011 = 0000 0000 0000 1000 = 0000 0000 0000 0011 = 0000 0000 0000 1000 = 0000 0000 0000 1101
On the C28x, the bit reversed addressing is restricted to block size < 64K. This is OK since most FFT implementations are much less than this.
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5.6.3
Circular Indirect Addressing Modes (XAR6, XAR1)

loc16/loc32 Syntax *AR6%++ Description 32bitDataAddr(31:0) = XAR6 if( XAR6(7:0) == XAR1(7:0) ) { XAR6(7:0) = 0x00 XAR6(15:8) = unchanged } else { if(16-bit data), XAR6(15:0) =+ 1 if(32-bit data), XAR6(15:0) =+ 2 } XAR6(31:16) = unchanged ARP = 6
AMODE 0
As seen in Figure 51, buffer size is determined by the 8 LSBs of AR1 or AR1[7:0]. Specifically, the buffer size is AR1[7:0] +1. When AR1[7:0] is 255, then the buffer size is at its maximum size of 256 words. XAR6 points to the current address in the buffer. The top of the buffer must be at an address where the 8 LSBs are all 0s. If one of the instructions accessing the circular buffer performs a 32-bit operation, make sure XAR6 and AR1 are both even before the buffer is accessed.
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Figure 51. Circular Buffer with AMODE = 0

15 AR1 X X 8 7 0 8 0
Buffer size = 8 + 1 = 9 31 Top of buffer XAR6 X X X X X 8 7 X 0 0 0
Must be zero XAR6[7:0] is incremented until it matches AR1[7:0]
31 Bottom of buffer XAR6 X X X X X
8 7 X 0
0 8
Matches AR1[7:0]
Example(s): ; Calculate MOVW MOVL MOVL MOV SPM ZAPA RPT ||QMACL ADDL MOVL MOVL
FIR filter (X[N] = data array, C[N] = coefficient array): DP,#Xpointer ; Load DP with page address of Xpointer XAR6,@Xpointer ; Load XAR6 with current X pointer XAR7,#C ; Load XAR7 with start address of C array @AR1,#N ; Load AR1 with size of data array N, 4 ; Set product shift mode to >> 4 ; Zero ACC, P, OVC #N1 ; Repeat next instruction N times P,*AR6%++,*XAR7++ ; ACC = ACC + P >> 4, ; P = (*AR6%++ * *XAR7++) >> 32 ACC,P << PM ; Final accumulate @Xpointer,XAR6 ; Store XAR6 into current X pointer @Sum,ACC ; Store result into sum
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AMODE 1
loc16/loc32 Syntax *+XAR6[AR1%++]
Description 32bitDataAddr(31:0) = XAR6 + AR1 if( XAR1(15:0) == XAR1(31:16) ) { XAR1(15:0) = 0x0000 } else { if(16-bit data), XAR1(15:0) =+ 1 if(32-bit data), XAR1(15:0) =+ 2 } XAR1(31:16) = unchanged ARP = 6
Note: With this addressing mode, there is no circular buffer alignment requirements.
As seen in Figure 52, buffer size is determined by the upper 16 bits of XAR1 or XAR1[31:16]. Specifically, the size is XAR1[31:16] + 1. XAR6 points to the top of the buffer. The current address in the buffer is pointed to by XAR6 with an offset of XAR1[15:0]. If the instructions that access the circular buffer perform 32-bit operations, make sure XAR6 and XAR1[31:16] are even.
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Figure 52. Circular Buffer with AMODE = 1

31 XAR1 0 0 0 16 15 9 0 0 0 0 0
Buffer size = 9 + 1 = 10 31 XAR6
Buffer index
0 003F8010
Top of buffer
XAR6 + XAR1[15:0] = 3F8010h 0x0000
XAR1[15:0] increments until it matches XAR1[31:16]
Bottom of buffer
XAR6 + XAR1[15:0] = 3F8010h + 0009h Matches XAR1[31:16]
Example(s): ; Calculate MOVW MOVL MOV MOV MOVL MOVL SPM ZAPA RPT ||QMACL ADDL MOV MOVL
FIR filter (X[N] = data array, C[N] = coefficientv array): DP,#Xindex ; Load DP with page address of Xindex XAR6,#X ; Load XAR6 with start address of X array @AH,#N ; Load AH with size of array X (N) AL,@Xindex ; Load AL with current circular index XAR1,@ACC ; Load parameters into XAR1 XAR7,#C ; Load XAR7 with start address of C array 4 ; Set product shift mode to >> 4 ; Zero ACC, P, OVC #N1 ; Repeat next instruction N times P,*+XAR6[AR1%++],*XAR7++ ; ACC = ACC + P >> 4, ; P = (*AR6%++ * *XAR7++) >> 32 ACC,P << PM ; Final accumulate @Xindex,AR1 ; Store AR1 into current X index @Sum,ACC ; Store result into sum
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Register Addressing Modes
5.7 Register Addressing Modes

This section includes register addressing modes for 32-bit and 16-bit registers.
5.7.1
32-Bit Register Addressing Modes

loc32 Syntax @ACC Description Access contents of 32-bit ACC register. When the @ACC register is the destination operand, this may affect the Z,N,V,C,OVC flags.
AMODE X
Example(s):
MOVL MOVL ADDL XAR6,@ACC @ACC,XT ACC,@ACC ; Load XAR6 with contents of ACC ; Load ACC with contents of XT register ; ACC = ACC + ACC
AMODE X
loc32 Syntax @P
Description Access contents of 32-bit P register. ; Load XAR6 with contents of P ; Load P with contents of XT register ; ACC = ACC + P
Example(s): MOVL XAR6,@P MOVL @P,XT ADDL ACC,@P
AMODE X
loc32 Syntax @XT
Description Access contents of 32-bit XT register. ; Load XAR6 with contents of XT ; Load P with contents of XT register ; ACC = ACC + XT
Example(s): MOVL XAR6,@XT MOVL P,@XT ADDL ACC,@XT
AMODE X
loc32 Syntax @XARn
Description Access contents of 32-bit XARn registers. ; Load XAR6 with contents of XAR2 ; Load P with contents of XAR2 register ; ACC = ACC + XAR2
Example(s): MOVL XAR6,@XAR2 MOVL P,@XAR2 ADDL ACC,@XAR2
Note: When writing assembly code, the @ symbol in front of the register is optional. For example: MOVL ACC,@P or MOVL ACC,P. The disassembler will use the @ to indicate operands that are loc16 or loc32. For example, MOVL ACC, @P is the MOVL ACC, loc32 instruction and MOVL @ACC, P is the MOVL loc32, P instruction.
5-25
5.7.2
16-Bit Register Addressing Modes

loc16 Syntax @AL Description Access contents of 16-bit AL register. AH register contents are un-affected. When the @AL register is the destination operand, this may affect the Z,N,V,C,OVC flags.
AMODE X
Example(s): MOV PH,@AL ADD AH,@AL MOV T,@AL
; Load PH with contents of AL ; AH = AH + AL ; Load T with contents of AL
AMODE X
loc16 Syntax
Description Access contents of 16-bit AH register. AL register contents are un-affected. When the @AH register is the destination operand, this may affect the Z,N,V,C,OVC flags.
@AH
Example(s): MOV PH,@AH ADD AL,@AH MOV T,@AH
; Load PH with contents of AH ; AL = AL + AH ; Load T with contents of AH
AMODE X
loc16 Syntax
Description Access contents of 16-bit PL register. PH register contents are un-affected.
@PL
Example(s): MOV PH,@PL ADD AL,@PL MOV T,@PL
; Load PH with contents of PL ; AL = AL + PL ; Load T with contents of PL
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AMODE X
loc16 Syntax
Description Access contents of 16-bit PH register. PL register contents are un-affected.
@PH
Example(s): MOV PL,@PH ADD AL,@PH MOV T,@PH
; Load PL with contents of PH ; AL = AL + PH ; Load T with contents of PH
AMODE X
loc16 Syntax
Description Access contents of 16-bit TH register. TL register contents are unaffected.
@TH
Example(s): MOV PL,@T ADD AL,@T MOVZ AR4,@T
; Load PL with contents of T ; AL = AL + T ; Load AR4 with contents of T, AR4H = 0
AMODE X
loc16 Syntax
Description Access contents of 16-bit SP register.
@SP
Example(s): MOVZ AR4,@SP MOV AL,@SP MOV @SP,AH
; Load AR4 with contents of SP, AR4H = 0 ; Load AL with contents of SP ; Load SP with contents of AH
AMODE X
loc16 Syntax
Description Access contents of 16-bit AR0 to AR7 registers. AR0H to AR7H register contents are unaffected.
@ARn
Example(s): MOVZ AR4,@AR2 MOV AL,@AR3 MOV @AR5,AH
; Load AR4 with contents of AR2, AR4H = 0 ; Load AL with contents of AR3 ; Load AR5 with contents of AH, AR5H = unchanged
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Data/Program/IO Space Immediate Addressing Modes
5.8 Data/Program/IO Space Immediate Addressing Modes

Syntax *(0:16bit) Description 32BitDataAddr(31:16) = 0 32BitDataAddr(15:0) = 16bit immediate value
Note: If instruction is repeated, the address is postincremented on each iteration. This addressing mode can only access the low 64K of data space.
Instructions that use this addressing mode:
MOV MOV
loc16,*(0:16bit) *(0:16bit),loc16
Syntax *(PA)
; [loc16] = [0:16bit] ; [loc16] = [0:16bit]
Description 32BitDataAddr(31:16) = 0 32BitDataAddr(15:0) = PA 16bit immediate value

Note: If instruction is repeated, the address is postincremented on each iteration. The I/O strobe signal is toggled when accessing I/O space with this addressing mode. The data space address lines are used for accessing I/O space.
Instructions that use this addressing mode: OUT *(PA),loc16 ; IOspace[0:PA] = [loc16] UOUT *(PA),loc16 ; IOspace[0:PA] = [loc16] IN loc16,*(PA) ; [loc16] = IOspace[0:PA] Syntax 0:pma Description
(unprotected)
22BitProgAddr(21:16) = 0 22BitProgAddr(15:0) = pma 16bit immediate value

Note: If instruction is repeated, the address is postincremented on each iteration. This addressing mode can only access the low 64K of program space.
Instructions that use this addressing mode: MAC P,loc16,0:pma ; ACC = ACC + P << PM, ; P = [loc16] * ProgSpace[0:pma]
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Data/Program/IO Space Immediate Addressing Modes
Syntax
Description 22BitProgAddr(21:16) = 0x3F 22BitProgAddr(15:0) = pma 16bit immediate value

Note: If instruction is repeated, the address is postincremented on each iteration. This addressing mode can only access the upper 64K of program space.
*(pma)
Instructions that use this addressing mode: XPREAD loc16,*(pma) ; [loc16] = ProgSpace[0x3F:pma] XMAC P,loc16,*(pma) ; ACC = ACC + P << PM, ; P = [loc16] * ProgSpace[0x3F:pma] XMACD P,loc16,*(pma) ; ACC = ACC + P << PM, ; P = [loc16] * ProgSpace[0x3F:pma], ; [loc16+1] = [loc16]
5-29
Program Space Indirect Addressing Modes
5.9 Program Space Indirect Addressing Modes

Syntax *AL Description 22BitProgAddr(21:16) = 0x3F 22BitProgAddr(15:0) = AL
Note: If instruction is repeated, the address in AL is copied to a shadow register and the value postincremented on each iteration. The AL register is not modified. This addressing mode can only access the upper 64K of program space.
Instructions that use this addressing mode: XPREAD loc16,*AL ; [loc16] = ProgSpace[0x3F:AL] XPWRITE *AL,loc16 ; ProgSpace[0x3F:AL] = [loc16] Syntax *XAR7 Description 22BitProgAddr(21:0) = XAR7
Note: If instruction is repeated, only in the XPREAD and XPWRITE instructions, is the address contained in XAR7 copied to a shadow register and the value postincremented on each iteration. The XAR7 register is not modified. For all other instructions, the address is not incremented even when repeated.
Instructions that use this addressing mode: MAC P,loc16,*XAR7 ; ACC = ACC + P << PM, ; P = [loc16] * ProgSpace[*XAR7] DMAC ACC:P,loc32,*XAR7 ; ACC = ([loc32].MSW * ProgSpace[*XAR7].MSW) >> PM, ; P = ([loc32].LSW * ProgSpace[*XAR7].MSW) >> PM QMACL P,loc32,*XAR7 ; ACC = ACC + P >> PM, ; P = ([loc32] * ProgSpace[*XAR7]) >> 32 IMACL P,loc32,*XAR7 ; ACC = ACC + P, ; P = ([loc32] * ProgSpace[*XAR7]) << PM PREAD loc16,*XAR7 ; [loc16] = ProgSpace[*XAR7] PWRITE *XAR7,loc16 ; ProgSpace[*XAR7] = [loc16] Syntax *XAR7++ Description 22BitProgAddr(21:0) = XAR7, if(16bit operation) XAR7 = XAR7 + 1, if(32bit operation) XAR7 = XAR7 + 2
Note: If instruction is repeated, the address is postincremented as normal.
Instructions that use this addressing mode: MAC P,loc16,*XAR7++ ; ACC = ACC + P << PM, ; P = [loc16] * ProgSpace[*XAR7++] DMAC ACC:P,loc32,*XAR7++ ; ACC=([loc32].MSW * ProgSpace[*XAR7++].MSW)>>PM, ; P=([loc32].LSW * ProgSpace[*XAR7++].MSW)>>PM QMACL P,loc32,*XAR7++ ; ACC = ACC + P >> PM, ; P = ([loc32] * ProgSpace[*XAR7++]) >> 32 IMACL P,loc32,*XAR7++ ; ACC = ACC + P, ; P = ([loc32] * ProgSpace[*XAR7++]) << PM 5-30
Byte Addressing Modes
5.10 Byte Addressing Modes

Syntax *+XARn[AR0] *+XARn[AR1] *+XARn[3bit] Description 32BitDataAddr(31:0) = XARn + Offset (Offset = AR0/AR1/3bit) if( Offset == Even Value ) Access LSByte Of 16bit Memory Location; Leave MSByte untouched; if( Offset == Odd Value ) Access MSByte Of 16bit Memory Location; Leave LSByte untouched;
Note: For all other addressing modes, only the LSByte of the addressed location is accessed, the MSByte is left untouched.
5-31
Byte Addressing Modes
Instructions that use this addressing mode: MOVB AX.LSB,loc16 ; if( address mode == *+XARn[AR0/AR1/3bit] ; if( offset == even ) ; AX.LSB = [loc16].LSB; ; AX.MSB = 0x00; ; if( offset == odd ) ; AX.LSB = [loc16].MSB; ; AX.MSB = 0x00; ; else ; AX.LSB = [loc16].LSB; ; AX.MSB = 0x00; MOVB AX.MSB,loc16 ; if( address mode == *+XARn[AR0/AR1/3bit] ; if( offset == even ) ; AX.LSB = untouched; ; AX.MSB = [loc16].LSB; ; if( offset == odd ) ; AX.LSB = untouched; ; AX.MSB = [loc16].MSB; ; else ; AX.LSB = untouched; ; AX.MSB = [loc16].LSB; MOVB loc16,AX.LSB ; if( address mode == *+XARn[AR0/AR1/3bit] ; if( offset == even ) ; [loc16].LSB = AX.LSB ; [loc16].MSB = untouched; ; if( offset == odd ) ; [loc16].LSB = untouched; ; [loc16].MSB = AX.LSB; ; else ; [loc16].LSB = AX.LSB; ; [loc16].MSB = untouched; MOVB loc16,AX.MSB ; if( address mode == *+XARn[AR0/AR1/3bit] ; if( offset == even ) ; [loc16].LSB = AX.MSB ; [loc16].MSB = untouched; ; if( offset == odd ) ; [loc16].LSB = untouched; ; [loc16].MSB = AX.MSB; ; else ; [loc16].LSB = AX.MSB; ; [loc16].MSB = untouched;
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Alignment of 32-Bit Operations
5.11 Alignment of 32-Bit Operations

All 32-bit reads and writes to memory are aligned at the memory interface to an even address boundary with the least significant word of the 32-bit data aligned to the even address. The output of the address generation unit does not force alignment, hence pointer values retain their values. For example:
MOVB MOVL AR0,#5 ; AR0 = 5 *AR0,ACC ; AL > address 0x000004 ; AH > address 0x000005 ; AR0 = 5
The programmer must take the above into account when generating addresses that are not aligned to an even boundary. 32-bit operands are stored in the following order; low order bits, 0 to 15, followed by the high order bits, 16 to 31, on the next highest 16-bit address increment (little-endian format).
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5-34
Chapter 6
C28x Assembly Language Instructions

This chapter presents summaries of the instruction set, defines special symbols and notations used, and describes each instruction in detail in alphabetical order.
Topic
6.1 6.2
Page
Instruction Set Summary (Organized by Function) . . . . . . . . . . . . . . . 6-2 Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6-1
Instruction Set Summary (Organized by Function)
6.1 Instruction Set Summary (Organized by Function)

Note: The examples in this chapter assume that the device is already operating in C28x Mode (OBJMODE = = 1, AMODE = = 0). To put the device into C28x mode following a reset, you must first set the OBJMODE bit in ST1 by executing the C28OBJ (or SETC OBJMODE) instruction. Cycle Counts assume the instruction is executed from zero-wait (single-cycle) memory and there are no pipeline stalls.
Note:
Table 61. Instruction Set Summary (Organized by Function)

Symbol XARn ARn, ARm ARnH ARPn Description XAR0 to XAR7 registers Lower 16-bits of XAR0 to XAR7 registers Upper 16-bits of XAR0 to XAR7 registers 3-bit auxiliary register pointer, ARP0 to ARP7 ARP0 points to XAR0 and ARP7 points to XAR7 AR(ARP) XAR(ARP) AX # PM PC ~ [loc16] 0:[loc16] S:[loc16] [loc32] 0:[loc32] S:[loc32] 7bit 0:7bit S:7bit Lower 16-bits of auxiliary register pointed to by ARP Auxiliary registers pointed to by ARP Accumulator high (AH) and low (AL) registers Immediate operand Product shift mode (+4,1,0,1,2,3,4,5,6) Program counter Bitwise compliment Contents of 16-bit location Contents of 16-bit location, zero extended Contents of 16-bit location, sign extended Contents of 32-bit location Contents of 32-bit location, zero extended Contents of 32-bit location, sign extended 7-bit immediate value 7-bit immediate value, zero extended 7-bit immediate value, sign extended
6-2
Instruction Set Summary (Organized by Function)
Table 61. Instruction Set Summary (Organized by Function) (Continued)

Symbol 8bit 0:8bit S:8bit 10bit 0:10bit 16bit 0:16bit S:16bit 22bit 0:22bit LSb LSB LSW MSb MSB MSW OBJ N {} = == Description 8-bit immediate value 8-bit immediate value, zero extended 8-bit immediate value, sign extended 10-bit immediate value 10-bit immediate value, zero extended 16-bit immediate value 16-bit immediate value, zero extended 16-bit immediate value, sign extended 22-bit immediate value 22-bit immediate value, zero extended Least Significant bit Least Significant Byte Least Significant Word Most Significant bit Most Significant Byte Most Significant Word OBJMODE bit state for which instruction is valid Repeat count (N = 0,1,2,3,4,5,6,7,....) Optional field Assignment Equivalent to
6-3
Register Operations
6.2 Register Operations

Note: The examples in this chapter assume that the device is already operating in C28x Mode (OBJMODE == 1, AMODE == 0). To put the device into C28x mode following a reset, you must first set the OBJMODE bit in ST1 by executing the C28OBJ (or SETC OBJMODE) instruction. Cycle Counts assume the instruction is executed from zero-wait (single-cycle) memory and there are no pipeline stalls.
Note:
Table 62. Register Operations

Mnemonic XARn Register Operations (XAR0XAR7) ADDB ADRK CMPR MOV MOV MOV MOVB MOVB MOVL MOVL MOVL MOVZ SBRK SUBB XARn,#7bit #8bit 0/1/2/3 AR6/7,loc16 loc16,ARn XARn,PC AR6/7,#8bit XARn,#8bit loc32,XARn XARn,loc32 XARn,#22bit ARn,loc16 #8bit XARn,#7bit Add 7-bit constant to auxiliary register Add 8-bit constant to current auxiliary register Compare auxiliary registers Load auxiliary register Store 16-bit auxiliary register Save the current program counter Load auxiliary register with an 8-bit constant Load auxiliary register with 8-bit value Store 32-bit auxiliary register Load 32-bit auxiliary register Load 32-bit auxiliary register with constant value Load lower half of XARn and clear upper half Subtract 8-bit constant from current auxiliary register Subtract 7-bit constant from auxiliary register 6-33 6-42 6-82 6-160 6-168 6-182 6-188 6-200 6-210 6-214 6-215 6-225 6-319 6-342 Description Page
DP Register Operations MOV MOVW MOVZ DP,#10bit DP,#16bit DP,#10bit Load data-page pointer Load the entire data page Load data page and clear high bits 6-162 6-223 6-226
SP Register Operations ADDB POP SP,#7bit ACC Add 7-bit constant to stack pointer Pop ACC register from stack 6-32 6-267
6-4
Register Operations
Table 62. Register Operations (Continued)

Mnemonic POP POP AR1:AR0 AR1H:AR0H Description Pop AR1 & AR0 registers from stack Pop AR1H & AR0H registers from stack Page 6-268 6-269
SP Register Operations (Continued) POP POP POP POP POP POP POP POP POP POP POP POP POP POP PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH AR3:AR2 AR5:AR4 DBGIER DP:ST1 DP IFR loc16 P RPC ST0 ST1 T:ST0 XT XARn ACC ARn:ARn AR1H:AR0H DBGIER DP:ST1 DP IFR loc16 P RPC Pop AR3 & AR2 registers from stack Pop AR5 & AR4 registers from stack Pop DBGIER register from stack Pop DP & ST1 registers on stack Pop DP register from stack Pop IFR register from stack Pop loc16 data from stack Pop P register from stack Pop RPC register from stack Pop ST0 register from stack Pop ST1 register from stack Pop T & ST0 registers from stack Pop XT register from stack Pop auxiliary register from stack Push ACC register on stack Push ARn & ARn registers on stack Push AR1H & AR0H registers on stack Push DBGIER register on stack Push DP & ST1 registers on stack Push DP register on stack Push IFR register on stack Push loc16 data on stack Push P register on stack Push RPC register on stack 6-268 6-268 6-270 6-272 6-271 6-273 6-274 6-275 6-276 6-277 6-278 6-279 6-281 6-280 6-284 6-285 6-286 6-287 6-289 6-288 6-290 6-291 6-292 6-293
6-5
Register Operations

Mnemonic PUSH PUSH ST0 ST1 Description Push ST0 register on stack Push ST1 register on stack Page 6-294 6-295
SP Register Operations (Continued) PUSH PUSH PUSH SUBB T:ST0 XT XARn SP,#7bit Push T & ST0 registers on stack Push XT register on stack Push auxiliary register on stack Subtract 7-bit constant from the stack pointer 6-296 6-298 6-297 6-341
AX Register Operations (AH, AL) ADD ADD ADDB AND AND AND ANDB ASR ASR CMP CMPB FLIP LSL LSL LSR LSR MAX MIN MOV AX,loc16 loc16,AX AX,#8bit AX,loc16,#16bit AX,loc16 loc16,AX AX,#8bit AX,1..16 AX,T AX,loc16 AX,#8bit AX AX,1..16 AX,T AX,1..16 AX,T AX,loc16 AX,loc16 AX,loc16 Add value to AX Add AX to specified location Add 8-bit constant to AX Bitwise AND Bitwise AND Bitwise AND Bitwise AND 8-bit value Arithmetic shift right Arithmetic shift right by T(3:0) = 0...15 Compare Compare 8-bit value Flip order of bits in AX register Logical shift left Logical shift left by T(3:0) = 0...15 Logical shift right Logical shift right by T(3:0) = 0..15 Find the maximum Find the minimum Load AX 6-27 6-28 6-31 6-45 6-49 6-48 6-51 6-53 6-54 6-74 6-79 6-96 6-135 6-136 6-140 6-136 6-149 6-153 6-161
6-6
Register Operations

Mnemonic MOV MOV loc16,AX loc16,AX,COND Description Store AX Store AX register conditionally Page 6-169 6-170
AX Register Operations (AH, AL) (Continued) MOVB MOVB MOVB MOVB MOVB NEG NOT OR OR ORB SUB SUB SUBR SXTB XOR XORB XOR AX,#8bit AX.LSB,loc16 AX.MSB,loc16 loc16,AX.LSB loc16,AX.MSB AX AX AX,loc16 loc16,AX AX,#8bit AX,loc16 loc16,AX loc16,AX AX AX,loc16 AX,#8bit loc16,AX Load AX with 8-bit constant Load LSB of AX reg, MSB = 0x00 Load MSB of AX reg, LSB = unchanged Store LSB of AX reg Store MSB of AX reg Negate AX register Complement AX register Bitwise OR Bitwise OR Bitwise OR 8-bit value Subtract specified location from AX Subtract AX from specified location Reverse-subtract specified location from AX Sign extend LSB of AX reg into MSB Bitwise exclusive OR Bitwise exclusive OR 8-bit value Bitwise exclusive OR 6-384 6-387 6-385 6-189 6-190 6-192 6-196 6-198 6-245 6-256 6-259 6-263 6-264 6-338 6-339 6-354
16-Bit ACC Register Operations ADD ADD ADD ADDB ADDCU ADDU ACC,loc16 {<< 0..16} ACC,#16bit {<< 0..15} ACC,loc16 << T ACC,#8bit ACC,loc16 ACC,loc16 Add value to accumulator Add value to accumulator Add shifted value to accumulator Add 8-bit constant to accumulator Add unsigned value plus carry to accumulator Add unsigned value to accumulator 6-25 6-22 6-24 6-30 6-35 6-39
6-7
Register Operations

Mnemonic AND AND ACC,loc16 ACC,#16bit {<< 0..16} Description Bitwise AND Bitwise AND Page 6-44 6-43
16-Bit ACC Register Operations (Continued) MOV MOV MOV MOV MOVB MOVH MOVU SUB SUB SUB SUBB SBBU SUBU OR OR XOR XOR ZALR ACC,loc16 {<< 0..16} ACC,#16bit {<< 0..15} loc16,ACC << 1..8 ACC,loc16 << T ACC,#8bit loc16,ACC << 1..8 ACC,loc16 ACC,loc16 << T ACC,loc16 {<< 0..16} ACC,#16bit {<< 0..15} ACC,#8bit ACC,loc16 ACC,loc16 ACC,loc16 ACC,#16bit {<< 0..16} ACC,loc16 ACC,#16bit {<< 0..16} ACC,loc16 Load accumulator with shift Load accumulator with shift Save low word of shifted accumulator Load accumulator with shift Load accumulator with 8-bit value Save high word of shifted accumulator Load accumulator with unsigned word Subtract shifted value from accumulator Subtract shifted value from accumulator Subtract shifted value from accumulator Subtract 8-bit value Subtract unsigned value plus inverse borrow Subtract unsigned 16-bit value Bitwise OR Bitwise OR Bitwise exclusive OR Bitwise exclusive OR Zero AL and load AH with rounding 6-159 6-159 6-167 6-158 6-187 6-202 6-220 6-335 6-333 6-337 6-340 6-317 6-356 6-257 6-258 6-382 6-383 6-394
32-Bit ACC Register Operations ABS ABSTC ADDL ADDL ADDCL ACC ACC ACC,loc32 loc32,ACC ACC,loc32 Absolute value of accumulator Absolute value of accumulator and load TC Add 32-bit value to accumulator Add accumulator to specified location Add 32-bit value plus carry to accumulator 6-19 6-20 6-36 6-38 6-34
6-8
Register Operations

Mnemonic ADDUL ADDL ACC,loc32 ACC,P << PM Description Add 32-bit unsigned value to accumulator Add shifted P to accumulator Page 6-41 6-37
32-Bit ACC Register Operations (Continued) ASRL CMPL CMPL CSB LSL LSL LSRL LSLL MAXL MINL MOVL MOVL MOVL MOVL MOVL NORM NORM NEG NEGTC NOT ROL ROR SAT SFR ACC,T ACC,loc32 ACC,P << PM ACC ACC,1..16 ACC,T ACC,T ACC,T ACC,loc32 ACC,loc32 ACC,loc32 loc32,ACC P,ACC ACC,P << PM loc32,ACC,COND ACC,XARn++/ ACC,*ind ACC ACC ACC ACC ACC ACC ACC,1..16 Arithmetic shift right of accumulator by T(4:0) Compare 32-bit value Compare 32-bit value Count sign bits Logical shift left 1 to 16 places Logical shift left by T(3:0) = 0...15 Logical shift right by T(4:0) Logical shift left by T(4:0) Find the 32-bit maximum Find the 32-bit minimum Load accumulator with 32 bits Store 32-bit accumulator Load P from the accumulator Load the accumulator with shifted P Store ACC conditionally Normalize ACC and modify selected auxiliary register. C2XLP compatible Normalize ACC operation Negate ACC If TC is equivalent to 1, negate ACC Complement ACC Rotate ACC left Rotate ACC right Saturate ACC based on OVC value Shift accumulator right by 1 to 16 places 6-57 6-80 6-81 6-83 6-133 6-134 6-144 6-139 6-152 6-155 6-204 6-206 6-212 6-205 6-207 6-253 6-251 6-244 6-248 6-255 6-310 6-311 6-313 6-325
6-9
Register Operations

Mnemonic SFR SUBBL ACC,T ACC,loc32 Description Shift accumulator right by T(3:0) = 0...15 Subtract 32-bit value plus inverse borrow Page 6-326 6-343
32-Bit ACC Register Operations (Continued) SUBCU SUBCUL SUBL SUBL SUBL SUBRL SUBUL TEST ACC,loc16 ACC,loc32 ACC,loc32 loc32,ACC ACC,P << PM loc32,ACC ACC,loc32 ACC Subtract conditional 16-bit value Subtract conditional 32-bit value Subtract 32-bit value Subtract 32-bit value Subtract 32-bit value Reverse-subtract specified location from ACC Subtract unsigned 32-bit value Test for accumulator equal to zero 6-345 6-347 6-350 6-353 6-351 6-355 6-357 6-362
64-Bit ACC:P Register Operations ASR64 ASR64 CMP64 LSL64 LSL64 LSR64 LSR64 NEG64 SAT64 ACC:P,#1..16 ACC:P,T ACC:P ACC:P,1..16 ACC:P,T ACC:P,#1..16 ACC:P,T ACC:P ACC:P Arithmetic shift right of 64-bit value Arithmetic shift right of 64-bit value by T(5:0) Compare 64-bit value Logical shift left 1 to 16 places 64-bit logical shift left by T(5:0) 64-bit logical shift right by 1 to 16 places 64-bit logical shift right by T(5:0) Negate ACC:P Saturate ACC:P based on OVC value 6-55 6-56 6-77 6-137 6-138 6-142 6-143 6-246 6-314
P or XT Register Operations (P, PH, PL, XT, T, TL) ADDUL MAXCUL MINCUL MOV MOV P,loc32 P,loc32 P,loc32 PH,loc16 PL,loc16 Add 32-bit unsigned value to P Conditionally find the unsigned maximum Conditionally find the unsigned minimum Load the high half of the P register Load the low half of the P register 6-40 6-150 6-154 6-177 6-178
6-10
Register Operations

Mnemonic MOV MOV loc16,P T,loc16 Description Store lower half of shifted P register Load the upper half of the XT register Page 6-174 6-180
P or XT Register Operations (P, PH, PL, XT, T, TL) (Continued) MOV MOV MOVA MOVAD MOVDL MOVH MOVL MOVL MOVL MOVL MOVP MOVS MOVX SUBUL loc16,T TL,#0 T,loc16 T,loc16 XT,loc32 loc16,P P,loc32 loc32,P XT,loc32 loc32,XT T,loc16 T,loc16 TL,loc16 P,loc32 Store the T register Clear the lower half of the XT register Load the T register and add the previous product Load T register Store XT and load new XT Save the high word of the P register Load the P register Store the P register Load the XT register Store the XT register Load the T register and store P in the accumulator Load T and subtract P from the accumulator Load lower half of XT with sign extension Subtract unsigned 32-bit value 6-175 6-181 6-183 6-185 6-201 6-203 6-213 6-209 6-216 6-211 6-217 6-218 6-224 6-358
16x16 Multiply Operations DMAC MAC MAC MPY MPY MPY MPY MPYA MPYA ACC:P,loc32,*XAR7/++ P,loc16,0:pma P,loc16,*XAR7/++ P,T,loc16 P,loc16,#16bit ACC,T,loc16 ACC,loc16,#16bit P,loc16,#16bit P,T,loc16 16-bit dual multiply and accumulate Multiply and accumulate Multiply and Accumulate 16 X 16 multiply 16 X 16-bit multiply 16 X 16-bit multiply 16 X 16-bit multiply 16 X 16-bit multiply and add previous product 16 X 16-bit multiply and add previous product 6-86 6-145 6-147 6-230 6-229 6-228 6-227 6-231 6-233
6-11
Register Operations

Mnemonic MPYB MPYS P,T,#8bit P,T,loc16 Description Multiply signed value by unsigned 8-bit constant 16 X 16-bit multiply and subtract Page 6-236 6-237
16x16 Multiply Operations (Continued) MPYB MPYU MPYU MPYXU MPYXU SQRA SQRS XMAC XMACD ACC,T,#8bit ACC,T,loc16 P,T,loc16 P,T,loc16 ACC,T,loc16 loc16 loc16 P,loc16,*(pma) P,loc16,*(pma) Multiply by 8-bit constant 16 X 16-bit unsigned multiply Unsigned 16 X 16 multiply Multiply signed value by unsigned value Multiply signed value by unsigned value Square value and add P to accumulator Square value and subtract from accumulator C2xLP source-compatible multiply and accumulate C2xLP source-compatible multiply and accumulate with data move 6-235 6-240 6-239 6-242 6-241 6-329 6-331 6-378 6-380
32x32 Multiply Operations IMACL IMPYAL IMPYL IMPYL IMPYSL IMPYXUL QMACL QMPYAL QMPYL QMPYL QMPYSL QMPYUL QMPYXUL P,loc32,*XAR7/++ P,XT,loc32 P,XT,loc32 ACC,XT,loc32 P,XT,loc32 P,XT,loc32 P,loc32,*XAR7/++ P,XT,loc32 ACC,XT,loc32 P,XT,loc32 P,XT,loc32 P,XT,loc32 P,XT,loc32 Signed 32 X 32-bit multiply and accumulate (lower half) Signed 32-bit multiply (lower half) and add previous P Signed 32 X 32-bit multiply (lower half) Signed 32 X 32-bit multiply (lower half) Signed 32-bit multiply (lower half) and subtract P Signed 32 X unsigned 32-bit multiply (lower half) Signed 32 X 32-bit multiply and accumulate (upper half) Signed 32-bit multiply (upper half) and add previous P Signed 32 X 32-bit multiply (upper half) Signed 32 X 32-bit multiply (upper half) Signed 32-bit multiply (upper half) and subtract previous P Unsigned 32 X 32-bit multiply (upper half) Signed 32 X unsigned 32-bit multiply (upper half) 6-100 6-103 6-106 6-105 6-107 6-109 6-300 6-302 6-305 6-304 6-306 6-308 6-309
6-12
Register Operations

Mnemonic Direct Memory Operations ADD loc16,#16bitSigned Add constant to specified location 6-29 Description Page
Direct Memory Operations (Continued) AND CMP DEC DMOV INC MOV MOV MOV MOV MOVB OR TBIT TBIT TCLR TSET XOR loc16,#16bitSigned loc16,#16bitSigned loc16 loc16 loc16 *(0:16bit),loc16 loc16,*(0:16bit) loc16,#16bit loc16,#0 loc16,#8bit,COND loc16,#16bit loc16,#bit loc16,T loc16,#bit loc16,#bit loc16,#16bit Bitwise AND Compare Decrement by 1 Data move contents of 16-bit location Increment by 1 Move value Move value Save 16-bit constant Clear 16-bit location Store byte conditionally Bitwise OR Test bit Test bit specified by T register Test and clear specified bit Test and set specified bit Bitwise exclusive OR 6-50 6-75 6-84 6-89 6-113 6-156 6-165 6-164 6-166 6-194 6-262 6-359 6-360 6-361 6-365 6-386
IO Space Operations IN OUT UOUT loc16,*(PA) *(PA),loc16 *(PA),loc16 Input data from port Output data to port Unprotected output data to I/O port 6-111 6-265 6-366
Program Space Operations PREAD PWRITE XPREAD loc16,*XAR7 *XAR7,loc16 loc16,*AL Read from program memory Write to program memory C2xLP source-compatible program read 6-282 6-299 6-389
6-13
Register Operations

Mnemonic XPREAD XPWRITE loc16,*(pma) *AL,loc16 Description C2xLP source-compatible program read C2xLP source-compatible program write Page 6-388 6-390
Branch/Call/Return Operations B BANZ BAR BF FFC IRET LB LB LC LC LCR LCR LOOPZ LOOPNZ LRET LRETE LRETR RPT SB SBF XB XB XB XB #8bit/loc16 8bitOff,COND 8bitOff,EQ/NEQ/TC/NTC pma pma,COND pma,*,ARPn *AL 22bitAddr *XAR7 22bitAddr *XAR7 22bitAddr *XARn loc16,#16bit loc16,#16bit 16bitOff,COND 16bitOff,ARn 16bOf,ARn,ARn,EQ/NEQ 16bitOff,COND XAR7,22bitAddr Conditional branch Branch if auxiliary register not equal to zero Branch on auxiliary register comparison Branch fast Fast function call Interrupt return Long branch Long indirect branch Long call immediate Long indirect call Long call using RPC Long indirect call using RPC Loop while zero Loop while not zero Long return Long return and enable interrupts Long return using RPC Repeat next instruction Short conditional branch Short fast conditional branch C2XLP source-compatible branch C2XLP source-compatible conditional branch C2XLP source-compatible branch function call C2XLP source-compatible function call 6-58 6-59 6-60 6-61 6-95 6-116 6-120 6-119 6-122 6-121 6-123 6-124 6-127 6-125 6-130 6-131 6-132 6-312 6-316 6-318 6-369 6-370 6-369 6-368
6-14
Register Operations

Mnemonic XBANZ XCALL pma,*ind{,ARPn} pma Description C2XLP source-compatible branch if ARn is not zero C2XLP source-compatible call Page 6-372 6-375
Branch/Call/Return Operations (Continued) XCALL XCALL XCALL XRET XRETC COND pma,COND pma,*,ARPn *AL C2XLP source-compatible conditional call C2XLP source-compatible call with ARP modification C2XLP source-compatible indirect call Alias for XRETC UNC C2XLP source-compatible conditional return 6-376 6-375 6-374 6-391 6-392
Interrupt Register Operations AND AND IACK INTR IER,#16bit IFR,#16bit #16bit INT1/../INT14 NMI EMUINT DLOGINT RTOSINT IER,loc16 loc16,IER IER,#16bit IFR,#16bit #0..31 Bitwise AND to disable specified CPU interrupts Bitwise AND to clear pending CPU interrupts Interrupt acknowledge Emulate hardware interrupts 6-46 6-47 6-97 6-114
MOV MOV OR OR TRAP
Load the interrupt-enable register Store interrupt enable register Bitwise OR Bitwise OR Software trap
6-163 6-172 6-260 6-261 6-363
Status Register Operations (ST0, ST1) CLRC CLRC CLRC C28ADDR CLRC C27OBJ OBJMODE Mode XF AMODE Clear status bits Clear the XF status bit and output signal Clear the AMODE bit Clear the AMODE status bit Clear the OBJMODE bit Clear the OBJMODE bit 6-72 6-71 6-67 6-64 6-69 6-63
6-15
Register Operations

Mnemonic CLRC C27MAP M0M1MAP Description Clear the M0M1MAP bit Set the M0M1MAP bit Page 6-68 6-62
Status Register Operations (ST0, ST1) (Continued) CLRC ZAP DINT EINT MOV MOV MOVU MOV MOVU SETC SETC SETC C28MAP SETC C28OBJ SETC LPADDR SPM PM AMODE OBJMODE PM,AX OVC,loc16 OVC,loc16 loc16,OVC loc16,OVC Mode XF M0M1MAP OVC OVC Clear OVC bits Clear overflow counter Disable maskable interrupts (set INTM bit) Enable maskable interrupt (clear INTM bit) Load product shift mode bits PM = AX(2:0) Load the overflow counter Load overflow counter with unsigned value Store the overflow counter Store the unsigned overflow counter Set multiple status bits Set XF bit and output signal Set M0M1MAP bit Set the M0M1MAP bit Set OBJMODE bit Set the OBJMODE bit Set AMODE bit Alias for SETC AMODE Set product shift mode bits 6-129 6-327 6-70 6-395 6-85 6-92 6-179 6-176 6-222 6-173 6-221 6-320 6-324 6-65 6-322 6-66 6-323
Miscellaneous Operations ABORTI ASP EALLOW IDLE NASP NOP {*ind} Abort interrupt Align stack pointer Enable access to protected space Put processor in IDLE mode Un-align stack pointer No operation with optional indirect address modification 6-18 6-52 6-90 6-98 6-243 6-250
6-16
Register Operations

Mnemonic ZAPA EDIS Miscellaneous Operations (Continued) ESTOP0 ESTOP1 Emulation Stop 0 Emulation Stop 1 6-93 6-94 Description Zero accumulator P register and OVC Disable access to protected space Page 6-396 6-91
6-17
ABORTI
ABORTI SYNTAX OPTIONS ABORTI Operands Description None OPCODE

0000 0000 0000 0001
Abort Interrupt OBJMODE RPT X CYC 2
Abort interrupt. This instruction is available for emulation purposes. Generally, a program uses the IRET instruction to return from an interrupt. The IRET instruction restores all of the values that were saved to the stack during the automatic context save. In restoring status register ST1 and the debug status register (DBGSTAT), IRET restores the debug context that was present before the interrupt. In some target applications, you might have interrupts that must not be returned from by the IRET instruction. Not using IRET can cause a problem for the emulation logic, because the emulation logic assumes that the original debug context will be restored. The abort interrupt (ABORTI) instruction is provided as a means to indicate that the debug context will not be restored and the debug logic needs to be reset to its default state. As part of its operation, the ABORTI instruction:
-
Sets the DBGM bit in ST1. This disables debug events. Modifies select bits in the DBGSTAT register. This effect is a resetting of the debug context. If the CPU was in the debug-halt state before the interrupt occurred, the CPU does not halt when the interrupt is aborted.
The ABORTI instruction does not modify the DBGIER, the IER, the INTM bit or any analysis registers (for example, registers used for breakpoints, watch points, and data logging). Flags and Modes Repeat
DBGM
The DBGM bit is set.
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
6-18
ABS ACC
ABS ACC SYNTAX OPTIONS ABS ACC Operands Description

ACC
Absolute Value of Accumulator OPCODE

1111 1111 0101 0110
OBJMODE RPT X
CYC 1
Accumulator register The content of the ACC register is replaced with its absolute value:
if(ACC = 0x8000 0000) V = 1; If (OVM = 1) ACC = 0x7FFF FFFF; else ACC = 0x8000 0000; else if(ACC < 0) ACC = ACC;
Flags and N Modes

Z C V
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. C is cleared by this operation. If (ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value and V is set. Otherwise, V is not affected. If (ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value, and the ACC value after the operation depends on the state of OVM: If OVM is cleared, ACC will be filled with 0x8000 0000. If OVM is set ACC will be saturated to 0x7FFF FFFF. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
OVM
Repeat
Example
; Take MOVL SETC ABS MOVL
absolute value of VarA, make sure value is saturated: ACC,@VarA ; Load ACC with contents of VarA OVM ; Turn overflow mode on ACC ; Absolute of ACC and saturate @VarA,ACC ; Store result into VarA
6-19
ABSTC ACC
ABSTC ACC SYNTAX OPTIONS ABSTC ACC Operands Description

ACC
Absolute Value of Accumulator and Load TC OPCODE

0101 0110 0101 1111
OBJMODE RPT 1
CYC 1
Accumulator register Replace the content of the ACC register with its absolute value and load the test control (TC) bit with the sign bit XORed with the previous value of the test control bit:
if(ACC = 0x8000 0000) { If (OVM = 1) ACC = 0x7FFF FFFF; else ACC = 0x8000 0000; V = 1; TC = TC XOR 1; { else { if(ACC < 0) ACC = ACC; TC = TC XOR 1; } C = 0;
Flags and Modes
N Z C V
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. The C flag bit is cleared. If (ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value and V is set; otherwise, V is not affected. If (ACC < 0) at the start of the operation, then TC = TC XOR 1; otherwise, TC is not affected. If at the start of the operation, ACC = 0x8000 0000, then this is considered an overflow value and the ACC value after the operation depends on OVM. If OVM is cleared and TC == 1, ACC will be filled with 0x8000 0000. If OVM is set and TC = 1, ACC will be saturated to 0x7FFF FFFF. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
TC
OVM
Repeat
6-20
ABSTC ACC
Example
; Calculate signed: Quot16 = Num16/Den16, Rem16 = Num16%Den16 CLRC TC ; Clear TC flag, used as sign flag MOV ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOV T,@AH ; Temp save Den16 in T register MOV ACC,@Num16 << 16 ; AH = Num16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOVU ACC,@AH ; AH = 0, AL = Num16 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@T ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV ACC,@AL << 16 ; AH = Quot16, AL = 0 NEGTC ACC ; Negate if TC = 1 MOV @Quot16,AH ; Store quotient in Quot16
6-21
ADD ACC,#16bit<<#0..15
ADD ACC,#16bit<<#0..15 SYNTAX OPTIONS ADD ACC,#16bit<<#0..15 OPCODE

1111 1111 0001 SHFT CCCC CCCC CCCC CCCC
Add Value to Accumulator OBJMODE RPT X CYC 1
Operands
ACC #16bit #0..15
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Add the left shifted 16-bit immediate constant value to the ACC register. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = ACC + S:16bit << shift value; else // sign extension mode disabled ACC = ACC + 0:16bit << shift value;
Description
Smart Encoding: If #16bit is an 8-bit number and the shift is 0, then the assembler will encode this instruction as ADDB ACC, #8bit to improve efficiency. To override this encoding, use the ADDW ACC, #16bit instruction alias. Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else the flag is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else the flag is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit immediate constant will be sign-extended before the addition. Else, the value will be zero extended. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
SXM OVM
Repeat
6-22
ADD ACC,#16bit<<#0..15
Example
; Calculate signed value: SETC SXM MOV ACC,@VarB << #10 ADD ACC,#23 << #6
ACC = (VarB << 10) + (23 << 6); ; Turn sign extension mode on ; Load ACC with VarB left shifted by 10 ; Add 23 left shifted by 6 to ACC
6-23
ADD ACC,loc16 << T
ADD ACC,loc16 << T SYNTAX OPTIONS ADD ACC,loc16<< T Operands

ACC loc16 T
Add Value to Accumulator OPCODE

0101 0110 0010 0011 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register, XT(31:16) Add to the ACC register the left-shifted contents of the 16-bit location pointed to by the loc16 addressing mode. The shift value is specified by the four least significant bits of the T register, T(3:0) = shift value = 0..15. Higher order bits of T are ignored. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = ACC + S:[loc16] << T(3:0); else // sign extension mode disabled ACC = ACC + 0:[loc16] << T(3:0);
Description
Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If OVM = 0, disabled and the operation generates a positive overflow, then the counter is incremented; if the operation generates a negative overflow, then the counter is decremented. If OVM = 1, enabled, then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the addition. Else, the value will be zero extended. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
SXM
OVM
Repeat
Example
; Calculate signed value: ACC = (VarA << SB) + (VarB << SB) SETC SXM ; Turn sign extension mode on MOV T,@SA ; Load T with shift value in SA MOV ACC,@VarA << T ; Load in ACC shifted contents of VarA MOV T,@SB ; Load T with shift value in SB ADD ACC,@VarB << T ; Add to ACC shifted contents of VarB
6-24
ADD ACC,loc16 << #0..16
ADD ACC,loc16 << #0..16 SYNTAX OPTIONS ADD ACC,loc16<<#0 ADD ACC,loc16 << #1..15 ADD ACC,loc16 << #16 ADD ACC,loc16<<0...15 Operands
ACC loc16 #0..16
Add Value to Accumulator OPCODE

1000 0001 LLLL LLLL 0101 0110 0000 0100 0000 SHFT LLLL LLLL 0000 0101 LLLL LLLL 1010 SHFT LLLL LLLL
OBJMODE RPT 1 1 X 0 Y Y Y
CYC N+1 N+1 N+1 N+1
Accumulator register Addressing mode (see Chapter 5) Shift value (default is << #0 if no value specified) Add the left shifted 16-bit location pointed to by the loc16 addressing mode to the ACC register. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = ACC + S:[loc16] << shift value; else // sign extension mode disabled ACC = ACC + 0:[loc16] << shift value;
Description
Flags and Modes
Z N C
After the addition, the Z flag is set if ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. Exception: If a shift of 16 is used, the ADD instruction can set C but not clear C.
V OVC
If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the addition. Else, the value will be zero extended. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. If the operation is repeatable, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled. If the operation is not repeatable, the instruction will execute only once.
6-25
SXM
OVM
Repeat
ADD ACC,loc16 << #0..16
Example
; Calculate signed value: ACC = VarA << 10 + VarB << 6; SETC SXM ; Turn sign extension mode on MOV ACC,@VarA << #10 ; Load ACC with VarA left shifted by 10 ADD ACC,@VarB << #6 ; Add VarB left shifted by 6 to ACC
6-26
ADD AX, loc16
ADD AX, loc16 SYNTAX OPTIONS ADD AX, loc16 Operands

AX loc16
Add Value to AX OPCODE

1001 010A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Add the contents of the location pointed to by the loc16 addressing mode to the specified AX register (AH or AL) and store the result in the AX register:
Description
Flags and Modes
After the addition, AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set, otherwise it is cleared. After the addition, AX is tested for a zero condition. The zero flag bit is set if the operation results in AX = 0; otherwise it is cleared. If the addition generates a carry, C is set; otherwise, C is cleared. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Add the contents of VarA with VarB and store in VarC MOV AL,@VarA ; Load AL with contents of VarA ADD AL,@VarB ; Add to AL contents of VarB MOV @VarC,AL ; Store result in VarC
6-27
ADD loc16, AX
ADD loc16, AX SYNTAX OPTIONS ADD loc16, AX Operands

loc16 AX
Add AX to Specified Location OPCODE

0111 001A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Add the contents of the specified AX register (AH or AL) to the location pointed to by the loc16 addressing mode and store the results in location pointed to by loc16:
[loc16] = [loc16] + AX;
Description
This is a read-modify-write operation. Flags and Modes

N
After the addition, [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set, otherwise it is cleared. After the addition, [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0; otherwise it is cleared If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Add the contents of VarA to index register AR0: MOV AL,@VarA ; Load AL with contents of VarA ADD @AR0,AL ; AR0 = AR0 + AL ; Add the contents of VarB to VarC: MOV AH,@VarB ; Load AH with contents of VarB ADD @VarC,AH ; VarC = VarC + AH
6-28
ADD loc16,#16bitSigned
ADD loc16,#16bitSigned SYNTAX OPTIONS ADD loc16,#16bitSigned
Add Constant to Specified Location OPCODE

0000 1000 LLLL LLLL CCCC CCCC CCCC CCCC
OBJMODE RPT X
CYC 1
Operands
loc16 #16bitSigned
Addressing mode (see Chapter 5) 16-bit immediate signed constant value
Description
Add the specified signed 16-bit immediate constant to the signed 16-bit content of the location pointed to by the loc16 addressing mode and store the 16-bit result in the location pointed to by loc16:
[loc16] = [loc16] + 16bitSigned;
Smart Encoding: If loc16 = AL or AH and #16bitSigned is an 8-bit number then the assembler will encode this instruction as ADDB AX, #16bitSigned to improve efficiency. To override this encoding, use the ADDW loc16, #16bitSigned instruction alias. Flags and Modes
N
After the addition, if bit 15 of [loc16] is 1, then the N bit is set; else N cleared. After the addition, if [loc16] is zero, the Z is set, else Z is cleared. If the addition generates a carry, C is set; otherwise, C is cleared. If an overflow occurs, V is set; otherwise, V is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C V
Repeat
Example
; Calculate: ; VarA = VarA + 10 ; VarB = VarB 3 ADD @VarA,#10 ADD @VarB,#3
; VarA = VarA + 10 ; VarB = VarB 3
6-29
ADDB ACC,#8bit
ADDB ACC,#8bit SYNTAX OPTIONS ADDB ACC,#8bit Operands

ACC #8bit
Add 8-bit Constant to Accumulator OPCODE

0000 1001 CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator register 8-bit immediate unsigned constant value Add an 8-bit, zero-extended constant to the ACC register:
ACC = ACC + 0:8bit;
Description
Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
OVM
Repeat
Example
; Increment contents of 32-bit location VarA: MOVL ACC,@VarA ADDB ACC,#1 MOVL @VarA,ACC ; Load ACC with contents of VarA ; Add 1 to ACC ; Store result back into VarA
6-30
ADDB AX, #8bitSigned
ADDB AX, #8bitSigned SYNTAX OPTIONS

ADDB AX, #8bitSigned
Add 8-bit Constant to AX OPCODE

1001 110A CCCC CCCC
OBJMODE RPT X
CYC 1
Operands
AX #8bitSigned
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate signed 2s complement constant value (-128 to 127)
Description
Add the sign extended 8-bit constant to the specified AX register (AH or AL) and store the result in the AX register:
AX = AX + S:8bit;
Flags and Modes
After the addition, AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set; otherwise it is cleared. After the addition, AX is tested for a zero condition. The zero flag bit is set if the operation results in AX = 0, otherwise it is cleared If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Add 2 to VarA and subtract 3 from VarB: MOV ADDB MOV MOV ADDB MOV AL,@VarA AL,#2 @VarA,AL AL,@VarB AL,#3 @VarB,AL ; ; ; ; ; ; Load AL with contents of VarA Add to AL the value 0x0002 (2) Store result in VarA Load AL with contents of VarB Add to AL the value 0xFFFD (3) Store result in VarB
6-31
ADDB SP, #7bit
ADDB SP, #7bit SYNTAX OPTIONS ADDB SP, #7bit Operands

SP #7bit
Add 7-bit Constant to Stack Pointer OPCODE

1111 1110 0CCC CCCC
OBJMODE RPT X
CYC 1
Stack pointer 7-bit immediate unsigned constant value Add a 7-bit unsigned constant to SP and store the result in SP:
SP = SP + 0:7bit;
Description
Flags and Modes Repeat
None
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once
FuncA: ADDB SP, #N ; Function with local variables on stack. ; Reserve N 16-bit words of space for ; local variables on stack:
Example
. . . SUBB SP, #N LRETR
; Deallocate reserved stack space. ; Return from function.
6-32
ADDB XARn, #7bit
ADDB XARn, #7bit SYNTAX OPTIONS ADDB XARn, #7bit Operands Description
XARn
Add 7-bit Constant to Auxiliary Register OPCODE

1101 1nnn 0CCC CCCC
OBJMODE RPT X
CYC 1
XAR0XAR7, 32-bit auxiliary registers Add a 7-bit unsigned constant to XARn and store the result in XARn:
XARn = XARn + 0:7bit;
None
MOVL XAR1,#VarA MOVL XAR2,*XAR1 ADDB XAR2,#10h ; ; ; ; Initialize XAR1 pointer with address of VarA Load XAR2 with contents of VarA XAR2 = VarA + 0x10
Example
6-33
ADDCL ACC,loc32
ADDCL ACC,loc32 SYNTAX OPTIONS ADDCL ACC,loc32 Operands

ACC loc32
Add 32-bit Value Plus Carry to Accumulator OPCODE

0101 0110 0100 0000 xxxx xxxx LLLL LLLL
OBJMODE RPT 1
CYC 1
Accumulator register Addressing mode (see Chapter 5) Add to the ACC register the 32-bit content of the location pointed to by the loc32 addressing mode:
ACC = ACC + [loc32] + C;
Description
Flags and Z Modes
After the addition, the Z flag is set if the ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The state of the carry bit before execution is included in the addition. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
N C
V OVC
OVM
Repeat
Example
; Add two 64-bit values (VarA and VarB) and store result in VarC: MOVL ACC,@VarA+0 ; Load ACC with contents of the low ; 32 bits of VarA ADDUL ACC,@VarB+0 ; Add to ACC the contents of the low ; 32 bits of VarB MOVL @VarC+0,ACC ; Store low 32-bit result into VarC MOVL ACC,@VarA+2 ; Load ACC with contents of the high ; 32 bits of VarA ADDCL ACC,@VarB+2 ; Add to ACC the contents of the high ; 32 bits of VarB with carry MOVL @VarC+2,ACC ; Store high 32-bit result into VarC
6-34
ADDCU ACC,loc16
ADDCU ACC,loc16 SYNTAX OPTIONS ADDCU ACC,loc16 Operands

ACC loc16
Add Unsigned Value Plus Carry to Accumulator OPCODE

0000 1100 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Addressing mode (see Chapter 5) Add the 16-bit contents of the location pointed to by the loc16 addressing mode, zero extended, plus the content of the carry flag bit to the ACC register:
ACC = ACC + 0:[loc16] + C;
Description
Flags and Modes
Z N C
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The state of the carry bit before execution is included in the addition. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
V OVC
OVM
Repeat
Example
; Add three 32-bit MOVU ACC,@VarAlow ADD ACC,@VarAhigh ADDU ACC,@VarBlow ADD ACC,@VarBhigh ADDCU ACC,@VarClow ADD ACC,@VarChigh
unsigned variables by 16-bit parts: ; AH = 0, AL = VarAlow << 16 ; AH = VarAhigh, AL = VarAlow ; ACC = ACC + 0:VarBlow << 16 ; ACC = ACC + VarBhigh << 16 ; ACC = ACC + VarClow + Carry << 16 ; ACC = ACC + VarChigh << 16
6-35
ADDL ACC,loc32
ADDL ACC,loc32 SYNTAX OPTIONS ADDL ACC,loc32 Operands

ACC loc32
Add 32-bit Value to Accumulator OPCODE

0000 0111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Add to the ACC register the 32-bit content of the location pointed to by the loc32 addressing mode:
ACC = ACC + [loc32];
Description
Flags and Modes
N Z C V OCV
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the addition, the Z flag is set if the ACC is zero, else Z is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
OVM
Repeat
Example
; Calculate the 32-bit value: VarC = VarA + VarB MOVL ACC,@VarA ; Load ACC with contents of VarA ADDL ACC,@VarB ; Add to ACC the contents of VarB MOVL @VarC,ACC ; Store result into VarC
6-36
ADDL ACC,P << PM
ADDL ACC,P << PM SYNTAX OPTIONS ADDL ACC,P << PM OPCODE
Add Shifted P to Accumulator OBJMODE RPT CYC
0001 0000 1010 1100 X Y N+1 Note: This instruction is an alias for the MOVA T,loc16 operation with loc16 = @T addressing mode.
Operands
ACC P << PM
Accumulator register Product register Product shift mode Add to the ACC register the contents of the P register, shifted as specified by the product shift mode (PM):
ACC = ACC + P << PM
Description
Flags and Modes
Z N C V OCV
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows if overflow mode is disabled.
OVM
PM
Repeat
Example
; Calculate: Y = ((M*X >> 4) ; Y, M, X, B are Q15 values SPM 4 ; SETC SXM ; MOV T,@M ; MPY P,T,@X ; MOV ACC,@B << 11 ; ADDL ACC,P << PM ; MOVH @Y,ACC << 5 ;
+ (B << 11)) >> 10 Set product shift to >> 4 Enable sign extension mode T = M P = M * X ACC = S:B << 11 ACC = (M*X >> 4) + (S:B << 11) Store Q15 result into Y
6-37
ADDL loc32,ACC
ADDL loc32,ACC SYNTAX OPTIONS ADDL loc32, ACC Operands

loc32 ACC
Add Accumulator to Specified Location OPCODE

0101 0110 0000 0001 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator register Add to the ACC register the 32-bit content of the location pointed to by the loc32 addressing mode:
[loc32] = [loc32] + ACC;
Description
This is a read-modify-write operation. Flags and Modes

N Z C V OCV
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the addition, the Z flag is set if the ACC is zero, else Z is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set, the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
OVM
Repeat
Example
; Increment the 32-bit value VarA: MOVB ACC,#1 ; Load ACC with 0x00000001 ADDL @VarA,ACC ; VarA = VarA + ACC
6-38
ADDU ACC,loc16
ADDU ACC,loc16 SYNTAX OPTIONS ADDU ACC,loc16 Operands

ACC loc16
Add Unsigned Value to Accumulator OPCODE

0000 1101 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Add the 16-bit contents of the location pointed to by the loc16 addressing mode to the ACC register. The addressed location is zero extended before the add:
ACC = ACC + 0:[loc16];
Description
Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If (OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If (OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
OVM
Repeat
Example
; Add three 32-bit MOVU ACC,@VarAlow ADD ACC,@VarAhigh ADDU ACC,@VarBlow ADD ACC,@VarBhigh ADDCU ACC,@VarClow ADD ACC,@VarChigh
unsigned variables by 16-bit parts: ; AH = 0, AL = VarAlow << 16 ; AH = VarAhigh, AL = VarAlow ; ACC = ACC + 0:VarBlow << 16 ; ACC = ACC + VarBhigh << 16 ; ACC = ACC + VarClow + Carry << 16 ; ACC = ACC + VarChigh << 16
6-39
ADDUL P,loc32
ADDUL P,loc32 SYNTAX OPTIONS ADDUL P,loc32 Operands

P loc32
Add 32-bit Unsigned Value to P OPCODE

0101 0110 0101 0111 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Addressing mode (see Chapter 5) Add to the P register the 32-bit content of the location pointed to by the loc32 addressing mode. The addition is treated as an unsigned ADD operation:
P = P + [loc32]; // unsigned add
Description
Note: The difference between a signed and unsigned 32-bit add is in the treatment of the overflow counter (OVC). For a signed ADD, the OVC counter monitors positive/negative overflow. For an unsigned ADD, the OVC unsigned (OVCU) counter monitors the carry.
Flags and Modes
N Z C V OVCU
After the addition, if bit 31 of the P register is 1, then set the N flag; otherwise clear N. After the addition, if the value of the P register is 0, then set the Z flag; otherwise clear Z. If the addition generates a carry, set C; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is incremented when the addition operation generates an unsigned carry. The OVM mode does not affect the OVCU counter. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Add 64-bit VarA + VarB and store result in VarC: MOVL P,@VarA+0 ; Load P with low 32 bits of VarA MOVL ACC,@VarA+2 ; Load ACC with high 32 bits of VarA ADDUL P,@VarB+0 ; Add to P unsigned low 32 bits of VarB ADDCL ACC,@VarB+2 ; Add to ACC with carry high 32 bits of VarB MOVL @VarC+0,P ; Store low 32-bit result into VarC MOVL @VarC+2,ACC ; Store high 32-bit result into VarC
6-40
ADDUL ACC, loc32
ADDUL ACC, loc32 SYNTAX OPTIONS ADDUL ACC, loc32 Operands

ACC loc32
Add 32-bit Unsigned Value to Accumulator OPCODE

OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Add to the ACC register the unsigned 32-bit content of the location pointed to by the loc32 addressing mode:
ACC = ACC + [loc32]; // unsigned add
Description
Note: The difference between a signed and unsigned 32-bit add is in the treatment of the overflow counter (OVC). For a signed ADD, the OVC counter monitors positive/negative overflow. For an unsigned ADD, the OVC unsigned (OVCU) counter monitors the carry.
Flags and Modes
Z N C V OVCU
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is incremented when the addition operation generates an unsigned carry. The OVM mode does not affect the OVCU counter. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVCU will count intermediate carries.
Repeat
Example
; Add two 64-bit values (VarA and VarB) and store result in VarC: MOVL ACC,@VarA+0 ; Load ACC with contents of the low ; 32 bits of VarA ADDUL ACC,@VarB+0 ; Add to ACC the contents of the low ; 32 bits of VarB MOVL @VarC+0,ACC ; Store low 32-bit result into VarC MOVL ACC,@VarA+2 ; Load ACC with contents of the high ; 32 bits of VarA ADDCL ACC,@VarB+2 MOVL @VarC+2,ACC ; Add to ACC the contents of the high ; 32 bits of VarB with carry ; Store high 32-bit result into VarC
6-41
ADRK #8bit
ADRK #8bit SYNTAX OPTIONS ADRK #8bit Operands Description

#8bit
Add to Current Auxiliary Register OPCODE

1111 1100 IIII IIII
OBJMODE RPT X
CYC 1
8-bit immediate constant value Add the 8-bit unsigned constant to the XARn register pointed to by ARP:
XAR(ARP) = XAR(ARP) + 0:8bit;
ARP
The 3-bit ARP points to the current valid Auxiliary Register, XAR0 to XAR7. This pointer determines which Auxiliary register is modified by the operation. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once
Example
TableA: .word 0x1111 .word 0x2222 .word 0x3333 .word 0x4444 FuncA: MOVL XAR1,#TableA MOVZ AR2,*XAR1
; ; ; ;
Initialize XAR1 pointer Load AR2 with the 16-bit value pointed to by XAR1 (0x1111) Set ARP = 1
ADRK #2 MOVZ AR3,*XAR1
; Increment XAR1 by 2 ; Load AR3 with the 16-bit value ; pointed to by XAR1 (0x3333)
6-42
AND ACC,#16bit << #0..16
AND ACC,#16bit << #0..16 SYNTAX OPTIONS AND ACC, #16bit << #0..15 AND ACC, #16bit << #16 OPCODE
0011 1110 0000 SHFT CCCC CCCC CCCC CCCC 0101 0110 0000 1000 CCCC CCCC CCCC CCCC
Bitwise AND OBJMODE RPT 1 1 CYC 1 1
Operands
ACC #16bit #0..16
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Perform a bitwise AND operation on the ACC register with the given 16-bit unsigned constant value left shifted as specified. The value is zero extended and lower order bits are zero filled before the AND operation. The result is stored in the ACC register:
ACC = ACC AND (0:16bit << shift value);
Description
Flags and Modes
N Z
The load to ACC is tested for a negative condition. If bit 31 of ACC is 1, then the negative flag bit is set; otherwise it is cleared. The load to ACC is tested for a zero condition. The zero flag bit is set if the operation generates ACC = 0; otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate the 32-bit value: VarA = VarA AND 0x0FFFF000 MOVL ACC,@VarA ; Load ACC with contents of VarA AND ACC,#0xFFFF << 12 ; AND ACC with 0x0FFFF000 MOVL @VarA,ACC ; Store result in VarA
6-43
AND ACC, loc16
AND ACC, loc16 SYNTAX OPTIONS AND ACC, loc16 Operands

ACC loc16
Bitwise AND OPCODE

1000 1001 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Perform a bitwise AND operation on the ACC register with the zero-extended content of the location pointed to by the loc16 address mode. The result is stored in the ACC register:
ACC = ACC AND 0:[loc16];
Description
Flags and Modes
N Z
Clear flag. The load to ACC is tested for a zero condition. The zero flag bit is set if the operation generates ACC = 0; otherwise it is cleared This operation is repeatable. If the operation follows a RPT instruction, then the AND instruction will be executed N+1 times. The state of the Z and N flags will reflect the final result.
Repeat
Example
; Calculate the 32-bit value: VarA = VarA AND 0:VarB MOVL ACC,@VarA ; Load ACC with contents of VarA AND ACC,@VarB ; AND ACC with contents of 0:VarB MOVL @VarA,ACC ; Store result in VarA
6-44
AND AX, loc16, #16bit
AND AX, loc16, #16bit SYNTAX OPTIONS AND AX, loc16, #16bit OPCODE
1100 110A LLLL LLLL CCCC CCCC CCCC CCCC
Bitwise AND OBJMODE RPT X CYC 1
Operands
AX loc16 #16bit
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) 16-bit immediate constant value Perform a bitwise AND operation on the 16-bit contents of the location pointed to by the loc16 addressing mode with the specified 16-bit immediate constant. The result is stored in the specified AX register:
AX = [loc16] AND 16bit;
Description
Flags and Modes
The load to AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set; otherwise it is cleared. The load to AX is tested for a zero condition. The zero flag bit is set if the operation generates AX = 0; otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Branch if either of Bits 2 and 7 of VarA are non-zero: AND AL,@VarA,#0x0084 ; AL = VarA AND 0x0084 SB Dest,NEQ ; Branch if result is non-zero ; Merge Bits 0,1,2 of VarA with Bits 8,9,10 of VarB and store in ; VarC in bit locations 0,1,2,3,4,5: AND AL,@VarA,#0x0007 ; Keep bits 0,1,2 of VarA AND AH,@VarB,#0x0700 ; Keep bits 8,9,10 of VarB LSR AH,#5 ; Scale back bits 8,9,10 to bits 3,4,5 OR AL,@AH ; Merge bits MOV @VarC,AL ; Store result in VarC
6-45
AND IER,#16bit
AND IER,#16bit SYNTAX OPTIONS AND IER,#16bit
Bitwise AND to Disable Specified CPU Interrupts OPCODE

0111 0110 0010 0110 CCCC CCCC CCCC CCCC
OBJMODE RPT X
CYC 2
Operands
IER #16bit
Interrupt enable register 16-bit immediate constant value (0x0000 to 0xFFFF) Disable specific interrupts by performing a bitwise AND operation with the IER register and the 16-bit immediate value. The result is stored in the IER register:
IER = IER AND #16bit;
Description
None
; Disable INT1 and INT6 only. Do not modify state of other ; interrupts enable: AND IER,#0xFFDE ; Disable INT1 and INT6
Example
6-46
AND IFR,#16bit
AND IFR,#16bit SYNTAX OPTIONS AND IFR,#16bit
Bitwise AND to Clear Pending CPU Interrupts OPCODE

OBJMODE RPT X
CYC 2
Operands
IFR #16bit
Interrupt flag register 16-bit immediate constant value (0x0000 to 0xFFFF) Clear specific pending interrupts by performing a bitwise AND operation with the IFR register and the 16-bit immediate value. The result of the AND operation is stored in the IFR register:
IFR = IFR AND #16bit; Note: Interrupt hardware has priority over CPU instruction operation in cases where the interrupt flag is being simultaneously modified by the hardware and the instruction.
Description
None
; Clear the contents of the IFR register. Disables all ; pending interrupts: AND IFR,#0x0000 ; Clear IFR register
Example
6-47
AND loc16, AX
AND loc16, AX SYNTAX OPTIONS AND loc16, AX Operands

loc16 AX
Bitwise AND OPCODE

1100 000A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Perform a bitwise AND operation on the contents of the location pointed to by the loc16 addressing mode with the specified AX register. The result is stored in location pointed to by loc16:
[loc16] = [loc16] AND AX;
Description
This is a read-modify-write operation. Flags and Modes Z N The load to [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set; otherwise it is cleared. The load to [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates ([loc16] = 0); otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
; AND the contents of VarA with VarB and store in VarB: MOV AL,@VarA ; Load AL with contents of VarA AND @VarB,AL ; VarB = VarB AND AL
Repeat
Example
6-48
AND AX, loc16
AND AX, loc16 SYNTAX OPTIONS AND AX, loc16 Operands

AX loc16
Bitwise AND OPCODE

1100 111A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Perform a bitwise AND operation on the contents of the specified AX register with the 16-bit contents of the location pointed to by the loc16 addressing mode. The result is stored in the AX register:
AX = AX AND 16bit;
Description
Flags and Modes
Repeat
Example
; AND the contents of VarA and VarB and branch if non-zero: MOV AL,@VarA ; Load AL with contents of VarA AND AL,@VarB ; AND AL with contents of VarB SB Dest,NEQ ; Branch if result is non-zero
6-49
AND loc16,#16bitSigned
AND loc16,#16bitSigned SYNTAX OPTIONS AND loc16,#16bitSigned OPCODE

Bitwise AND OBJMODE RPT X CYC 1
Operands
loc16 #16bitSigned
Addressing mode (see Chapter 5) 16-bit signed immediate constant value Perform a bitwise AND operation on the 16-bit content of the location pointed to by the loc16 addressing mode and the specified 16-bit immediate constant. The result is stored in the location pointed to by loc16:
[loc16] = [loc16] AND 16bit;
Description
Smart Encoding: If loc16 = AH or AL and #16bitSigned is an 8-bit number, then the assembler will encode this instruction as ANDB AX, #8-bit to improve efficiency. To override this, use the ANDW AX, #16bitSigned instruction alias. Flags and Modes
N Z
After the operation if bit 15 of [loc16] 1, set N; otherwise, clear N. After the operation if [loc16] is zero, set Z; otherwise, clear Z. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Clear Bits 3 and 11 of VarA: ; VarA = VarA AND #~(1 << 3 | 1 << 11) AND @VarA,#~(1 << 3 | 1 ; Clear bits 3 and 11 of VarA << 11)
6-50
ANDB AX, #8bit
ANDB AX, #8bit SYNTAX OPTIONS ANDB AX, #8bit Operands

AX #8bit
Bitwise AND 8-bit Value OPCODE

1001 000A CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate constant value Perform a bitwise AND operation with the content of the specified AX register (AH or AL) with the given 8-bit unsigned immediate constant zero extended. The result is stored in AX:
AX = AX AND 0:8bit;
Description
Flags and Modes
Repeat
Example
; Add VarA to VarB, keep LSByte and store result in VarC: MOV AL,@VarA ; Load AL with contents of VarA ADD AL,@VarB ; Add to AL contents of VarB ANDB AL,#0xFF ; AND contents of AL with 0x00FF MOV @VarC,AL ; Store result in VarC
6-51
ASP
ASP SYNTAX OPTIONS ASP Operands Description None OPCODE

0111 0110 0001 1011
Align Stack Pointer OBJMODE RPT X CYC 1
Ensure that the stack pointer (SP) is aligned to an even address. If the least significant bit of SP is 1, SP points to an odd address and must be moved by incrementing SP by 1. The SPA bit is set as a record of this alignment. If instead the ASP instruction finds that the SP already points to an even address, SP is left unchanged and the SPA bit is cleared to indicate that no alignment has taken place. In either case, the change to the SPA bit is made in the decode 2 phase of the pipeline.
if(SP = odd) SP = SP + 1; SPA = 1;else SPA = 0;
If you wish to undo a previous alignment by the ASP instruction, use the NASP instruction. Flags and Modes Repeat SPA If SP holds an odd address before the operation, SPA is set; otherwise, SPA is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Alignment of stack pointer in interrupt service routine:
; Vector table: INTx: .long INTxService . . INTxService: ASP . . . NASP IRET ; INTx interrupt vector
Example
; Align stack pointer
; Re-align stack pointer ; Return from interrupt.
6-52
ASR AX,#1...16
ASR AX,#1...16 SYNTAX OPTIONS ASR AX,#1...16 Operands

AX 1016
Arithmetic Shift Right OPCODE

1111 1111 101A SHFT
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Shift value Perform an arithmetic right shift on the content of the specified AX register (AH or AL) by the amount given in the shift value field. During the shift, the value is sign extended and the last bit to be shifted out of the AX register is stored in the carry status flag bit:
AX Last bit out C Right shift (Immediate value) Discard other bits AX
Description
SIGN
Flags and Modes
After the shift, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. After the shift, if AX is 0, then the Z bit is set; otherwise it is cleared. The last bit to be shifted out of AH or AL is stored in C. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C
Repeat
Example
; Calculate signed value: VarC = (VarA + VarB) >> 2 MOV AL,@VarA ; Load AL with contents of VarA ADD AL,@VarB ; Add to AL contents of VarB ASR AL,#2 ; Scale result by 2 MOV @VarC,AL ; Store result in VarC
6-53
ASR AX,T
ASR AX,T SYNTAX OPTIONS ASR AX,T Operands

AX T
Arithmetic Shift Right OPCODE

1111 1111 0110 010A
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register Perform an arithmetic shift right on the content of the specified AX register as specified by the four least significant bits of the T register, T(3:0) = shift value = 015. The contents of higher order bits are ignored. During the shift, the value is sign extended. If the T(3:0) register bits specify a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of AX:
AX Last bit out or cleared C Right shift (Contents of T [3:0]) Discard other bits AX
Description
SIGN
Flags and Modes
After the shift, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. Even if the T(3:0) register bits specify a shift of 0, the value of AH or AL is still tested for the negative condition and N is affected. After the shift, if AX is 0, then the Z bit is set, otherwise it is cleared. Even if the T(3:0) register bits specify a shift of 0, the value of AH or AL is still tested for the zero condition and Z is affected. If T(3:0) specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of AH or AL. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate signed value: VarC = VarA >> VarB; MOV T,@VarB ; Load T with contents of VarB MOV AL,@VarA ; Load AL with contents of VarA ASR AL,T ; Scale AL by value in T bits 0 to 3 MOV @VarC,AL ; Store result in VarC
6-54
ASR64 ACC:P,#1..16
ASR64 ACC:P,#1..16 SYNTAX OPTIONS ASR64 ACC:P,#1..16 Operands

ACC:P #1..16
Arithmetic Shift Right of 64-bit Value OPCODE

0101 0110 1000 SHFT
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Shift value Arithmetic shift right the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field. As the value is shifted, the most significant bits are sign extended and the last bit shifted out is stored in the carry bit flag:
ACC:P Last bit out C Right shift (immediate value) Discard other bits ACC:P
Description
SIGN
Flags and Modes
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. The last bit shifted out of the combined 64-bit value is loaded into the C bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Arithmetic shift right the 64-bit Var64 by 10: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL P,@Var64+0 ; Load P with low 32 bits of Var64 ASR64 ACC:P,#10 ; Arithmetic shift right ACC:P by 10 MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-55
ASR64 ACC:P,T
ASR64 ACC:P,T SYNTAX OPTIONS ASR64 ACC:P,T Operands

ACC:P T
Arithmetic Shift Right of 64-bit Value OPCODE

0101 0110 0010 1100
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Arithmetic shift right the 64-bit combined value of the ACC:P registers by the amount specified in six least significant bits of the T register, T(5:0) = 063. Higher order bits are ignored. As the value is shifted, the most significant bits are sign extended. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC:P registers:
ACC:P Last bit out or cleared C Right shift Contents of T[5:0] Discard other bits ACC:P
Description
SIGN
Flags and Modes
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. If (T[5:0] = 0) clear C; otherwise, the last bit shifted out of the combined 64-bit value is loaded into the C bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C
Repeat
Example
; Arithmetic shift right the 64-bit Var64 by contents of Var16: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL P,@Var64+0 ; Load P with low 32 bits of Var64 MOV T,@Var16 ; Load T with shift value from Var16 ASR64 ACC:P,T ; Arithmetic shift right ACC:P by T(5:0) MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-56
ASRL ACC,T
ASRL ACC,T SYNTAX OPTIONS ASRL ACC,T Operands

ACC T
Arithmetic Shift Right of Accumulator OPCODE

0101 0110 0001 0000
OBJMODE RPT 1
CYC 1
Accumulator register Upper 16 bits of the multiplicand (XT) register Perform an arithmetic shift right on the content of the ACC register as specified by the five least significant bits of the T register, T(4:0) = 031. Higher order bits are ignored. During the shift, the value is sign extended. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC register:
ACC Last bit out or cleared C Right shift (Contents of T[4:0] Discard other bits ACC
Description
SIGN
Flags and Modes
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the zero condition and Z is affected. After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the negative condition and N is affected. If (T(4:0) = 0) then C is cleared; otherwise, the last bit shifted out is loaded into the C flag bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Arithmetic shift right contents of VarA by VarB: MOVL ACC,@VarA ; ACC = VarA MOV T,@VarB ; T = VarB (shift value) ASRL ACC,T ; Arithmetic shift right ACC by T(4:0) MOVL @VarA,ACC ; Store result into VarA
6-57
B 16bitOffset,COND
B 16bitOffset,COND SYNTAX OPTIONS B 16bitOffset,COND Operands

16bitOffset COND
Branch OPCODE
1111 1111 1110 COND CCCC CCCC CCCC CCCC
OBJMODE RPT X
CYC 7/4
16-bit signed immediate constant offset value (32768 to +32767 range) Conditional codes:
COND 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Syntax NEQ EQ GT GEQ LT LEQ HI HIS, C LO, NC LOS NOV OV NTC TC NBIO UNC Description Not Equal To Equal To Greater Then Greater Then Or Equal To Less Then Less Then Or Equal To Higher Higher Or Same, Carry Set Lower, Carry Clear Lower Or Same No Overflow Overflow Test Bit Not Set Test Bit Set BIO Input Equal To Zero Unconditional Flags Tested Z = 0 Z = 1 Z = 0 AND N = 0 N = 0 N = 1 Z = 1 OR N = 1 C = 1 AND Z = 0 C = 1 C = 0 C = 0 OR Z = 1 V = 0 V = 1 TC = 0 TC = 1 BIO = 0
Description
Conditional branch. If the specified condition is true, then branch by adding the signed 16-bit constant value to the current PC value; otherwise continue execution without branching:
If (COND = true) PC = PC + signed 16-bit offset; If (COND = false) PC = PC + 2; Note: If (COND = true) then the instruction takes 7 cycles. If (COND = false) then the instruction takes 4 cycles.
If the V flag is tested by the condition, then V is cleared.
6-58
BANZ 16bitOffset,ARn
BANZ 16bitOffset,ARn SYNTAX OPTIONS BANZ 16bitOffset,ARn
Branch if Auxiliary Register Not Equal to Zero OPCODE

0000 0000 0000 1nnn CCCC CCCC CCCC CCCC
OBJMODE RPT X
CYC 4/2
Operands
16bitOffset ARn
16-bit signed immediate constant value Lower 16 bits of auxiliary registers XAR0 to XAR7 If the 16-bit content of the specified auxiliary register is not equal to 0, then the 16-bit sign offset is added to the PC value. This forces program control to the new address (PC + 16bitOffset). The 16-bit offset is sign extended to 22 bits before the addition. Then, the content of the auxiliary register is decremented by 1. The upper 16 bits of the auxiliary register (ARnH) is not used in the comparison and is not affected by the post decrement:
if( ARn != 0 ) PC = PC + signed 16-bit offset; ARn = ARn 1; ARnH = unchanged; Note: If branch is taken, then the instruction takes 4 cycles If branch is not taken, then the instruction takes 2 cycles
Description
None
; Copy the contents of Array1 to Array2: ; int32 Array1[N]; ; int32 Array2[N]; ; for(i=0; i < N; i++) ; Array2[i] = Array1[i]; MOVL XAR2,#Array1 ; XAR2 = pointer to Array1 MOVL XAR3,#Array2 ; XAR3 = pointer to Array2 MOV @AR0,#(N1) ; Repeat loop N times Loop: MOVL ACC,*XAR2++ ; ACC = Array1[i] MOVL *XAR3++,ACC ; Array2[i] = ACC BANZ Loop,AR0 ; Loop if AR0 != 0, AR0
Example
6-59
BAR 16bitOffset,ARn,ARm,EQ/NEQ
BAR 16bitOffset,ARn,ARm,EQ/NEQ SYNTAX OPTIONS BAR 16bitOffset,ARn,ARm,EQ BAR 16bitOffset,ARn,ARm,NEQ Operands

16bitOffset ARn ARm
Branch on Auxiliary Register Comparison OPCODE

1000 1111 10nn nmmm CCCC CCCC CCCC CCCC 1000 1111 11nn nmmm CCCC CCCC CCCC CCCC
OBJMODE RPT 1 1
CYC 4/2 4/2
16-bit signed immediate constant offset value (32768 to +32767 range) Lower 16 bits of auxiliary registers XAR0 to XAR7 Lower 16 bits of auxiliary registers XAR0 to XAR7
Condition Tested
Syntax NEQ EQ Description
Description
Not Equal To Equal To
ARn != ARm ARn = ARm
Compare the 16-bit contents of the two auxiliary registers ARn and ARm registers and branch if the specified condition is true; otherwise continue execution without branching:
If (tested condition = true) PC = PC + signed 16-bit offset; If (tested condition = false) PC = PC + 2; Note: If (tested condition = true) then the instruction takes 4 cycles. If (tested condition = false) then the instruction takes 2 cycles.
None
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; String compare:
MOVL XAR2,#StringA MOVL XAR3,#StringB MOV @AR4,#0 Loop: MOVZ AR0,*XAR2++ MOVZ AR1,*XAR3++ BAR Exit,AR0,AR4,EQ BAR Loop,AR0,AR1,EQ NotEqual: . Exit: ; XAR2 points to StringA ; XAR3 points to StringB ; AR4 = 0 ; ; ; ; ; AR0 = StringA[i] AR1 = StringB[i], i++ Exit if StringA[i] = 0 Loop if StringA[i] = StringB[i] StringA and B not the same
Example
; StringA and B the same
6-60
BF 16bitOffset,COND
BF 16bitOffset,COND SYNTAX OPTIONS BF 16bitOffset,COND Operands

16bitOffset COND
Branch Fast OPCODE

OBJMODE RPT 1
CYC 4/4
16-bit signed immediate constant offset value (32768 to +32767 range) Conditional codes:
Description
Fast conditional branch. If the specified condition is true, then branch by adding the signed 16-bit constant value to the current PC value; otherwise continue execution without branching:
If (COND = true) PC = PC + signed 16-bit offset; If (COND = false) PC = PC + 2; Note: The branch fast (BF) instruction takes advantage of dual prefetch queue on the C28x core that reduces the cycles for a taken branch from 7 to 4: If (COND = true) then the instruction takes 4 cycles. If (COND = false) then the instruction takes 4 cycles.
6-61
C27MAP
C27MAP SYNTAX OPTIONS C27MAP OPCODE

0101 0110 0011 1111
Set the M0M1MAP Bit OBJMODE RPT X CYC 5
Note: This instruction is an alias for the CLRC M0M1MAP operation.
Operands Description
None Clear the M0M1MAP status bit, configuring the mapping of the M0 and M1 memory blocks for C27x object-compatible operation. The memory blocks are mapped as follows:
C28 at Reset (M0M1MAP = 1) C27x Compatible Mapping (M0M1MAP = 0) Program Space 00 0000 M1 00 0400 M0 00 0400 M0 00 07FF M1 00 07FF Data Space 00 0000
Program Space M0
Data Space M0
M1
M1
Note: The pipeline is flushed when this instruction is executed.
M0M1MAP The M0M1MAP bit is cleared.
; Set the device Reset: C27OBJ C28ADDR .c28_amode C27MAP . . mode from reset to C27x object-compatible mode: ; ; ; ; Enable C27x Object Mode Enable C27x/C28x Address Mode Tell assembler we are using C27x/C28x addressing Enable C27x Mapping Of M0 and M1 blocks
Example
6-62
C27OBJ
C27OBJ SYNTAX OPTIONS C27OBJ OPCODE

0101 0110 0011 0110
Clear the OBJMODE Bit OBJMODE RPT X CYC 5
Note: This instruction is an alias for the CLRC OBJMODE operation.
None Clear the OBJMODE status bit in Status Register ST1, configuring the device to execute C27x object code. This is the default mode of the processor after reset.
Clear the OBJMODE bit.
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Set the device mode from reset to C27x:
Reset: C27OBJ C28ADDR .c28_amode C27MAP . . ; ; ; ; Enable C27x Object Mode Enable C27x/C28x Address Mode Tell assembler we are in C27x/C28x addr mode Enable C27x Mapping Of M0 and M1 blocks
Example
6-63
C28ADDR
C28ADDR SYNTAX OPTIONS C28ADDR OPCODE

0101 0110 0001 0110
Clear the AMODE Status Bit OBJMODE RPT X CYC 1
Note: This instruction is an alias for the CLRC AMODE operation.
None Clear the AMODE status bit in Status Register ST1, putting the device in C27x/C28x addressing mode (see Chapter 5).
Note: This instruction does not flush the pipeline.
AMODE The AMODE bit is cleared.
; Execute the operation VarC = VarA + VarB written in ; C2xLP syntax: LPADDR ; Full C2xLP address compatible mode .lp_amode ; Tell assembler we are in C2xLP mode LDP #VarA ; Initialize DP (low 64K only) LACL VarA ; ACC = VarA (ACC high = 0) ADDS VarB ; ACC = ACC + VarB (unsigned) SACL VarC ; Store result into VarC C28ADDR ; Return to C28x address mode .c28_amode ; Tell assembler we are in C28x mode
Example
6-64
C28MAP
C28MAP SYNTAX OPTIONS C28MAP OPCODE

0101 0110 0001 1010
Set the M0M1MAP Bit OBJMODE RPT X CYC 5
Note: This instruction is an alias for the SETC M0M1MAP instruction.
None Set the M0M1MAP status bit in Status register ST1, configuring the mapping of the M0 and M1 memory blocks for C28x operation. The memory blocks are mapped as follows:
Program Space M0
Data Space M0
M1
M1
M0M1MAP The M0M1MAP bit is set.
; Set the device mode from reset to C28x mode: Reset: C28OBJ ; Enable C28x Object Mode C28ADDR ; Enable C28x Address Mode .c28_amode ; Tell assembler we are in C28x address mode C28MAP ; Enable C28x Mapping Of M0 and M1 blocks . .
Example
6-65
C28OBJ
C28OBJ SYNTAX OPTIONS C28OBJ OPCODE

0101 0110 0001 1111
Set the OBJMODE Bit OBJMODE RPT X CYC 5
Note: This instruction is an alias for the SETC OBJMODE instruction.
None Set the OBJMODE status bit, putting the device in C28x object mode (supports C2xLP source):
OBJMODE Set the OBJMODE bit.
Reset: C28OBJ C28ADDR .c28_amode C28MAP . . ; ; ; ; Enable C28x Object Mode Enable C27x/C28x Address Mode Tell assembler we are in C27x/C28x address mode Enable C28x Mapping Of M0 and M1 blocks
Example
6-66
CLRC AMODE
CLRC AMODE SYNTAX OPTIONS CLRC AMODE Operands Description

AMODE
Clear the AMODE Bit OPCODE

0101 0110 0001 0110
OBJMODE RPT X
CYC 1
Status bit Clear the AMODE status bit in Status Register ST1, enabling C27x/C28x addressing (see Chapter 5).
AMODE
The AMODE bit is cleared.
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Execute the operation VarC = VarA + VarB written in C2xLP
; syntax: SETC AMODE .lp_amode LDP #VarA LACL VarA ADDS VarB SACL VarC CLRC AMODE .c28_amode ; ; ; ; ; ; ; ; Full C2xLP address-compatible mode Tell assembler we are in C2xLP mode Initialize DP (low 64K only) ACC = VarA (ACC high = 0) ACC = ACC + VarB (unsigned) Store result into VarC Return to C28x address mode Tell assembler we are in C28x mode
Example
6-67
CLRC M0M1MAP
CLRC M0M1MAP SYNTAX OPTIONS CLRC M0M1MAP Operands Description

M0M1MAP Status bit
Clear the M0M1MAP Bit OPCODE

0101 0110 0011 1111
OBJMODE RPT X
CYC 5
Clear the M0M1MAP status bit in Status Register ST1, configuring the mapping of the M0 and M1 memory blocks for C27x operation. The memory blocks are mapped as follows:
Program Space M0
Data Space M0
M1
M1
Note: The pipeline is flushed when this instruction is executed. This bit is provided for compatibility for users migrating from C27x. The M0M1MAP bit should always remain set to 1 for users operating in C28x mode and C2xLP source-compatible mode.
Flags and Modes Example
M0M1MAP
The M0M1MAP bit is cleared.
; Set the device mode from reset to C27x object-compatible mode: Reset: CLRC OBJMODE ; Enable C27x Object Mode CLRC AMODE ; Enable C27x/C28x Address Mode .c28_amode ; Tell assembler we are in C27x/C28x addr mode CLRC M0M1MAP ; Enable C27x Mapping Of M0 and M1 blocks . .
6-68
CLRC OBJMODE
CLRC OBJMODE SYNTAX OPTIONS CLRC OBJMODE Operands Description

OBJMODE
Clear the OBJMODE Bit OPCODE

0101 0110 0011 0110
OBJMODE RPT X
CYC 5
Status bit Clear the OBJMODE status bit, enabling the device to execute C27x object code.
OBJMODE
The OBJMODE bit is cleared.
; Set the device mode from reset to C27x object-compatible mode: Reset: CLRC OBJMODE ; Enable C27x Object Mode CLRC AMODE ; Enable C27x/C28x Address Mode .c28_amode ; Tell assembler we are in C27x/C28x addr mode CLRC M0M1MAP ; Enable C27x Mapping Of M0 and M1 blocks . .
Example
6-69
CLRC OVC
CLRC OVC SYNTAX OPTIONS CLRC OVC OPCODE

0101 0110 0101 1100
Clear Overflow Counter OBJMODE RPT 1 CYC 1
Note: This instruction is an alias for the ZAP OVC operation.
Operands Description Flags and Modes Repeat
OVC
Overflow counter bits in Status Register 0 (ST0) Clear the overflow counter (OVC) bits in ST0.
OVC
The 6-bit overflow counter bits (OVC) are cleared.
; Calculate: VarD = sat(VarA + VarB + VarC) CLRC OVC ; Zero overflow counter MOVL ACC,@VarA ; ACC = VarA ADDL ACC,@VarB ; ACC = ACC + VarB ADDL ACC,@VarC ; ACC = ACC + VarC SAT ACC ; Saturate if OVC != 0 MOVL @VarD,ACC ; Store saturated result into VarD
Example
6-70
CLRC XF
CLRC XF SYNTAX OPTIONS CLRC XF Operands Description Flags and Modes Repeat
XF XF
Clear XF Status Bit OPCODE

0101 0110 0001 1011
OBJMODE RPT X
CYC 1
XF status bit and output signal Clear the XF status bit and pull the corresponding output signal low. The XF status bit is cleared.
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Pulse XF signal high if branch not taken:
MOV AL,@VarA SB Dest,NEQ SETC XF CLRC XF . . Dest: . ; ; ; ; Load AL with contents of VarA ACC = VarA Set XF bit and signal high Clear XF bit and signal low
Example
6-71
CLRC Mode
CLRC Mode SYNTAX OPTIONS CLRC CLRC CLRC CLRC CLRC CLRC CLRC CLRC CLRC mode SXM OVM TC C INTM DBGM PAGE0 VMAP OPCODE
0010 1001 CCCC CCCC 0010 1001 0000 0001 0010 1001 0000 0010 0010 1001 0000 0100 0010 1001 0000 1000 0010 1001 0001 0000 0010 1001 0010 0000 0010 1001 0100 0000 0010 1001 1000 0000
Clear Status Bits OBJMODE X X X X X X X X X RPT CYC 1, 2 1 1 1 1 2 2 1 1
Description
Clear the specified status bits. The mode operand is a mask value that relates to the status bits in this way: Status Register ST0 ST0 ST0 ST0 ST1 ST1 ST1 ST1 Flag SXM OVM TC C INTM DBGM PAGE0 VMAP Cycles 1 1 1 1 2 2 1 1
Mode bit 0 1 2 3 4 5 6 7
Note: The assembler accepts any number of flag names in any order.
Flags and SXM Modes OVM

TC C INTM DBGM PAGE0 VMAP
Any of the specified bits can be cleared by the instruction.
Repeat
6-72
CLRC Mode
Example
; Modify flag settings:

SETC CLRC CLRC SETC SETC CLRC INTM,DBGM TC,C,SXM,OVM #0xFF #0xFF C,SXM,TC,OVM DBGM,INTM ; ; ; ; ; ; Set INTM and DBGM bits to 1 Clear TC, C, SXM, OVM bits to 0 Clear all bits to 0 Set all bits to 1 Set TC, C, SXM, OVM bits to 1 Clear INTM and DBGM bits to 0
6-73
CMP AX, loc16
CMP AX, loc16 SYNTAX OPTIONS CMP AX, loc16 Operands

AX loc16
Compare OPCODE
0101 010A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) The content of the specified AX register (AH or AL) is compared with the 16-bit content of the location pointed to by the loc16 addressing mode. The result of (AX- [loc16] ) is evaluated and the status flag bits set accordingly. The AX register and content of the location pointed to by loc16 are left unchanged:
Set Flags On (AX [loc16]);
Description
Flags and Modes
If the result of the operation is negative, then N is set; otherwise it is cleared. The CMP instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0x0001. If the precision were limited to 16 bits, the result would cause an overflow to the positive number 0x7FFF and N would be cleared. However, because the CMP instruction assumes infinite precision, it would set N to indicate that 0x8000 0x0001 actually results in a negative number. The comparison is tested for a zero condition. The zero flag bit is set if the operation ( AX [loc16] ) = 0, otherwise it is cleared. If the subtraction generates a borrow, then C is cleared; otherwise C is set. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Branch if VarA is higher then VarB: MOV AL,@VarA ; Load AL with contents of VarA CMPB AL,@VarB ; Set Flags On (AL VarB) SB Dest,HI ; Branch if VarA higher then VarB
6-74
CMP loc16,#16bit
CMP loc16,#16bitSigned SYNTAX OPTIONS CMP loc16,#16bitSigned OPCODE

Compare OBJMODE RPT X CYC 1
Operands
loc16 #16bitSigned
Addressing mode (see Chapter 5) 16-bit immediate signed constant value Compare the 16-bit contents of the location pointed to by the loc16 addressing mode to the signed 16-bit immediate constant value. To perform the comparison, the result of ([loc16] #16bitSigned ) is evaluated and the status flag bits are set accordingly. The content of loc16 is left unchanged:
Modify flags on ([loc16] 16bitSigned);
Description
Smart Encoding: If loc16 = AL or AH and #16bitSigned is an 8-bit number, then the assembler will encode this instruction as CMPB AX, #8bit, to override this encoding, use the CMPW AX, #16bitSigned instruction alias. Flags and Modes
N
If the result of the operation is negative, then N is set; otherwise it is cleared. The CMP instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0x0001. If the precision were limited to 16 bits, the result would cause an overflow to the positive number 0x7FFF and N would be cleared. However, because the CMP instruction assumes infinite precision, it would set N to indicate that 0x8000 0x0001 actually results in a negative number. The comparison is tested for a zero condition. The zero flag bit is set if the operation ([loc16] 16bitSigned ) = 0, otherwise it is cleared. If the subtraction generates a borrow, then C is cleared; otherwise C is set. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. The examples in this chapter assume that the device is already operating in C28x Mode (OBJMODE = 1, AMODE = 0). To put the device into C28x mode following a reset, you must first set the OBJMODE bit in ST1 by executing the C28OBJ (or SETC OBJMODE) instruction.
Z C
Repeat
Note:
6-75
CMP loc16,#16bit
Example
; Calculate:
; if( VarA > 20 ) ; VarA = 0; CMP @VarA,#20 MOVB @VarA,#0,GT
; Set flags on (VarA 20) ; Zero VarA if greater then
6-76
CMP64 ACC:P
CMP64 ACC:P SYNTAX OPTIONS CMP64 ACC:P Operands Description

ACC:P
Compare 64-bit Value OPCODE

0101 0110 0101 1110
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) The 64-bit content of the combined ACC:P registers is compared against zero and the flags are set appropriately:
if((V = 1) & (ACC(bit 31) = 1)) N = 0; else N = 1; if((V = 1) & (ACC(bit 31) = 0)) N = 1; else N = 0; if(ACC:P = 0x8000 0000 0000 0000) Z = 1; else Z = 0; V = 0; Note: This operation should be used as follows:
CMP64 ACC:P ; Clear V flag perform 64-bit operation CMP64 ACC:P ; Set Z,N flags, V=0 conditionally branch
Flags and Modes
The content of the ACC register is tested to determine if the 64-bit ACC:P value is negative. The CMP64 instruction takes into account the state of the overflow flag (V) to increase precision when determining if ACC is negative. For example, consider the subtraction on ACC of 0x8000 0000 0x0000 0001. This results in an overflow to a positive number (0x7FFF FFFF) and V would be set. Because the CMP64 instruction takes into account the overflow, it would interpret the result as a negative number and not a positive number. If the value is ACC is found to be negative, then N is set; otherwise N is cleared. The zero flag bit is set if the combined 64 bits of ACC:P is zero, otherwise it is cleared. The state of the V flag is used along with bit 31 of the ACC register to determine if the value in the ACC:P register is negative. V is cleared by the operation. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z V
Repeat
6-77
CMP64 ACC:P
Example
; If 64-bit VarA > 64-bit VarB, branch: MOVL P,@VarA+0 ; Load P with low 32 bits of VarA MOVL ACC,@VarA+2 ; Load ACC with high 32 bits of VarA SUBUL P,@VarB+0 ; Sub from P unsigned low 32 bits of VarB CMP64 ACC:P ; Clear V flag SUBBL ACC,@VarB+2 ; Sub from ACC with borrow high 32 bits of VarB CMP64 ACC:P ; Set Z,N flags appropriately for ACC:P SB Dest,GT ; branch if VarA > VarB
6-78
CMPB AX, #8bit
CMPB AX, #8bit SYNTAX OPTIONS CMPB AX, #8bit Operands

AX #8bit

0101 001A CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate constant value Compare the content of the specified AX register (AH or AL) with the zero-extended 8-bit unsigned immediate constant. The result of (AX 0:8bit) is evaluated and the status flag bits are set accordingly. The content of the AX register is left unchanged:
Set Flags On (AX 0:8bit);
Description
Flags and Modes
If the result of the operation is negative, then N is set; otherwise it is cleared. The CMPB instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0x0001. If the precision were limited to 16 bits, the result would cause an overflow to the positive number 0x7FFF and N would be cleared. However, because the CMPB instruction assumes infinite precision, it would set N to indicate that 0x8000 0x0001 actually results in a negative number. The comparison is tested for a zero condition. The zero flag bit is set if the operation (AX [0:8bit]) = 0, otherwise it is cleared. If the subtraction generates a borrow, then C is cleared; otherwise C is set. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Check if VarA is within range 0x80 <= VarA <= 0xF0: MOV AL,@VarA ; Load AL with contents of VarA CMPB AL,#0xF0 ; Set Flags On (AL 0x00F0) SB OutOfRange,GT ; Branch if VarA greater then 0x00FF CMPB AL,#0x80 ; Set Flags On (AL 0x0080) SB OutOfRange,LT ; Branch if VarA less then 0x0080
6-79
CMPL ACC,loc32
CMPL ACC,loc32 SYNTAX OPTIONS CMPL ACC,loc32 Operands

ACC loc32

0000 1111 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Addressing mode (see Chapter 5) The content of the ACC register is compared with the 32-bit location pointed to by the loc32 addressing mode. The status flag bits are set according to the result of (ACC [loc32]). The ACC register and the contents of the location pointed to by loc32 are left unchanged:
Modify flags on (ACC [loc32]);
Description
Flags and Modes
If the result of the operation is negative, then N is set; otherwise it is cleared. The CMPL instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0000 0x0000 0001. If the precision were limited to 32 bits, the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared. However, because the CMPL instruction assumes infinite precision, it would set N to indicate that 0x8000 0000 0x0000 0001 actually results in a negative number. The comparison is tested for a zero condition. The zero flag bit is set if the operation (AX [loc32]) = 0, otherwise it is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Swap the contents of 32-bit VarA and VarB if VarB is higher: MOVL ACC,@VarB ; ACC = VarB MOVL P,@VarA ; P = VarA CMPL ACC,@P ; Set flags on (VarB - VarA) MOVL @VarA,ACC,HI ; VarA = ACC if higher MOVL @P,ACC,HI ; P = ACC if higher MOVL @VarA,P ; VarA = P
6-80
CMPL ACC,P << PM
CMPL ACC,P << PM SYNTAX OPTIONS CMPL ACC,P << PM Operands

ACC P <<PM

1111 1111 0101 1001
OBJMODE RPT X
CYC 1
Accumulator register Product register Product shift mode The content of the ACC register is compared with the content of the P register, shifted by the amount specified by the product shift mode (PM). The status flag bits are set according to the result of (ACC [ P << PM]). The content of the ACC register and the P register are left unchanged:
Modify flags on (ACC [P << PM]);
Description
Flags and Modes
If the result of the operation is negative, then N is set; otherwise it is cleared. The CMPL instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0000 0x0000 0001. If the precision were limited to 32 bits, the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared. However, because the CMPL instruction assumes infinite precision, it would set N to indicate that 0x8000 0000 0x0000 0001 actually results in a negative number. The comparison is tested for a zero condition. The zero flag bit is set if the operation (AX [P<<PM]) = 0, otherwise, it is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C PM
Repeat
Example
; Compare the following (VarA VarB >> 4): MOVL ACC,@VarA ; ACC = VarA SPM 4 ; Set the product shift mode to >> 4 MOVL P,@VarB ; P = VarB CMPL ACC,P << PM ; Compare (VarA VarB >> 4)
6-81
CMPR 0/1/2/3
CMPR 0/1/2/3 SYNTAX OPTIONS CMPR 0 CMPR 1 CMPR 2 CMPR 3 Operands Description None OPCODE
0101 0110 0001 1101 0101 0110 0001 1001 0101 0110 0001 1000 0101 0110 0001 1100
Compare Auxiliary Registers OBJMODE RPT 1 1 1 1 CYC 1 1 1 1
Compare AR0 to the 16-bit auxiliary register pointed to by ARP. The comparison type is determined by the instruction.
CMPR CMPR CMPR CMPR 0: 1: 2: 3: if(AR0 if(AR0 if(AR0 if(AR0 = AR[ARP]) TC = 1, else TC = 0 > AR[ARP]) TC = 1, else TC = 0 < AR[ARP]) TC = 1, else TC = 0 != AR[ARP]) TC = 1, else TC = 0
Flags and Modes
ARP
The 3-bit ARP points to the current valid Auxiliary Register, XAR0 to XAR7. This pointer determines which Auxiliary register is compared to AR0. If the test is true, TC is set, else TC is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
TC
Repeat
Example
TableA: .word 0x1111 .word 0x2222 FuncA: MOVL XAR1,#VarA MOVZ AR0,*XAR1++ MOVZ AR1,*XAR1 CMPR 0 B Equal,TC CMPR 2 B Less,TC . .
; Initialize XAR1 Pointer ; Load AR0 with 0x1111, clear AR0H, ; ARP = 1 ; Load AR1 with 0x2222, clear AR1H ; AR0 = AR1? No, clear TC ; Dont branch ; AR1 > AR2? Yes, set TC ; Branch to Less
6-82
CSB ACC
CSB ACC SYNTAX OPTIONS CSB ACC Operands Description

ACC
Count Sign Bits OPCODE

0101 0110 0011 0101
OBJMODE RPT 1
CYC 1
Accumulator register Count the sign bits in the ACC register by determining the number of leading 0s or 1s in the ACC register and storing the result, minus one, in the T register:
T = 0, 1 sign bit T = 1, 2 sign bits . . T = 31, 32 sign bits Note: The count sign bit operation is often used in normalization operations and is particularly useful for algorithms such as; calculating Square Root of a number, calculating the inverse of a number, searching for the first 1 bit in a word.
Flags and Modes
N is set if bit 31 of ACC is 1, else N is cleared. Z is set if ACC is 0, else Z is cleared. The TC bit will reflect the state of the sign bit after the operation (TC=1 for negative). This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z TC
Repeat
Example
; Normalize the contents of VarA: MOVL ACC,@VarA ; Load ACC with contents of VarA CSB ACC ; Count sign bits LSLL ACC,T ; Logical shift left ACC by T(4:0) MOVL @VarA,ACC ; Store result into VarA
6-83
DEC loc16
DEC loc16 SYNTAX OPTIONS DEC loc16 Operands Description

loc16
Decrement by 1 OPCODE
0000 1011 LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Subtract 1 from the signed content of the location pointed to by the loc16 addressing mode:
Flags and Modes
N Z C V
After the operation if bit 15 of [loc16] is 1, set N; otherwise, clear N. After the operation if [loc16] is zero, set Z; otherwise, clear Z. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
; VarA = VarA 1; ; Decrement contents of VarA
Repeat
Example
DEC @VarA
6-84
DINT
DINT SYNTAX OPTIONS DINT
Disable Maskable Interrupts (Set INTM Bit) OPCODE

0011 1011 0001 0000
OBJMODE RPT X
CYC 2
Note: This instruction is an alias for the SETC mode operation with the mode field = INTM.
None Disable all maskable CPU interrupts by setting the INTM status bit. DINT has no effect on the unmaskable reset or NMI interrupts.
INTM
The instruction sets this bit to disable interrupts.
; Make the DINT MOVL ADDL MOVL EINT operation VarC = VarA + VarB atomic: ; Disable interrupts (INTM = 1) ACC,@VarA ; ACC = VarA ACC,@VarB ; ACC = ACC + VarB @VarC,ACC ; Store result into VarC ; Enable interrupts (INTM = 0)
Example
6-85
DMAC ACC:P,loc32,*XAR7/++
DMAC ACC:P,loc32,*XAR7/++ SYNTAX OPTIONS DMAC ACC:P,loc32,*XAR7 DMAC ACC:P,loc32,*XAR7++
16-Bit Dual Multiply and Accumulate OPCODE

0101 0110 0100 1011 1100 0111 LLLL LLLL 0101 0110 0100 1011 1000 0111 LLLL LLLL
OBJMODE RPT 1 1 Y Y
CYC N+2 N+2
Operands
ACC:P loc32
Accumulator register (ACC) and product register (P) Addressing mode (see Chapter 5)
Note: The @ACC and @P register addressing modes cannot be used. No illegal instruction trap will be generated if used (assembler will flag an error).
*XAR7 /++
Indirect program-memory addressing using auxiliary register XAR7, can access full 4M x 16 program space range (0x000000 to 0x3FFFFF) Dual 16-bit x 16-bit signed multiply and accumulate. The first multiplication takes place between the upper words of the 32-bit locations pointed to by the loc32 and *XAR7/++ addressing modes and second multiplication takes place with the lower words.
16bits loc32 XT VarA_1 VarA_2 VarA_1 VarA_2 Temp VarB_1 VarB_2 XAR7 16bits VarB_1 VarB_2
Description
VarA_1 * VarB_1 << PM ACC
VarA_2 * VarB_2 << PM P
After the operation the ACC contains the result of multiplying and adding the upper word of the addressed 32-bit operands. The P register contains the result of multiplying and adding the lower word of the addressed 32-bit operands.
XT Temp ACC P = = = = [loc32]; Prog[*XAR7 or *XAR7++]; ACC + (XT.MSW * Temp.MSW) << PM; P + (XT.LSW * Temp.LSW) << PM;
Z, N, V, C flags and OVC counter are affected by the operation on ACC only. The PM shift affects both the ACC and P operations.
6-86
On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *XAR7/++ addressing mode can be used to access data space variables that fall within the program space address range. With some addressing mode combinations, you can get conflicting references. In such cases, the C28x will give the loc16/loc32 field priority on changes to XAR7. For example:
DMAC ACC:P,*XAR7,*XAR7++ DMAC ACC:P,*XAR7++,*XAR7 DMAC ACC:P,*XAR7,*XAR7++ ; XAR7 given priority ; *XAR7++ given priority ; *XAR7++ given priority
Flags and Modes
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry of the ACC register, C is set; otherwise C is cleared. If an overflow of the ACC register occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow of the ACC register, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow of the ACC register, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. Note that OVM only affects the ACC operation. The value in the PM bits sets the shift mode for the output operation from the product register. The PM mode affects both the ACC and P register accumulates. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result in the ACC. The V flag will be set if an intermediate overflow occurs in the ACC.
N C
OVC
OVM
PM
Repeat
6-87
Example
; ; ; ; ; ; ; ;
Calculate sum of product using dual 16-bit multiply: int16 X[N] ; Data information int16 C[N] ; Coefficient information (located in low 4M) ; Data and Coeff must be aligned to even address ; N must be an even number sum = 0; for(i=0; i < N; i++) sum = sum + (X[i] * C[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #(N/2)1 ; Repeat next instruction N/2 times ||DMAC P,*XAR2++,*XAR7++ ; ACC = ACC + (X[i+1] * C[i+1]) >> 5 ; P = P + (X[i] * C[i]) >> 5 i++ ADDL ACC,@P ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-88
DMOV loc16
DMOV loc16 SYNTAX OPTIONS DMOV loc16 Operands

loc16
Data Move Contents of 16-bit Location OPCODE

1010 0101 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Addressing mode (see Chapter 5)

Note: For this operation, registeraddressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T. An illegal instruction trap will be generated.
Description
Copy the contents pointed to by loc16 into the next highest address:
[loc16 + 1] = [loc16];
None
This instruction is repeatable. If the operation is follows a RPT instruction, then it will be executed N+1 times.
; Calculate using 16-bit multiply: ; int16 X[3]; ; int16 C[3]; ; Y = (X[0]*C[0] >> 2) + (X[1]*C[1] >> 2) + (X[2]*C[2] >> 2); ; X[2] = X[1]; ; X[1] = X[0]; SPM 2 ; Set product shift to >> 2 MOVP T,@X+2 ; T = X[2] MPYS P,T,@C+2 ; P = T*C[2], ACC = 0 MOVA T,@X+1 ; T = X[1], ACC = X[2]*C[2] >> 2 MPY P,T,@C+1 ; P = T*C[1] MOVA T,@X+0 ; T = X[0], ACC = ACC + X[1]*C[1] >> 2 MPY P,T,@C+0 ; P = T*C[0] ADDL ACC,P << PM ; ACC = ACC + X[0]*C[0] >> 2 DMOV @X+1 ; X[2] = X[1] DMOV @X+0 ; X[1] = X[0] MOVL @Y,ACC ; Store result into Y
Example
6-89
EALLOW
EALLOW SYNTAX OPTIONS EALLOW Operands Description None
Enable Write Access to Protected Space OPCODE

0111 0110 0010 0010
OBJMODE RPT X
CYC 4
Enable access to emulation space and other protected registers. This instruction sets the EALLOW bit in status register ST1. When this bit is set, the C28x CPU allows write access to the memory-mapped registers as well as other protected registers. See the data sheet for your particular device to determine which registers the EALLOW bit protects. To again protect against writes to the registers, use the EDIS instruction. EALLOW only controls write access; reads are allowed even if EALLOW has not been executed. On an interrupt or trap, the current state of the EALLOW bit is saved off onto the stack within ST1 and the EALLOW bit is autocratically cleared. Therefore, at the start of an interrupt service routine access to the protected registers is disabled. The IRET instruction will restore the current state of the EALLOW bit saved on the stack. The EALLOW bit is overridden via the JTAG port, allowing full control of register accesses during debug from Code Composer Studio.
EALLOW The EALLOW flag is set.
; Enable access to RegA EALLOW AND @RegA,#0x4000 MOV @RegB,#0 EDIS and RegB which are EALLOW protected: ; Enable access to selected registers ; RegA = RegA AND 0x0400 ; RegB = 0 ; Disable access to selected registers
Example
6-90
EDIS
EDIS SYNTAX OPTIONS EDIS Operands Description None
Disable Write Access to Protected Registers OPCODE

0111 0110 0001 1010
OBJMODE RPT X
CYC 4
Disable access to emulation space and other protected registers. This instruction clears the EALLOW bit in status register ST1. When this bit is clear, the C28x CPU does not allow write access to the memorymapped emulation registers and other protected registers. See the data sheet for your particular device to determine which registers the EALLOW bit protects. To allow write access to the registers, use the EALLOW instruction.
EALLOW The EALLOW flag is cleared.
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Enable access to RegA and RegB which are EALLOW protected:
EALLOW NOP ; ; ; ; Enable access to selected registers Wait 2 cycles for enable to take effect. The number of cycles is device and/or register dependant.
Example
NOP AND @RegA,#0x4000 MOV @RegB,#0 EDIS
; RegA = RegA AND 0x0400 ; RegB = 0 ; Disable access to selected registers
6-91
EINT
EINT SYNTAX OPTIONS EINT

Note:
Enable Maskable Interrupts (Clear INTM Bit) OPCODE

0010 1001 0001 0000
OBJMODE RPT X
CYC 2
This instruction is an alias for the CLRC mode operation with the mode field = INTM.
Operands Description Flags and Modes Repeat

INTM
None Enable interrupts by clearing the INTM status bit. This bit is cleared by the instruction to enable interrupts.
; Make the DINT MOVL ADDL MOVL EINT operation VarC = VarA + VarB atomic: ; Disable interrupts (INTM = 1) ACC,@VarA ; ACC = VarA ACC,@VarB ; ACC = ACC + VarB @VarC,ACC ; Store result into VarC ; Enable interrupts (INTM = 0)
Example
6-92
ESTOP0
ESTOP0 SYNTAX OPTIONS ESTOP0 Operands Description None Emulation Stop 0 OPCODE
0111 0110 0010 0101
Emulation Stop 0 OBJMODE RPT X CYC 1
This instruction is available for emulation purposes. It is used to create a software breakpoint. When an emulator is connected to the C28x and emulation is enabled, this instruction causes the C28x to halt, regardless of the state of the DBGM bit in status register ST1. In addition, ESTOP0 does not increment the PC. When an emulator is not connected or when a debug program has disabled emulation, the ESTOP0 instruction is treated the same way as a NOP instruction. It simply advances the PC to the next instruction. Flags and Modes Repeat None
6-93
ESTOP1
ESTOP1 SYNTAX OPTIONS ESTOP1 Operands Description None Emulation Stop 1 OPCODE
0111 0110 0010 0100
Emulation Stop 1 OBJMODE RPT X CYC 1
This instruction is available for emulation purposes. It is used to create an embedded software breakpoint. When an emulator is connected to the C28x and emulation is enabled, this instruction causes the C28x to halt, regardless of the state of the DBGM bit in status register ST1. Before halting the processor, ESTOP1 increments the PC so that it points to the instruction following the ESTOP1. When an emulator is not connected or when a debug program has disabled emulation, the ESTOP0 instruction is treated the same way as a NOP instruction. It simply advances the PC to the next instruction. Flags and Modes Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. None
6-94
FFC XAR7,22bit
FFC XAR7,22bit SYNTAX OPTIONS FFC XAR7,22bit OPCODE

0000 0000 11CC CCCC CCCC CCCC CCCC CCCC
Fast Function Call OBJMODE RPT X CYC 4
Operands
XAR7 22bit
Auxiliary register XAR7 22-bit program-address (0x00 0000 to 0x3F FFFF range) Fast function call. The return PC value is stored into the XAR7 register and the 22-bit immediate destination address is loaded into the PC:
XAR7(21:0) = PC + 2; XAR7(31:22) = 0; PC = 22 bit;
Description
None
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Fast function call of FuncA:
FFC . . FuncA: . . LB XAR7,FuncA ; Call FuncA, return address in XAR7
Example
; Function A:
*XAR7
; Return: branch to address in XAR7
6-95
FLIP AX
FLIP AX SYNTAX OPTIONS FLIP AX Operands Description

AX
Flip Order of Bits in AX Register OPCODE

0101 0110 0111 000A
OBJMODE 1
RPT
CYC 1
Accumulator high (AH) or accumulator low (AL) register Bit reverse the contents of the specified AX register (AH or AL):
temp = AX(bit AX(bit . . AX(bit AX(bit AX; 0) = temp(bit 15); 1) = temp(bit 14);
14) = temp(bit 1); 15) = temp(bit 0);
Flags and Modes
After the operation, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. After the operation, if AX is 0, then the Z bit is set, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Flip the contents of 32-bit variable VarA: MOV AH,@VarA+0 ; Load AH with low 16 bits of VarA MOV AL,@VarA+1 ; Load AL with high 16 bits of VarA FLIP AL ; Flip contents of AL FLIP AH ; Flip contents of AH MOVL @VarA,ACC ; Store 32-bit result in VarA
6-96
IACK #16bit
IACK #16bit SYNTAX OPTIONS IACK #16bit Operands Description

#16bit
Interrupt Acknowledge OPCODE

OBJMODE RPT X
CYC 1
16-bit constant immediate value (0x0000 to 0xFFFF range) Acknowledge an interrupt by outputting the specified 16-bit constant on the low 16 bits of the data bus. Certain peripherals will provide the capability to capture this value to provide low-cost trace. See the data sheet for details for your device.
data_bus(15:0) = 16bit;
None
6-97
IDLE
IDLE SYNTAX OPTIONS IDLE Operands Description None OPCODE

0111 0110 0010 0001
Put Processor in Idle Mode OBJMODE RPT X CYC 5
Put the processor into idle mode and wait for enabled or nonmaskable interrupt. Devices using the 28x CPU may use the IDLE instruction in combination with external logic to achieve different low-power modes. See the device-specific datasheets for more detail. The idle instruction causes the following sequence of events: 1) The pipeline is flushed. 2) All outstanding memory cycles are completed. 3) The IDLESTAT bit of status register ST1 is set. 4) Clocks to the CPU are stopped after the entire instruction buffer is full, placing the device in the idle state. In the idle state, CLKOUT (the clock output from the CPU) and all clocks to blocks outside the CPU (including the emulation block) continue to operate as long as CLKIN (the clock input to the CPU) is driven. The PC continues to hold the address of the IDLE instruction; the PC is not incremented before the CPU enters the idle state. 5) The IDLE output CPU signal is activated (driven high). 6) The device waits for an enabled or nonmaskable hardware interrupt. If such an interrupt occurs, the IDLESTAT bit is cleared, the PC is incremented by 1, and the device exits the idle state. If the interrupt is maskable, it must be enabled in the interrupt enable register (IER). However, the device exits the idle state regardless of the value of the interrupt global mask bit (INTM) of status register ST1. After the device exits the idle mode, the CPU must respond to the interrupt request. If the interrupt can be disabled by the INTM bit in status register ST1, the next event depends on INTM: - If (INTM = 0), then the interrupt is enabled, and the CPU executes the corresponding interrupt service routine. On return from the interrupt, execution begins at the instruction following the IDLE instruction.
- If (INTM = 1), then the interrupt is blocked and program execution
continues at the instruction immediately following the IDLE. If the interrupt cannot be disabled by INTM, the CPU executes the corresponding interrupt service routine. On return from the interrupt, execution begins at the instruction following the IDLE.
6-98
IDLE
IDLESTAT
Before entering the idle mode, IDLESTAT is set; after exiting the idle mode IDLESTAT is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
6-99
IMACL P,loc32,*XAR7/++
IMACL P,loc32,*XAR7/++ SYNTAX OPTIONS IMACL P,loc32,*XAR7 IMACL P,loc32,*XAR7++
Signed 32 X 32-Bit Multiply and Accumulate (Lower Half) OPCODE

OBJMODE RPT 1 1 Y Y
CYC N+2 N+2
Operands
P loc32
Product register Addressing mode (see Chapter 5)

Note: The @ACC addressing mode cannot be used when the instruction is repeated. No illegal instruction trap will be generated if used (assembler will flag an error).
*XAR7/++
Indirect program-memory addressing using auxiliary register XAR7; can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) 32-bit x 32-bit signed multiply and accumulate. First, add the unsigned previous product (stored in the P register), ignoring the product shift mode (PM), to the ACC register. Then, multiply the signed 32-bit content of the location pointed to by the loc32 addressing mode by the signed 32-bit content of the program-memory location pointed to by the XAR7 register. The product shift mode (PM) then determines which part of the lower 38 bits of the 64-bit result are stored in the P register. If specified, post-increment the XAR7 register by 1:
ACC = ACC + unsigned P; temp(37:0) = lower_38 bits(signed [loc32] * signed Prog[*XAR7 or XAR7++]); if( PM = +4 shift ) P(31:4) = temp(27:0), P(3:0) = 0; if( PM = +1 shift ) P(31:1) = temp(30:0), P(0) = 0; if( PM = 0 shift ) P(31:0) = temp(31:0); if( PM = 1 shift ) P(31:0) = temp(32:1); if( PM = 2 shift ) P(31:0) = temp(33:2); if( PM = 3 shift ) P(31:0) = temp(34:3); if( PM = 4 shift ) P(31:0) = temp(35:4); if( PM = 5 shift ) P(31:0) = temp(36:5); if( PM = 6 shift ) P(31:0) = temp(37:6);
Description
6-100
IMACL IMACL IMACL P,*XAR7,*XAR7++ P,*XAR7++,*XAR7 P,*XAR7,*XAR7++ ; XAR7 given priority ; *XAR7++ given priority ; *XAR7++ given priority
Flags and Modes
Z N C V OVCU
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is incremented when the addition operation generates an unsigned carry. The OVM mode does not affect the OVCU counter. The value in the PM bits sets the shift mode that determines which portion of the lower 38 bits of the 64-bit results are stored in the P register. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result in the ACC. The V flag will be set if an intermediate overflow occurs in the ACC.
PM
Repeat
6-101
Example
; ; ; ;
Calculate sum of product using 32-bit multiply and retain 64-bit result: int32 X[N]; // Data information int32 C[N]; // Coefficient information (located in // low 4M) ; int64 sum = 0; ; for(i=0; i < N; i++) ; sum = sum + (X[i] * C[i]) >> 5; ; Calculate low 32 bits: MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVCU RPT #(N1) ; Repeat next instruction N times ||IMACL P,*XAR2++,*XAR7++ ; OVCU:ACC = OVCU:ACC + P, ; P = (X[i] * C[i]) << 5, ; i++ ADDUL ACC,@P ; OVCU:ACC = OVCU:ACC + P MOVL @sum+0,ACC ; Store low 32 bits result into sum ; Calculate high 32 bits: MOVU @AL,OVC ; ACC = OVCU (carry count) MOVB AH,#0 MPYB P,T,#0 ; P = 0 MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C RPT #(N1) ; Repeat next instruction N times ||QMACL P,*XAR2++,*XAR7++ ; ACC = ACC + P >> 5, ; P = (X[i] * C[i]) >> 32, ; i++ ADDL ACC,P << PM ; ACC = ACC + P >> 5 MOVL @sum+2,ACC ; Store high 32 bits result into sum
6-102
IMPYAL P,XT,loc32
IMPYAL P,XT,loc32 SYNTAX OPTIONS IMPYAL P,XT,loc32
Signed 32-Bit Multiply (Lower Half) and Add Previous P OPCODE

0101 0110 0100 1100 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
P XT loc32
Product register Multiplicand register Addressing mode (see Chapter 5) Add the unsigned content of the P register, ignoring the product shift mode (PM), to the ACC register. Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode. The product shift mode (PM) then determines which part of the lower 38 bits of the 64-bit result are stored in the P register:
ACC = ACC + unsigned P; temp(37:0) = lower_38 bits(signed XT * signed [loc32]); if( PM = +4 shift ) P(31:4) = temp(27:0), P(3:0) = 0; if( PM = +1 shift ) P(31:1) = temp(30:0), P(0) = 0; if( PM = 0 shift ) P(31:0) = temp(31:0); if( PM = 1 shift ) P(31:0) = temp(32:1); if( PM = 2 shift ) P(31:0) = temp(33:2); if( PM = 3 shift ) P(31:0) = temp(34:3); if( PM = 4 shift ) P(31:0) = temp(35:4); if( PM = 5 shift ) P(31:0) = temp(36:5); if( PM = 6 shift ) P(31:0) = temp(37:6);
Description
Flags and Modes
Z N C V OVCU PM
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is incremented when the addition operation generates an unsigned carry. The OVM mode does not affect the OVCU counter. The value in the PM bits sets the shift mode that determines which portion of the lower 38 bits of the 64-bit results are stored in the P register. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
6-103
IMPYAL P,XT,loc32
Example
; Calculate signed result: ; Y64 = (X0*C0 + X1*C1 + X2*C2) >> 2 SPM 2 ; Set product shift mode to >> 2 ZAPA ; Zero ACC, P, OVCU MOVL XT,@X0 ; XT = X0 IMPYL P,XT,@C0 ; P = low 32 bits of (X0*C0 << 2) MOVL XT,@X1 ; XT = X1 IMPYAL P,XT,@C1 ; OVCU:ACC = OVCU:ACC + P, ; P = low 32 bits of (X1*C1 << 2) MOVL XT,@X2 ; XT = X2 IMPYAL P,XT,@C2 ; OVCU:ACC = OVCU:ACC + P, ; P = low 32 bits of (X2*C2 << 2) ADDUL ACC,@P ; OVCU:ACC = OVCU:ACC + P MOVL @Y64+0,ACC ; Store low 32-bit result into Y64 MOVU @AL,OVC ; ACC = OVCU (carry count) MOVB AH,#0 QMPYL P,XT,@C2 ; P = high 32 bits of (X2*C2) MOVL XT,@X1 ; XT = X1 QMPYAL P,XT,@C1 ; ACC = ACC + P >> 2, ; P = high 32 bits of (X1*C1) MOVL XT,@X0 ; XT = X0 QMPYAL P,XT,@C0 ; ACC = ACC + P >> 2, ; P = high 32 bits of (X0*C0) ADDL ACC,P << PM ; ACC = ACC + P >> 2 MOVL @Y64+2,ACC ; Store high 32-bit result into Y64
6-104
IMPYL ACC,XT,loc32
IMPYL ACC,XT,loc32 SYNTAX OPTIONS IMPYL ACC,XT,loc32
Signed 32 X 32-Bit Multiply (Lower Half) OPCODE

0101 0110 0100 0100 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 2
Operands
ACC XT loc32
Accumulator register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode and store the lower 32 bits of the 64-bit result in the ACC register:
ACC = signed XT * signed [loc32];
Description
Flags and Modes
Z N
After the operation, the Z flag is set if the ACC value is zero, else Z is cleared. After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate result: Y32 = M32*X32 + B32 MOVL XT,@M32 ; XT = M32 IMPYL ACC,XT,@X32 ; ACC = low 32 bits of (M32*X32) ADDL ACC,@B32 ; ACC = ACC + B32 MOVL @Y32,ACC ; Store result into Y32
6-105
IMPYL P,XT,loc32
IMPYL P,XT,loc32 SYNTAX OPTIONS IMPYL P,XT,loc32 Operands

P XT loc32
Signed 32 X 32-Bit Multiply (Lower Half) OPCODE

0101 0110 0000 0101 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode. The product shift mode (PM) then determines which part of the lower 38 bits of the 64-bit result gets stored in the P register as shown in the diagram below:
temp(37:0) = lower_38 bits(signed XT * signed [loc32]); if( PM = +4 shift ) P(31:4) = temp(27:0), P(3:0) = 0; if( PM = +1 shift ) P(31:1) = temp(30:0), P(0) = 0; if( PM = 0 shift ) P(31:0) = temp(31:0); if( PM = 1 shift ) P(31:0) = temp(32:1); if( PM = 2 shift ) P(31:0) = temp(33:2); if( PM = 3 shift ) P(31:0) = temp(34:3); if( PM = 4 shift ) P(31:0) = temp(35:4); if( PM = 5 shift ) P(31:0) = temp(36:5); if( PM = 6 shift ) P(31:0) = temp(37:6);
Description
PM
The value in the PM bits sets the shift mode that determines which portion of the lower 38 bits of the 64-bit results are stored in the P register. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Calculate signed result: Y64 = M32*X32

MOVL IMPYL QMPYL MOVL MOVL XT,@M32 P,XT,@X32 ACC,XT,@X32 @Y64+0,P @Y64+2,ACC ; ; ; ; XT = P = ACC = Store M32 low 32 bits of (M32*X32) high 32 bits of (M32*X32) result into Y64
6-106
IMPYSL P,XT,loc32
IMPYSL P,XT,loc32 SYNTAX OPTIONS IMPYSL P,XT,loc32
Signed 32-Bit Multiply (Low Half) and Subtract P OPCODE

0101 0110 0100 0011 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
P XT loc32
Product register Multiplicand register Addressing mode (see Chapter 5) Subtract the unsigned content of the P register, ignoring the product shift mode (PM), from the ACC register. Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode. The product shift mode (PM) then determines which part of the lower 38 bits of the 64-bit result are stored in the P register:
ACC = ACC - unsigned P; temp(37:0) = lower_38 bits(signed XT * signed [loc32]); if( PM = +4 shift ) P(31:4) = temp(27:0), P(3:0) = 0; if( PM = +1 shift ) P(31:1) = temp(30:0), P(0) = 0; if( PM = 0 shift ) P(31:0) = temp(31:0); if( PM = 1 shift ) P(31:0) = temp(32:1); if( PM = 2 shift ) P(31:0) = temp(33:2); if( PM = 3 shift ) P(31:0) = temp(34:3); if( PM = 4 shift ) P(31:0) = temp(35:4); if( PM = 5 shift ) P(31:0) = temp(36:5); if( PM = 6 shift ) P(31:0) = temp(37:6);
Description
Flags and Modes
Z N C V OVCU
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is decremented when the subtraction operation generates an unsigned borrow. The OVM mode does not affect the OVCU counter.
6-107
IMPYSL P,XT,loc32
PM
Repeat
Example
; Calculate signed result: ; Y64 = (X0*C0 X1*C1 X2*C2) >> 2 SPM 2 ; Set product shift mode to >> 2 ZAPA ; Zero ACC, P, OVCU MOVL XT,@X0 ; XT = X0 IMPYL P,XT,@C0 ; P = low 32 bits of (X0*C0 << 2) MOVL XT,@X1 ; XT = X1 IMPYSL P,XT,@C1 ; OVCU:ACC = OVCU:ACC P, ; P = low 32 bits of (X1*C1 << 2) MOVL XT,@X2 ; XT = X2 IMPYSL P,XT,@C2 ; OVCU:ACC = OVCU:ACC P, ; P = low 32 bits of (X2*C2 << 2) SUBUL ACC,@P ; OVCU:ACC = OVCU:ACC P MOVL @Y64+0,ACC ; Store low 32-bit result into Y64 MOVU @AL,OVC ; ACC = OVCU (borrow count) MOVB AH,#0 NEG ACC ; Negate borrow QMPYL P,XT,@C2 ; P = high 32 bits of (X2*C2) MOVL XT,@X1 ; XT = X1 QMPYSL P,XT,@C1 ; ACC = ACC P >> 2,| ; P = high 32 bits of (X1*C1) MOVL XT,@X0 ; XT = X0 QMPYSL P,XT,@C0 ; ACC = ACC P >> 2, ; P = high 32 bits of (X0*C0) SUBL ACC,P << PM ; ACC = ACC P >> 2 MOVL @Y64+2,ACC ; Store high 32-bit result into Y64
6-108
IMPYXUL P,XT,loc32
IMPYXUL P,XT,loc32 SYNTAX OPTIONS IMPYXUL P,XT,loc32 Operands

P XT loc32
Signed 32 X Unsigned 32-Bit Multiply (Lower Half) OPCODE

0101 0110 0110 0101 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the loc32 addressing mode. The product shift mode (PM) then determines which part of the lower 38 bits of the 64-bit result are stored in the P register:
temp(37:0) = lower_38 bits(signed XT * unsigned [loc32]); if( PM = +4 shift ) P(31:4) = temp(27:0), P(3:0) = 0; if( PM = +1 shift ) P(31:1) = temp(30:0), P(0) = 0; if( PM = 0 shift ) P(31:0) = temp(31:0); if( PM = 1 shift ) P(31:0) = temp(32:1); if( PM = 2 shift ) P(31:0) = temp(33:2); if( PM = 3 shift ) P(31:0) = temp(34:3); if( PM = 4 shift ) P(31:0) = temp(35:4); if( PM = 5 shift ) P(31:0) = temp(36:5); if( PM = 6 shift ) P(31:0) = temp(37:6);
Description
PM
6-109
IMPYXUL P,XT,loc32
Example
; Calculate result: Y64 = M64*X64 + B64 ; Y64 = Y1:Y0, M64 = M1:M0, X64 = X1:X0, B64 MOVL XT,@X0 ; XT = X0 IMPYL P,XT,@M0 ; P = low 32 bits of MOVL ACC,@B0 ; ACC = B0 ADDUL ACC,@P ; ACC = ACC + P MOVL @Y0,ACC ; Store result into Y0 QMPYUL P,XT,@M0 ; P = high 32 bits of MOVL XT,@X1 ; XT = X1 MOVL ACC,@P ; ACC = P IMPYXUL P,XT,@M0 ; P = low 32 bits of MOVL XT,@M1 ; XT = M1 ADDCL ACC,@P ; ACC = ACC + P + carry IMPYXUL P,XT,@X0 ; P = low 32 bits of ADDUL ACC,@P ; ACC = ACC + P ADDUL ACC,@B1 ; ACC = ACC + B1 MOVL @Y1,P ; Store result into Y1
= B1:B0 (uns M0 * uns X0)
(uns M0 * uns X0)
(uns M0 * sign X1)
(sign M1 * uns X0)
6-110
IN loc16,*(PA)
IN loc16,*(PA) SYNTAX OPTIONS IN loc16,*(PA) Operands

loc16 *(PA)
Input Data From Port OPCODE

OBJMODE RPT 1 Y
CYC N+2
Addressing mode (see Chapter 5) Immediate I/O space memory address Load the location pointed to by the loc16 addressing mode with the content of the specified I/O location pointed to by *(PA):
[loc16] = IOspace[PA];
Description
I/O Space is limited to 64K range (0x0000 to 0xFFFF). On the external interface (XINTF), the I/O strobe signal (XIS), if available on your particular device, is toggled during the operation. The I/O address appears on the lower 16 XINTF address lines (XA[15:0]) and the upper address lines are zeroed. The data is read on the lower 16 data lines (XD[15:0]).
Note: I/O space may not be implemented on all C28x devices. See the data sheet for your particular device for details.
Flags and Modes
N Z
If (loc16 = @AX), then after the move AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then after the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0, otherwise it is cleared. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the (PA) I/O space address is post-incremented by 1 during each repetition.
Repeat
Example
; IORegA address = 0x0300; ; IOREgB address = 0x0301; ; IOREgC address = 0x0302; ; IORegA = 0x0000; ; IORegB = 0x0400; ; IORegC = VarA; ; if( IORegC = 0x2000 ) ; IORegC = 0x0000; IORegA .set 0x0300 IORegB .set 0x0301 IORegC .set 0x0302 MOV @AL,#0 UOUT *(IORegA),@AL MOV @AL,#0x0400 UOUT *(IORegB),@AL OUT *(IORegC),@VarA IN @AL,*(IORegC) CMP @AL,#0x2000 SB $10,NEQ
; ; ; ; ; ; ; ; ; ; ;
Define IORegA address Define IORegB address Define IORegC address AL = 0 IOspace[IORegA] = AL AL = 0x0400 IOspace[IORegB] = AL IOspace[IORegC] = VarA AL = IOspace[IORegC] Set flags on (AL 0x2000) Branch if not equal
6-111
IN loc16,*(PA)
MOV UOUT $10:
@AL,#0 *(IORegC),@AL
; AL = 0 ; IOspace[IORegC] = AL
6-112
INC loc16
INC loc16 SYNTAX OPTIONS INC loc16 Operands Description

loc16
Increment by 1 OPCODE
0000 1010 LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Add 1 to the signed content of the location pointed to by the loc16 addressing mode:
[loc16] = [loc16] + 1;
Flags and Modes
After the operation if bit 15 of [loc16] 1, set N; otherwise, clear N. After the operation if [loc16] is zero, set Z; otherwise, clear Z. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C V
Repeat
Example
; VarA = VarA + 1; INC @VarA
; Increment contents of VarA
6-113
INTR
INTR SYNTAX OPTIONS INTR INTx INTR DLOGINT INTR RTOSINT INTR NMI INTR EMUINT Operands
INTx DLOGINT RTOSINT NMI EMUINT
Emulate Hardware Interrupt OPCODE

0000 0000 0001 CCCC 0000 0000 0001 CCCC 0000 0000 0001 CCCC 0111 0110 0001 0110 0111 0110 0001 1100
OBJMODE RPT X X X X X
CYC 8 8 8 8 8
Maskable CPU interrupt vector name, x = 1 to 14 Maskable CPU datalogging interrupt Maskable CPU real-time operating system interrupt Nonmaskable interrupt Maskable emulation interrupt Emulate an interrupt. The INTR instruction transfers program control to the interrupt service routine that corresponds to the vector specified by the instruction. The INTR instruction is not affected by the INTM bit in status register ST1. It is also not affected by enable bits in the interrupt enable register (IER) or the debug interrupt enable register (DBGIER). Once the INTR instruction reaches the decode 2 phase of the pipeline, hardware interrupts cannot be serviced until the INTR instruction is finished executing (until the interrupt service routine begins). Interrupt Vector RESET INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INTx where x = 9 10 11 12 13 14 Interrupt Vector INT9 INT10 INT11 INT12 INT13 INT14
Description
INTx where x = 0 1 2 3 4 5 6 7 8
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INTR
Part of the operation involves saving pairs of 16-bit CPU registers onto the stack pointed to by the SP register. Each pair of registers is saved in a single 32-bit operation. The register forming the low word of the pair is saved first (to an even address); the register forming the high word of the pair is saved next (to the following odd address). For example, the first value saved is the concatenation of the T register and the status register ST0 (T:ST0). ST0 is saved first, then T. This instruction should not be used with vectors 112 when the peripheral interrupt expansion (PIE) block is enabled.
if(not the NMI vector) Clear the corresponding IFR bit; Flush the pipeline; temp = PC + 1; Fetch specified vector; SP = SP + 1; [SP] = T:ST0; SP = SP + 2; [SP] = AH:AL; SP = SP + 2; [SP] = PH:PL; SP = SP + 2; [SP] = AR1:AR0; SP = SP + 2; [SP] = DP:ST1; SP = SP + 2; [SP] = DBGSTAT:IER; SP = SP + 2; [SP] = temp; Clear corresponding IER bit; INTM = 0; // disable INT1INT14, DLOGINT, RTOSINT DBGM = 1; // disable debug events EALLOW = 0; // disable access to emulation registers LOOP = 0; // clear loop flag IDLESTAT = 0; //clear idle flag PC = fetched vector;
Flags and Modes
DBGM INTM EALLOW LOOP IDLESTAT
Debug events are disabled by setting the DBGM bit. Setting the INTM bit disables maskable interrupts. EALLOW is cleared to disable access to protected registers. The loop flag is cleared. The idle flag is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
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IRET
IRET
Interrupt Return
SYNTAX OPTIONS IRET
OPCODE
0111 0110 0000 0010
OBJMODE RPT X
CYC 8
None Return from an interrupt. The IRET instruction restores the PC value and other register values that were automatically saved by an interrupt operation. The order in which the values are restored is opposite to the order in which they were saved. All values are popped from the stack using 32-bit operations. The stack pointer is not forced to align to an even address during the register restore operations:
SP = SP 2; PC = [SP]; SP = SP 2; DBGSTAT:IER = [SP]; SP = SP 2; DP:ST1 = [SP]; SP = SP 2; AR1:AR0 = [SP]; SP = SP PH:PL = SP = SP AH:AL = SP = SP T:ST0 = SP = SP 2; [SP]; 2; [SP]; 2; [SP]; 1;
Note: Interrupts cannot be serviced until the IRET instruction completes execution.
Flags and Modes
SXM OVM TC C Z N V PM OVC INTM
The operation restores the state of all flags and modes of the ST0 register.
The operation restores the state of the specified flags and modes of the ST1 register. The following bits are not affected: LOOP, IDLESTAT, M0M1MAP
6-116
IRET
DBGM PAGEO VMAP SPA EALLOW AMODE OBJMODE XF ARP
Repeat
6-117
IRET
Example
; Full interrupt context Save and Restore: ; Vector table: INTx: .long INTxService ; INTx interrupt vector . . . ; Interrupt context save: INTxService: ; ACC, P, T, ST0, ST1, DP, AR0, ; AR1, IER, DPGSTAT registers saved ; on stack. ; Return PC saved on stack. ; IER bit corresponding to INTx ; is disabled. ; ST1(EALLOW bit = 0). ; ST1(LOOP bit = 0). ; ST1(DBGM bit = 1). ; ST1(INTM bit = 1). PUSH AR1H:AR0H ; Save remaining registers. PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 PUSH XT ; Interrupt user code: . . . ; Interrupt context restore: POP XT ; Restore registers. POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H IRET ; Return from interrupt.
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LB *XAR7
LB *XAR7 SYNTAX OPTIONS LB *XAR7 Operands

*XAR7
Long Indirect Branch OPCODE

0111 0110 0010 0000
OBJMODE RPT X
CYC 4
indirect program-memory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Long branch indirect. Load the PC with the lower 22 bits of the XAR7 register: PC = XAR7(21:0); None
Description
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; Branch to subroutines in SwitchTable selected by Switch value:
SwitchTable: .long Switch0 .long Switch1 . . MOVL XAR2,#SwitchTable MOVZ AR0,@Switch MOVL XAR7,*+XAR2[AR0] LB *XAR7 SwitchReturn: . . Switch0: . . LB Switch1: . . LB ; Switch address table: ; Switch0 address ; Switch1 address
Example
; ; ; ;
XAR2 = pointer to SwitchTable AR0 = Switch index XAR7 = SwitchTable[Switch] Indirect branch using XAR7
; Function A:
SwitchReturn
; Return: long branch ; Function B:
SwitchReturn
; Return: long branch
6-119
LB 22bit
LB 22bit SYNTAX OPTIONS LB 22bit Operands Description

22bit
Long Branch OPCODE

OBJMODE RPT X
CYC 4
22-bit program-address (0x000000 to 0x3FFFFF range) Long branch. Load the PC with the selected 22-bit program address: PC = 22bit; None
; Branch to subroutines in SwitchTable selected by Switch ; value: SwitchTable: ; Switch address table: .long Switch0 ; Switch0 address .long Switch1 ; Switch1 address . . MOVL XAR2,#SwitchTable MOVZ AR0,@Switch MOVL XAR7,*+XAR2[AR0] LB *XAR7 SwitchReturn: . . Switch0: . . LB Switch1: . . LB ; ; ; ; XAR2 = pointer to SwitchTable AR0 = Switch index XAR7 = SwitchTable[Switch] Indirect branch using XAR7
Example
; Function A:
SwitchReturn
; Return: long branch ; Function B:
SwitchReturn
; Return: long branch
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LC *XAR7
LC *XAR7 SYNTAX OPTIONS LC *XAR7 Operands

*XAR7
Long Indirect Call OPCODE

0111 0110 0000 0100
OBJMODE RPT X
CYC 4
indirect program-memory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Indirect long call. The return PC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations. Next, the destination address stored in the XAR7 register is loaded into the PC:
temp(21:0) = PC + 1; [SP] = temp(15:0); SP = SP + 1; [SP] = temp(21:16); SP = SP + 1; PC = XAR7(21:0); Note: For more efficient function calls when operating with OBJMODE = 1, use the LCR and LRETR instructions instead of the LC and LRET instructions.
Description
None
; Call to subroutines in SwitchTable selected by Switch value: SwitchTable: ; Switch address table: .long Switch0 ; Switch0 address .long Switch1 ; Switch1 address . . MOVL XAR2,#SwitchTable ; XAR2 = pointer to SwitchTable MOVZ AR0,@Switch ; AR0 = Switch index MOVL XAR7,*+XAR2[AR0] ; XAR7 = SwitchTable[Switch] LC *XAR7 ; Indirect call using XAR7 . . Switch0: ; Subroutine 0: . . LRET ; Return Switch1: . . LRET ; Subroutine 1:
Example
; Return
6-121
LC 22bit
LC 22bit SYNTAX OPTIONS LC 22bit OPCODE

Long Call OBJMODE RPT X CYC 4
22bit
22-bit program-address (0x00 0000 to 0x3F FFFF range) Long function call. The return PC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations. Next, the immediate 22-bit destination address is loaded onto the PC:
temp(21:0) = PC + 2; [SP] = temp(15:0); SP = SP + 1; [SP] = temp(21:16) SP = SP + 1; PC = 22bit; Note: For more efficient function calls when operating with OBJMODE = 1, use the LCR and LRETR instructions instead of the LC and LRET instructions.
None
; Standard function call of FuncA: LC FuncA ; Call FuncA, return address on stack . . FuncA: . . LRET ; Function A:
Example
; Return from address on stack
6-122
LCR #22bit
LCR #22bit SYNTAX OPTIONS LCR #22bit OPCODE

0111 0110 01CC CCCC CCCC CCCC CCCC CCCC 22bit
Long Call Using RPC OBJMODE RPT 1 CYC 4
22-bit program-address (0x00 0000 to 0x3F FFFF range) Long call using return PC pointer (RPC). The current RPC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations. Next, the RPC register is loaded with the return address. Next, the 22-bit immediate destination address is loaded into the PC:
[SP] SP = [SP] SP = RPC PC = RPC(15:0); SP + 1; = RPC(21:16); SP + 1; = PC + 2; = 22bit;
Note: The LCR and LRETR operations, enable 4 cycle call and 4 cycle return. The standard LC and LRET operations only enable a 4 cycle call and 8 cycle return. The LCR and LRETR operations can be nested and can freely replace the LC and LRET operations. This is the case on interrupts also. Only on a task switch operation, does the RPC need to be manually saved and restored.
None
This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. ; RPC call of FuncA:
LCR . . FuncA: . . LRETR FuncA ; Call FuncA, return address in RPC
Example
; Function A:
; RPC return
6-123
LCR *XARn
LCR *XARn SYNTAX OPTIONS LCR *XARn Operands

*XARn
Long Indirect Call Using RPC OPCODE

0011 1110 0110 0RRR
OBJMODE RPT 1
CYC 4
indirect program-memory addressing using auxiliary register XAR0 to XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Long indirect call using return PC pointer (RPC). The current RPC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations. Next, the RPC register is loaded with the return address. Next, the destination address stored in the XARn register is loaded into the PC:
[SP] SP = [SP] SP = RPC PC = RPC(15:0); SP + 1; = RPC(21:16); SP + 1; = PC + 1; = XARn(21:0);
Description
Note: The LCR and LRETR operations, enable 4 cycle call and 4 cycle return. The standard LC and LRET operations only enable a 4 cycle call and 8 cycle return. The LCR and LRETR operations can be nested and can freely replace the LC and LRET operations. This is the case on interrupts also. Only on a task switch operation, does the RPC need to be manually saved and restored.
Flags and Modes Repeat Example
None This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
; Call to subroutines in SwitchTable selected by Switch value: SwitchTable: ; Switch address table: .long Switch0 ; Switch0 address .long Switch1 ; Switch1 address . MOVL XAR2,#SwitchTable ; XAR2 = pointer to SwitchTable MOVZ AR0,@Switch ; AR0 = Switch index MOVL XAR6,*+XAR2[AR0] ; XAR6 = SwitchTable[Switch] LCR *XAR6 ; Indirect RPC call using XAR6 . Switch0: ; Subroutine 0: . . LRETR ; RPC Return Switch1: ; Subroutine 1: . LRETR ; RPC Return
6-124
LOOPNZ loc16,#16bit
LOOPNZ loc16,#16bit
Loop While Not Zero
SYNTAX OPTIONS LOOPNZ loc16,#16bit
OPCODE
OBJMODE RPT X
CYC 5N+5
Operands
loc16 #16bit
Addressing mode (see Chapter 5) 16-bit immediate value (0x0000 to 0xFFFF range) Loop while not zero.
while([loc16] & 16bit != 0);
Description
The LOOPNZ instruction uses a bitwise AND operation to compare the value referenced by the loc16 addressing mode and the 16-bit mask value. The instruction performs this comparison repeatedly for as long as the result of the operation is not 0. The process can be described as follows: 1) Set the LOOP bit in status register ST1. 2) Generate the address for the value referenced by the loc16 addressing mode. 3) If loc16 is an indirect-addressing operand, perform any specialized modification to the SP or the specified auxiliary register and/or the ARPn pointer. 4) Compare the addressed value with the mask value by using a bitwise AND operation. 5) If the result is 0, clear the LOOP bit and increment the PC by 2. If the result is not 0, then return to step 1. The loop created by steps 1 through 5 can be interrupted by hardware interrupts. When an interrupt occurs, if the LOOPNZ instruction is still active, the return address saved on the stack points to the LOOPNZ instruction. Therefore, upon return from the interrupt the LOOPNZ instruction is fetched again. While the result of the AND operation is not 0, the LOOPNZ instruction begins again every five cycles in the decode 2 phase of the pipeline. Thus the memory location or register is read once every five cycles. If you use an indirect addressing mode for the loc16 operand, you can specify an increment or decrement for the pointer (SP or auxiliary register). If you do, the pointer is modified each time in the decode 2 phase of the pipeline. This means that the mask value is compared with a new data-memory value each time.
6-125
LOOPNZ loc16,#16bit
The LOOPNZ instruction does not flush prefetched instructions from the pipeline. However, when an interrupt occurs, prefetched instructions are flushed. When any interrupt occurs, the current state of the LOOP bit is saved as ST1 is saved on the stack. The LOOP bit in ST1 is then cleared by the interrupt. The LOOP bit is a passive status bit. The LOOPNZ instruction changes LOOP, but LOOP does not affect the instruction. You can abort the LOOPNZ instruction within an interrupt service routine. Test the LOOP bit saved on the stack. If it is set, then increment (by 2) the return address on the stack. Upon return from the interrupt, this incremented address is loaded into the PC and the instruction following the LOOPNZ is executed. Flags and Modes
N
If bit 15 of the result of the AND operation is 1, set N; otherwise, clear N. If the result of the AND operation is 0, set Z; otherwise, clear Z. LOOP is repeatedly set while the result of the AND operation is not 0. LOOP is cleared when the result is 0. If an interrupt occurs before the LOOPNZ instruction enters the decode 2 phase of the pipeline, the instruction is flushed from the pipeline and, thus, does not affect the LOOP bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z LOOP
Repeat
Example
; Wait until bit 3 in RegA is cleared before writing to RegB: LOOPNZ @RegA,#0x0004 ; Loop while (RegA AND 0x0004 != 0) MOV @RegB,#0x8000 ; RegB = 0x8000
6-126
LOOPZ loc16,#16bit
LOOPZ loc16,#16bit
Loop While Zero
SYNTAX OPTIONS LOOPZ loc16,#16bit
OPCODE
OBJMODE RPT X
CYC 5N+5
Operands
loc16 #16bit
Addressing mode (see Chapter 5) 16-bit immediate value (0x0000 to 0xFFFF range) Loop while zero.
while([loc16] & 16bit = 0);
Description
The LOOPZ instruction uses a bitwise AND operation to compare the value referenced by the loc16 addressing mode and the 16-bit mask value. The instruction performs this comparison repeatedly for as long as the result of the operation is 0. The process can be described as follows: 1) Set the LOOP bit in status register ST1. 2) Generate the address for the value referenced by the loc16 addressing mode. 3) If loc16 is an indirect-addressing operand, perform any specialized modification to the SP or the specified auxiliary register and/or the ARPn pointer. 4) Compare the addressed value with the mask value by using a bitwise AND operation. 5) If the result is not 0, clear the LOOP bit and increment the PC by 2. If the result is 0, then return to step 1. The loop created by steps 1 through 5 can be interrupted by hardware interrupts. When an interrupt occurs, if the LOOPZ instruction is still active, the return address saved on the stack points to the LOOPZ instruction. Therefore, upon return from the interrupt the LOOPZ instruction is fetched again. While the result of the AND operation is 0, the LOOPZ instruction begins again every five cycles in the decode 2 phase of the pipeline. Thus the memory location or register is read once every five cycles. If you use an indirect addressing mode for the loc16 operand, you can specify an increment or decrement for the pointer (SP or auxiliary register). If you do, the pointer is modified each time in the decode 2 phase of the pipeline. This means that the mask value is compared with a new data-memory value each time.
6-127
LOOPZ loc16,#16bit
The LOOPZ instruction does not flush prefetched instructions fr4om the pipeline. However, when an interrupt occurs, prefetched instructions are flushed. When any interrupt occurs, the current state of the LOOP bit is saved as ST1 is saved on the stack. The LOOP bit in ST1 is then cleared by the interrupt. The LOOP bit is a passive status bit. The LOOPZ instruction changes LOOP, but LOOP does not affect the instruction. You can abort the LOOPZ instruction within an interrupt service routine. Test the LOOP bit saved on the stack. If it is set, then increment (by 2) the return address on the stack. Upon return from the interrupt, this incremented address is loaded into the PC and the instruction following the LOOPZ is executed. Flags and Modes
N Z LOOP
If bit 15 of the result of the AND operation is 1, set N; otherwise, clear N. If the result of the AND operation is 0, set Z; otherwise, clear Z. LOOP is repeatedly set while the result of the AND operation is 0. LOOP is cleared when the result is not 0. If an interrupt occurs before the LOOPZ instruction enters the decode 2 phase of the pipeline, the instruction is flushed from the pipeline and, thus, does not affect the LOOP bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Wait until bit 3 in RegA is set before writing to RegB:

LOOPZ MOV @RegA,#0x0004 @RegB,#0x8000 ; Loop while (RegA AND 0x0004 = 0) ; RegB = 0x8000
6-128
LPADDR
LPADDR SYNTAX OPTIONS LPADDR OPCODE

0101 0110 0001 1110
Set the AMODE Bit OBJMODE RPT X CYC 1
Note: LPADDR is an alias for the SETC AMODE Operation.
None Set the AMODE status bit, putting the device in C2xLP compatible addressing mode (see Chapter 5).
AMODE The AMODE bit is set.
; Execute the operation VarC = VarA + VarB written in C2xLP syntax: LPADDR ; Full C2xLP address compatible mode .lp_amode ; Tell assembler we are in C2XLP mode LDP #VarA ; Initialize DP (low 64K only) LACL VarA ; ACC = VarA (ACC high = 0) ADDS VarB ; ACC = ACC + VarB (unsigned) SACL VarC ; Store result into VarC C28ADDR ; Return to C28x address mode .c28_amode ; Tell assembler we are in C28x mode
Example
6-129
LRET
LRET SYNTAX OPTIONS LRET Operands Description None OPCODE

0111 0110 0001 0100
Long Return OBJMODE RPT X CYC 8
Long return. The return address is popped, from the software stack into the PC, in two 16-bit operations:
SP = SP 1; temp(31:16) = [SP]; SP = SP 1; temp(15:0) = [SP]; PC = temp(21:0);
Flags and Modes
None
Note: For more efficient function calls when operating with OBJMODE = 1, use the LCR and LRETR instructions in place of the LC and LRET instructions.
Repeat
; Standard function call of FuncA: LC FuncA ; Call FuncA, return address on stack . . FuncA: . . LRET ; Function A:
Example
; Return from address on stack
6-130
LRETE
LRETE SYNTAX OPTIONS LRETE Operands Description None OPCODE
Long Return and Enable Interrupts OBJMODE RPT X CYC 8
0111 0110 0001 0000
Long return and enable interrupts. The return address is popped, from the software stack into the PC, in two 16-bit operations. Next, the global interrupt flag (INTM) is cleared. This enables global maskable interrupts:
SP = SP 1; temp(31:16) = [SP]; SP = SP 1; temp(15:0) = [SP]; PC = temp(21:0); INTM = 0;
INTM
This instruction enables interrupts by clearing the INTM bit.
; Standard function call of FuncA. Disable interrupts on entry and ; enable interrupts on exit: LC FuncA ; Call FuncA, return address on stack . . FuncA: SETC INTM . . LRETE ; Function A: ; Disable interrupts
Example
; Return from address on stack, ; Enable interrupts
6-131
LRETR
LRETR SYNTAX OPTIONS LRETR Operands Description None OPCODE

0000 0000 0000 0110
Long Return Using RPC OBJMODE RPT 1 CYC 4
Long return using return PC pointer (RPC). The return address stored in the RPC register is loaded onto the PC. Next, the RPC register is loaded from the software stack in two 16-bit operations:
PC = RPC; SP = SP 1; temp(31:16) = [SP]; SP = SP 1; temp(15:0) = [SP]; RPC = temp(21:0); Note: The LCR and LRETR operations, enable 4 cycle call and 4 cycle return. The standard LC and LRET operations only enable a 4 cycle call and 8 cycle return. The LCR and LRETR operations can be nested and can freely replace the LC and LRET operations. This is the case on interrupts also. Only on a task switch operation, does the RPC need to be manually saved and restored.
None
; RPC call of FuncA: LCR FuncA . . FuncA: . . LRETR
Example
; Call FuncA, return address in RPC
; Function A:
; RPC return
6-132
LSL ACC,#1..16
LSL ACC,#1..16 SYNTAX OPTIONS LSL ACC,#1..16 Operands

ACC #1..16
Logical Shift Left OPCODE

1111 1111 0011 SHFT
OBJMODE RPT X Y
CYC N+1
Accumulator register Shift value Perform a logical shift left on the content of the ACC register by the amount specified by the shift value. During the shift, the low order bits of the ACC register are zero filled and the last bit shifted out is stored in the carry flag bit:
Last bit out C Left shift (Immediate value) Discard other bits ACC ACC
Description
Flags and Modes
After the shift, if bit 31 of ACC is 1 then the negative flag bit is set; otherwise it is cleared. After the shift, if ACC is 0, then the Z bit is set, otherwise it is cleared. The last bit to be shifted out of ACC is stored in C. This instruction is repeatable. If the operation follows a RPT instruction, then the LSL instruction will be executed N+1 times. The state of the Z, N, and C flags will reflect the final result.
Z C
Repeat
Example
; Logical MOVL LSL MOVL
shift left contents of VarA by 4: ACC,@VarA ; ACC = VarA ACC,#4 ; Logical shift left ACC by 4 @VarA,ACC ; Store result into VarA
6-133
LSL ACC,T
LSL ACC,T SYNTAX OPTIONS LSL ACC,T Operands

ACC T
Logical Shift Left by T(3:0) OPCODE

1111 1111 0101 0000
OBJMODE RPT X
CYC 1
Accumulator register Upper 16 bits of the multiplicand (XT) register Perform a logical shift left on the content of the ACC register by the amount specified by the four least significant bits of the T register, T(3:0) = 015. Higher order bits are ignored. During the shift, the low order bits of the ACC register are zero filled. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC register:
Last bit out or cleared C Left shift (Contents T(3:0) Discard other bits ACC ACC
Description
Flags and Modes
Repeat
Example
; Logical MOVL MOV LSL MOVL
shift left contents of VarA by VarB: ACC,@VarA ; ACC = VarA T,@VarB ; T = VarB (shift value) ACC,T ; Logical shift left ACC by T(3:0) @VarA,ACC ; Store result into VarA
6-134
LSL AX,#1...16
LSL AX,#1...16 SYNTAX OPTIONS LSL AX,#116 Operands

AX #116

1111 1111 100A SHFT
OBJMODE X
RPT
CYC 1
Accumulator high (AH) or accumulator low (AL) register Shift value Perform a logical shift left on the content of the specified AX register (AH or AL) by the amount given shift value field. During the shift, the low order bits of the AX register are zero filled and the last bit to be shifted out is stored in the carry bit flag:
Last bit out C Left shift (Immediate value) Discard other bits AX AX
Description
Flags and Modes
After the shift, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. After the shift, if AX is 0, then the Z bit is set, otherwise it is cleared. The last bit to be shifted out of AH or AL is stored in C. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C
Repeat
Example
; Multiply index register AR0 by 2: MOV AL,@AR0 ; Load AL with contents of AR0 LSL AL,#1 ; Scale result by 1 (*2) MOV @AR0,AL ; Store result back in AR0
6-135
LSL AX,T
LSL AX,T SYNTAX OPTIONS LSL AX,T Operands

AX T
Logical Shift Left by T(3:0) OPCODE

1111 1111 0110 011A
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register Perform a logical shift left on the content of the specified AX register by the amount specified by the four least significant bits of the T register, T(3:0). The contents of higher order bits are ignored. During the shift, the low order bits of the AX register are zero filled. If the T(3:0) register bits specify a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of AX:
Last bit out or cleared C Left shift (Contents of T(3:0) Discard other bits AX
Description
AX
Flags and Modes
Repeat
Example
; Calculate value: VarC = VarA << VarB; MOV T,@VarB ; Load T with contents of VarB MOV AL,@VarA ; Load AL with contents of VarA LSL AL,T ; Scale AL by value in T bits 0 to 3 MOV @VarC,AL ; Store result in VarC
6-136
LSL64 ACC:P,#1..16
LSL64 ACC:P,#1..16 SYNTAX OPTIONS LSL64 ACC:P,#1..16 Operands

ACC:P #1..16

0101 0110 1010 SHFT
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Shift value Logical shift left the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field. During the shift, the low order bits are zero-filled and the last bit shifted out is stored in the carry bit flag:
Last bit out C Left shift (Immediate value) Discard other bits ACC:P ACC:P
Description
Flags andModes
Repeat
Example
; Logical shift left the 64-bit Var64 by 10: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL P,@Var64+0 ; Load P with low 32 bits of Var64 LSL64 ACC:P,#10 ; Logical shift left ACC:P by 10 MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-137
LSL64 ACC:P,T
LSL64 ACC:P,T SYNTAX OPTIONS LSL64 ACC:P,T Operands

ACC:P T
64-Bit Logical Shift Left by T(5:0) OPCODE

0101 0110 0101 0010
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Logical shift left the 64-bit combined value of the ACC:P registers by the amount specified in the six least significant bits of the T register, T(5:0) = 063. Higher order bits are ignored. During the shift, the low order bits are zero-filled. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC:P registers:
Last bit out or cleared C Left shift contents of T (5:0) Discard other bits ACC:P ACC:P
Description
Flags and Modes
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. If (T(5:0) = 0) clear C; otherwise, the last bit shifted out of the combined 64-bit value is loaded into the C bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Logical shift left the 64-bit Var64 by contents of Var16: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL P,@Var64+0 ; Load P with low 32 bits of Var64 MOV T,@Var16 ; Load T with shift value from Var16 LSL64 ACC:P,T ; Logical shift left ACC:P by T(5:0) MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-138
LSLL ACC,T
LSLL ACC,T SYNTAX OPTIONS LSLL ACC,T Operands

ACC T
Logical Shift Left by T (4:0) OPCODE

0101 0110 0011 1011
OBJMODE RPT 1
CYC 1
Accumulator register Upper 16 bits of the multiplicand (XT) register
Upper 16 bits of the multiplicand register (XT) Perform a logical shift left on the content of the ACC register by the amount specified by the five least significant bits of the T register, T(4:0) = 031. Higher order bits are ignored. During the shift, the low order bits of the ACC register are zero filled. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC register:
Last bit out or cleared C Left shift (Contents of T (4:0) Discard other bits ACC ACC
Description
Flags and Z Modes

N
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the zero condition and Z is affected. After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the negative condition and N is affected. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Logical shift left contents of VarA by VarB: MOVL MOV LSLL MOVL ACC,@VarA T,@VarB ACC,T @VarA,ACC ; ; ; ; ACC = VarA T = VarB (shift value) Logical shift left ACC by T(4:0) Store result into VarA
6-139
LSR AX,#1...16
LSR AX,#1...16 SYNTAX OPTIONS LSR AX,#116 Operands

AX #116
Logical Shift Right OPCODE

1111 1111 110A SHFT
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Shift value Perform a logical right shift on the content of the specified AX register by the amount given by the shift value field. During the shift, the high order bits of the AX register are zero filled and the last bit to be shifted out is stored in the carry flag bit:
AX Last bit out C Right shift (Immediate value) Discard other bits
Description
AX
Flags and Modes
After the shift, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. After the shift, if AX is 0, then the Z bit is set, otherwise it is cleared. The last bit to be shifted out of AH or AL is stored in C. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C
Repeat
Example
; Divide index register AR0 by 2: MOV AL,@AR0 ; Load AL with contents of AR0 LSR AL,#1 ; Scale result by 1 (/2) MOV @AR0,AL ; Store result back in AR0
6-140
LSR AX,T
LSR AX,T SYNTAX OPTIONS LSR AX,T Operands

AX
Logical Shift Right by T(3:0) OPCODE

1111 1111 0110 001A
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register
Description
Perform a logical shift right on the content of the specified AX register (AH or AL) as specified by the four least significant bits of the T register, T(3:0). The contents of higher order bits are ignored. During the shift, the high order bits of the AX register are zero filled If the T(3:0) register bits specify a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of AX:
AX Last bit out or cleared C Right shift Contents of T (3:0) Discard other bits AX
Flags and Modes
Repeat
Example
; Calculate un-signed value: VarC = VarA >> VarB; MOV T,@VarB ; Load T with contents of VarB MOV AL,@VarA ; Load AL with contents of VarA LSR AL,T ; Scale AL by value in T bits 0 to 3 MOV @VarC,AL ; Store result in VarC
6-141
LSR64 ACC:P,#1..16
LSR64 ACC:P,#1..16 SYNTAX OPTIONS LSR64 ACC:P,#1..16 Operands

ACC:P #1..16
64-Bit Logical Shift Right OPCODE

0101 0110 1001 SHFT
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Shift value Logical shift right the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field. As the value is shifted, the most significant bits are zero filled and the last bit shifted out is stored in the carry bit flag:
ACC:P Last bit out C Right shift (Immediate value) Discard other bits ACC:P
Description
Flags and Modes
Repeat
Example
; Logical shift right the 64-bit Var64 by 10: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL LSR64 MOVL MOVL P,@Var64+0 ACC:P,#10 @Var64+2,ACC @Var64+0,P ; ; ; ; Load P with low 32 bits of Var64 Logical shift right ACC:P by 10 Store high 32-bit result into Var64 Store low 32-bit result into Var64
6-142
LSR64 ACC:P,T
LSR64 ACC:P,T SYNTAX OPTIONS LSR64 ACC:P,T Operands

ACC:P T
64-Bit Logical Shift Right by T(5:0) OPCODE

0101 0110 0101 1011
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Logical shift right the 64-bit combined value of the ACC:P registers by the amount specified by the six least significant bits of the T register, T(5:0) = 063. Higher order bits are ignored. As the value is shifted, the most significant bits are zero filled. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC:P registers:
ACC:P Last bit out or cleared C Right shift (Contents of T(5:0) Discard other bits ACC:P
Description
Flags and Modes
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. If (T(5:0) = 0) clear C; otherwise, the last bit shifted out of the combined 64-bit value is loaded into the C bit. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Arithmetic shift right the 64-bit Var64 by contents of Var16: MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64 MOVL P,@Var64+0 ; Load P with low 32 bits of Var64 MOV T,@Var16 ; Load T with shift value from Var16 LSR64 ACC:P,T ; Logical shift right ACC:P by T(5:0) MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-143
LSRL ACC,T
LSRL ACC,T SYNTAX OPTIONS LSRL ACC,T Operands

ACC T
Logical Shift Right by T (4:0) OPCODE

0101 0110 0010 0010
OBJMODE RPT 1
CYC 1
Accumulator register Upper 16 bits of the multiplicand (XT) register Perform a logical shift right on the content of the ACC register as specified by the five least significant bits of the T register, T(4:0) = 031. Higher order bits are ignored. During the shift, the high order bits of ACC are zero-filled. If T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit to be shifted out of the ACC register:
ACC Last bit out or cleared C Right shift Contents of T (4:0) Discard other bits ACC
Description
Flags and Modes
Repeat
Example
; Logical MOVL MOV LSRL MOVL
shift right contents of VarA by VarB: ACC,@VarA ; ACC = VarA T,@VarB ; T = VarB (shift value) ACC,T ; Logical shift right ACC by T(4:0) @VarA,ACC ; Store result into VarA
6-144
MAC P,loc16,0:pma
MAC P,loc16,0:pma SYNTAX OPTIONS MAC P,loc16,0:pma Operands

P loc16 0:pma
Multiply and Accumulate OPCODE

OBJMODE RPT X Y
CYC N+2
Product register Addressing mode (see Chapter 5) Immediate program memory address, access low 64K range of program space only (0x000000 to 0x00FFFF) 1) Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. 2) Load the T register with the content of the location pointed to by the loc16 addressing mode. 3) Multiply the signed 16-bit content of the T register by the signed 16-bit content of the addressed program memory location and store the 32-bit result in the P register:
ACC = ACC + P << PM; T = [loc16]; P = signed T * signed Prog[0x00:pma];
Description
The C28x forces the upper 6 bits of the program memory address, specified by the 0:pma addressing mode, to 0x00 when using this form of the MAC instruction. This limits the program memory address to the low 64K of program address space (0x000000 to 0x00FFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the 0:pma addressing mode can be used to access data space variables that fall within its address range. Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed.
OVM
6-145
MAC P,loc16,0:pma
PM
The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. When repeated, the program-memory address is incremented by 1 during each repetition.
Repeat
Example
; Calculate sum of product using 16-bit multiply: ; int16 X[N] ; Data information ; int16 C[N] ; Coefficient information, located in low 64K ; sum = 0; ; for(i=0; i < N; i++) ; sum = sum + (X[i] * C[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #N1 ; Repeat next instruction N times ||MAC P,*XAR2++,0:C ; ACC = ACC + P >> 5, ; P = *XAR2++ * *C++ ADDL ACC,P << PM ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-146
MAC P ,loc16,*XAR7/++
MAC P ,loc16,*XAR7/++ SYNTAX OPTIONS MAC P, loc16, *XAR7 MAC P, loc16, *XAR7++ OPCODE
Multiply and Accumulate OBJMODE RPT 1 1 Y Y CYC N+2 N+2
Operands
P loc16 *XAR7 /++
Product register Addressing mode (see Chapter 5) Indirect program-memory addressing using auxiliary register XAR7, can access full 4M x 16 program space range (0x000000 to 0x3FFFFF) Use the following steps for this instruction: 1) Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. 2) Load the T register with the content of the location pointed to by the loc16 addressing mode. 3) Multiply the signed 16-bit content of the T register by the signed 16-bit content of the program memory location pointed to by the XAR7 register and store the 32-bit result in the P register. If specified, post-increment the XAR7 register by 1:
ACC = ACC + P << PM; T = [loc16]; P = signed T * signed Prog[*XAR7 or *XAR7++];
Description
On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the XAR7/++ addressing mode can be used to access data space variables that fall within the program space address range. With some addressing mode combinations, you can get conflicting references. In such cases, the C28x will give the loc16/loc32 field priority on changes to XAR7. For example:
MAC P,*XAR7,*XAR7++ MAC P,*XAR7++,*XAR7 MAC P,*XAR7,*XAR7++ ; XAR7 given priority ; *XAR7++ given priority ; *XAR7++ given priority
6-147
MAC P ,loc16,*XAR7/++
Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
OVM
PM
Repeat
Example
; Calculate sum of product using 16-bit multiply: ; int16 X[N] ; Data information ; int16 C[N] ; Coefficient information (located in low 4M) ; sum = 0; ; for(i=0; i < N; i++) ; sum = sum + (X[i] * C[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #N1 ; Repeat next instruction N times ||MAC P,*XAR2++,*XAR7++ ; ACC = ACC + P >> 5, ; P = *XAR2++ * *XAR7++ ADDL ACC,P << PM ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-148
MAX AX, loc16
MAX AX, loc16 SYNTAX OPTIONS MAX AX, loc16 OPCODE

0101 0110 0111 001A 0000 0000 LLLL LLLL
Find the Maximum OBJMODE RPT 1 Y CYC N+1
Operands
AX loc16
Accumulator high (AH) or accumulator low (AL) register Addressing modes (see Chapter 5) Compare the signed contents of the specified AX register (AH or AL) with the signed content of the location pointed to by the loc16 addressing mode and load the AX register with the larger of these two values:
if(AX < [loc16]), AX = [loc16]; if(AX >= [loc16]), AX = unchanged;
Description
Flags and Modes
If AX is less than the contents of the addressed location (AX < [loc16]) then the negative flag bit will be set; otherwise, it will be cleared. If AX and the contents of the addressed location are equal (AX = [loc16]) then the zero flag bit will be set; otherwise, it will be cleared. If AX is less than the contents of the addressed location (AX < [loc16]) then the overflow flag bit will be set. This instruction cannot clear the V flag. If the operation is follows a RPT instruction, the instruction will be executed N+1 times. The state of the N, Z, and V flags will reflect the final result.
Repeat
Example
; Saturate VarA as follows: ; if(VarA > 2000) VarA = 2000; ; if(VarA < 2000) VarA = 2000; MOV AL,@VarA ; Load AL with contents of VarA MOV @AH,#2000 ; Load AH with the value 2000 MIN AL,@AH ; if(AL > AH) AL = AH NEG AH ; AH = 2000 MAX AL,@AH ; if(AL < AH) AL = AH MOV @VarA,AL ; Store result into VarA
6-149
MAXCUL P,loc32
MAXCUL P,loc32 SYNTAX OPTIONS MAXCUL P,loc32 Operands

P loc32 Product register
Conditionally Find the Unsigned Maximum OPCODE

0101 0110 0101 0001 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Based on the state of the N and Z flags, conditionally compare the unsigned contents of the P register with the 32-bit, unsigned content of the location pointed to by the loc32 addressing mode and load the P register with the larger of the two numbers:
if( (N=1) & (Z=0) ) P = [loc32]; if( (N=0) & (Z=1) & (P < [loc32]) ) V=1, P = [loc32]; if( (N=0) & (Z=0) ) P = unchanged; Note: The P < [loc32] operation is treated like a 32-bit unsigned compare.
Description
This instruction is typically combined with the MAXL instruction to form a 64-bit maximum function. It is assumed that the N and Z flags will first be set by using a MAXL instruction to compare the upper 32 bits of a 64-bit value. The MAXCUL instruction is then used to conditionally compare the lower 32 bits based on the results of the upper 32-bit comparison. Flags and Modes
N Z
If (N = 1 and z = 0) then load P with [loc32]. If (N = 0 and Z = 1) compare the unsigned content of the P with the unsigned [loc32] and load P with the larger of the two. If (N = 0 and Z = 0) do nothing.
If (N = 0 AND Z = 1 AND P < [loc32] ) then V is set; otherwise, V is unchanged. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
6-150
MAXCUL P,loc32
Example
; Saturate 64-bit Var64 as follows: ; if(Var64 > MaxPos64 ) Var64 = MaxPos64 ; if(Var64 < MaxNeg64 ) Var64 = MaxNeg64 MOVL ACC,@Var64+2 ; Load ACC:P with Var64 MOVL P,@Var64+0 MINL ACC,@MaxPos64+2 ; if(ACC:P > MaxPos64) ACC:P = MaxPos64 MINCUL P,@MaxPos64+0 SB saturate,OV MAXL ACC,@MaxNeg64+2 ; if(ACC:P < MaxNeg64) ACC:P = MaxNeg64 MAXCUL P,@MaxNeg64+0 Saturate: MOVL @Var64+2,ACC ; Store result into Var64 MOVL @Var64,P
6-151
MAXL ACC,loc32
MAXL ACC,loc32 SYNTAX OPTIONS MAXL ACC,loc32 Operands

ACC loc32
Find the 32-bit Maximum
OPCODE
0101 0110 0110 0001 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Compare the content of the ACC register with the location pointed to by the loc32 addressing mode and load the ACC register with the larger of these two values:
if(ACC < [loc32]), ACC = [loc32]; if(ACC >= [loc32]), ACC = unchanged;
Description
Flags and Modes
If ACC is equal to the contents of the addressed location (ACC = [loc32]), set Z; otherwise, clear Z. If ACC is less than the contents of the addressed location, (ACC < [loc32]), set N; otherwise clear N. The MAXL instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0000 0x0000 0001. If the precision were limited to 32 bits, the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared. However, because the MAXL instruction assumes infinite precision, it would set N to indicate that 0x8000 0000 0x0000 0001 actually results in a negative number. If (ACC [loc32]) generates a borrow, clear the C bit; otherwise set C. If ACC is less than the contents of the addressed location (ACC < [loc32]), set V. This instruction cannot clear the V flag. This instruction is repeatable. If the operation follows a RPT instruction, then the MAXL instruction will be executed N+1 times. The state of the Z, N, and C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
C V
Repeat
Example
; Saturate VarA as follows: ; if(VarA > MaxPos) VarA = MaxPos ; if(VarA < MaxNeg) VarA = MaxNeg MOVL ACC,@VarA ; ACC = VarA MINL ACC,@MaxPos ; if(ACC > MaxPos) ACC = MaxPos MAXL ACC,@MaxNeg ; if(ACC < MaxNeg) ACC = MaxNeg MOVL @VarA,ACC ; Store result into VarA
6-152
MIN AX, loc16
MIN AX, loc16 SYNTAX OPTIONS MIN AX, loc16 OPCODE

0101 0110 0111 010A 0000 0000 LLLL LLLL
Find the Minimum
OBJMODE RPT 1 Y
CYC N+1
Operands
AX loc16
Accumulator high (AH) or accumulator low (AL) register Addressing modes (see Chapter 5) Compare the signed content of the specified AX register (AH or AL) with the content of the signed location pointed to by the loc16 addressing mode and load the AX register with the smaller of these two values:
if(AX > [loc16]), AX = [loc16]; if(AX <= [loc16]), AX = unchanged;
Description
Flags and Modes
If AX is less than the contents of the addressed location (AX < [loc16]) then the negative flag bit will be set; otherwise, it will be cleared. If AX and the contents of the addressed location are equal (AX = [loc16]) then the zero flag bit will be set; otherwise, it will be cleared. If AX is greater then the contents of the addressed location (AX > [loc16]) then the overflow flag bit will be set. This instruction cannot clear the V flag. If the operation is follows a RPT instruction, the instruction will be executed N+1 times. The state of the N, Z and V flags will reflect the final result.
Repeat
Example
; Saturate VarA as follows: ; if(VarA > 2000) VarA = 2000; ; if(VarA < 2000) VarA = 2000; MOV AL,@VarA ; Load AL with contents of VarA MOV @AH,#2000 ; Load AH with the value 2000 MIN AL,@AH ; if(AL > AH) AL = AH NEG AH ; AH = 2000 MAX AL,@AH ; if(AL < AH) AL = AH MOV @VarA,AL ; Store result into VarA
6-153
MINCUL P,loc32
MINCUL P,loc32 SYNTAX OPTIONS MINCUL P,loc32 Operands

P loc32
Conditionally Find the Unsigned Minimum OPCODE

OBJMODE RPT 1
CYC 1
Product register Addressing mode (see Chapter 5) Based on the state of the N and Z flags, conditionally compare the unsigned contents of the P register with the 32-bit, unsigned content of the location pointed to by the loc32 addressing mode and load the P register with the smaller of the two numbers:
if( (N = 0) & (Z = 0) ) P = [loc32]; if( (N = 0) & (Z = 1) & (P > [loc32]) ) V=1, P = [loc32]; if( (N = 1) & (Z = 0) ) P = unchanged; Note: The p < [loc32] operation is treated like a 32-bit unsigned compare.
Description
This instruction is typically combined with the MINL instruction to form a 64-bit minimum function. It is assumed that the N and Z flags will first be set by using a MINL instruction to compare the upper 32 bits of a 64-bit value. The MINCUL instruction is then used to conditionally compare the lower 32 bits based on the results of the upper 32-bit comparison. Flags and Modes
N Z
If (N = 1 AND Z = 0), then load the P register with [loc32]. If (N = 0 AND Z =1), compare unsigned and load P with the smaller P register to [loc32]. If (N = 0 AND Z = 0), do nothing. If (N = 0 AND Z = 1 AND P < [loc32] ) then V is set; otherwise, V is unchanged. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat Example
; Saturate 64-bit Var64 as follows: ; if(Var64 > MaxPos64 ) Var64 = MaxPos64 ; if(Var64 < MaxNeg64 ) Var64 = MaxNeg64 MOVL ACC,@Var64+2 ; Load ACC:P with Var64 MOVL P,@Var64+0 MINL ACC,@MaxPos64+2 ; if(ACC:P > MaxPos64) ACC:P = MaxPos64 MINCUL P,@MaxPos64+0 MAXL ACC,@MaxNeg64+2 ; if(ACC:P < MaxNeg64) ACC:P = MaxNeg64 MAXCUL P,@MaxNeg64+0 MOVL @Var64+2,ACC ; Store result into Var64 MOVL @Var64+0,P
6-154
MINL ACC,loc32
MINL ACC,loc32 SYNTAX OPTIONS MINL ACC,loc32 Operands

ACC loc32
Find the 32-bit Minimum OPCODE

0101 0110 0101 0000 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Compare the content of the ACC register with the location pointed to by the loc32 addressing mode and load the ACC register with the smaller of these two values:
if(ACC <= [loc32]), ACC = unchanged; if(ACC > [loc32]), ACC = [loc32];
Description
Flags and Modes
If ACC is equal to the contents of the addressed location (ACC = [loc32]), set Z; otherwise clear Z. If ACC is less than the contents of the addressed location, (ACC < [loc32]), set N; otherwise clear N. The MINL instruction assumes infinite precision when it determines the sign of the result. For example, consider the subtraction 0x8000 0000 0x0000 0001. If the precision were limited to 32 bits, the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared. However, because the MINL instruction assumes infinite precision, it would set N to indicate that 0x8000 0000 0x0000 0001 actually results in a negative number. If (ACC [loc32]) generates a borrow, clear the C bit; otherwise set C. If ACC is greater than the contents of the addressed location (ACC < [loc32]), set V. This instruction cannot clear the V flag. This instruction is repeatable. If the operation follows a RPT instruction, then the MINL instruction will be executed N+1 times. The state of the Z, N, and C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
C V
Repeat
Example
; Saturate VarA as follows: ; if(VarA > MaxPos) VarA = MaxPos ; if(VarA < MaxNeg) VarA = MaxNeg MOVL ACC,@VarA ; ACC = VarA MINL ACC,@MaxPos ; if(ACC > MaxPos) ACC = MaxPos MAXL ACC,@MaxNeg ; if(ACC < MaxNeg) ACC = MaxNeg MOVL @VarA,ACC ; Store result into VarA
6-155
MOV *(0:16bit), loc16
MOV *(0:16bit), loc16 SYNTAX OPTIONS MOV *(0:16bit),loc16 OPCODE

Move Value OBJMODE RPT X Y CYC N+2
Operands
*(0:16bit)
Immediate direct memory address, access low 64K range of data space only (0x00000000 to 0x0000FFFF) Addressing mode (see Chapter 5) Move the content of the location pointed to by the loc16 addressing mode to the memory location specified by the 0:16bit constant address:
[0x0000:16bit] = [loc16];
loc16
Description
None
This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the (0:16bit) data-memory address is post-incremented by 1 during each repetition. Only the lower 16 bits of the address is affected.
; ; ; ; ; Copy the contents of Array1 to Array2: int16 Array1[N]; int16 Array2[N]; // Located in low 64K of data space for(i=0; i < N; i++) Array2[i] = Array1[i];
Example
MOVL XAR2,#Array1 RPT #(N1) ||MOV *(0:Array2),*XAR2++ ; ; ; ; XAR2 = pointer to Array1 Repeat next instruction N times Array2[i] = Array1[i], i++
6-156
MOV ACC,#16bit<<#0..15
MOV ACC,#16bit<<#0..15 SYNTAX OPTIONS MOV ACC,loc16<<#0..15 OPCODE

Load Accumulator With Shift OBJMODE X RPT CYC 1
Operands
ACC #16bit #0..15
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Load the ACC register with the left shifted contents of the 16-bit immediate value. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = S:16bit << shift value; else // sign extension mode disabled ACC = 0:16bit << shift value;
Description
Flags and Modes
N Z SXM
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the load, the Z flag is set if the ACC value is zero, else Z is cleared. If sign extension mode bit is set; then the 16-bit constant operand will be sign extended before the load; else, the value will be zero extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate signed value: ACC = 2010 << 10 + VarB << 6; SETC SXM ; Turn sign extension mode on MOV ACC,#2010 << #10 ; Load ACC with 2010 left shifted by 10 ADD ACC,@VarB << #6 ; Add VarB left shifted by 6 to ACC
6-157
MOV ACC,loc16<<T
MOV ACC,loc16<<T SYNTAX OPTIONS MOV ACC,loc16 << T OPCODE

0101 0110 0000 0110 0000 0000 LLLL LLLL
Load Accumulator With Shift OBJMODE 1 RPT CYC 1
Operands
ACC loc16 T
Accumulator register Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register, XT(31:16) Load the ACC register with the left-shifted contents of the 16-bit location pointed to by the loc16 addressing mode. The shift value is specified by the four least significant bits of the T register, T(3:0) = shift value = 0..15. Higher order bits are ignored. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = S:[loc16] << T(3:0); else // sign extension mode disabled ACC = 0:[loc16] << T(3:0);
Description
Flags and Modes
N Z SXM
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the load, the Z flag is set if the ACC value is zero, else Z is cleared. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the load; else the value will be zero extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate signed value: ACC = (VarA << SB) + (VarB << SB) SETC SXM ; Turn sign extension mode on MOV T,@SA ; Load T with shift value in SA MOV ACC,@VarA << T ; Load in ACC shifted contents of VarA MOV T,@SB ; Load T with shift value in SB ADD ACC,@VarB << T ; Add to ACC shifted contents of VarB
6-158
MOV ACC, loc16<<#0..16
MOV ACC, loc16<<#0..16 SYNTAX OPTIONS MOV ACC,loc16<<#0 MOV ACC, loc16<<#1..15 OPCODE
1000 0101 LLLL LLLL 1110 0000 LLLL LLLL 0101 0110 0000 0011 0000 SHFT LLLL LLLL 1110 SHFT LLLL LLLL
Load Accumulator With Shift OBJMODE 1 0 1 0 X RPT CYC 1 1 1 1 1
MOV ACC, loc16<<#16 Operands

ACC loc16 #0..16
0010 0101 LLLL LLLL
Accumulator register Addressing mode (see Chapter 5) Shift value (default is << #0 if no value specified) Load the ACC register with the left shifted contents of the addressed location pointed to by the loc16 addressing mode. The shifted value is sign extended if sign extension mode is turned on (SXM = 1) else the shifted value is zero extended (SXM = 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = S:[loc16] << shift value; else // sign extension mode disabled ACC = 0:[loc16] << shift value;
Description
Flags and Modes
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the load, the Z flag is set if the ACC is zero, else Z is cleared. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the load; else the value will be zero extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z SXM
Repeat
Example
; Calculate signed value: ACC = VarA << 10 + VarB << 6; SETC SXM ; Turn sign extension mode on MOV ACC,@VarA << #10 ; Load ACC with VarA left shifted by 10 ADD ACC,@VarB << #6 ; Add VarB left shifted by 6 to ACC
6-159
MOV AR6/7, loc16
MOV AR6/7, loc16 SYNTAX OPTIONS MOV AR6, loc16 MOV AR7, loc16 Operands
AR6/7 loc16 Description
Load Auxiliary Register OPCODE

0101 1110 LLLL LLLL 0101 1111 LLLL LLLL
OBJMODE X X
RPT
CYC 1 1
AR6 or AR7, auxiliary registers Addressing mode (see Chapter 5) Load AR6 or AR7 with the contents of the 16-bit location and leave the upper 16 bits of XAR6 and XAR7 unchanged:
AR6/7 = [loc16]; AR6/7H = unchanged;
None
6-160
MOV AX, loc16
MOV AX, loc16 SYNTAX OPTIONS MOV AX, loc16 Operands

AX loc16
Load AX OPCODE
1001 001A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Load accumulator high register (AH) or accumulator low register (AL) register with the 16-bit contents of the location pointed to by the loc16 addressing mode, leaving the other half of the accumulator register unchanged:
AX = [loc16];
Description
Flags and Modes
The load to AX is tested for a negative condition. If bit 15 of AX is 1, then this flag is set; otherwise it is cleared. The load to AX is tested for a zero condition. The bit is set if the operation results in AX = 0, otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
MOV
AH, *+XAR0[0]
SB
NotZero,NEQ
; ; ; ; ;
Load AH with the 16-bit contents of location pointed to by XAR0. AL is unchanged. Branch if contents of AH were non zero.
6-161
MOV DP, #10bit
MOV DP, #10bit SYNTAX OPTIONS MOV DP, #10bit Operands

DP #10bit
Load Data-Page Pointer OPCODE

1111 10CC CCCC CCCC
OBJMODE RPT X
CYC 1
Data page register 10-bit immediate constant value Load the data page register with a 10-bit constant leaving the upper 6 bits unchanged:
DP(9:0) = 10bit; DP(15:10) = unchanged;
Description
None
MOV DP, #VarA ; ; ; ; Load DP with the data page that contains VarA. Assumes VarA is in the lower 0x0000 FFC0 of memory. DP(15:10) is left unchanged.
Example
6-162
MOV IER,loc16
MOV IER,loc16 SYNTAX OPTIONS MOV IER,loc16 Operands

IER loc16 Description
Load the Interrupt-Enable Register OPCODE

0010 0011 LLLL LLLL
OBJMODE RPT X
CYC 5
Interrupt-enable register Addressing mode (see Chapter 5) Enable and disable selected interrupts by loading the content of the location pointed to by the loc16 addressing mode into the IER register:
IER = [loc16];
None
; Push the contents of IER on the stack and load IER with the ; contents of VarA: MOV *SP++,IER ; Save IER on stack MOV IER,@VarA ; Load IER with contents of VarA
Example
6-163
MOV loc16, #16bit
MOV loc16, #16bit SYNTAX OPTIONS MOV loc16, #16bit OPCODE

Save 16-bit Constant OBJMODE RPT X Y CYC N+1
Operands
loc16 #16bit
Addressing mode (see Chapter 5) 16-bit constant immediate value Load the location pointed to by the loc16 addressing mode with the 16-bit constant immediate value:
[loc16] = 16bit; Note: For #16bit = #0, see the MOV loc16, #0 instruction on page 6-166.
Description
Smart Encoding: If loc16 = AL or AH and #16bit is an 8-bit number, then the assembler will encode this instruction as MOVB AX, #8bit to improve efficiency. To override this, use the MOVW AX, #16bit alias instruction. Flags and Modes
Z N
If (loc16 = @AX), then the load to AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Initialize the contents of Array1 with 0xFFFF: ; int16 Array1[N]; ; for(i=0; i < N; i++) ; Array1[i] = 0xFFFF; MOVL XAR2,#Array1 ; XAR2 = pointer to Array1 RPT #(N1) ; Repeat next instruction N times ||MOV *XAR2++,#0xFFFF ; Array1[i] = 0xFFFF, ; i++
6-164
MOV loc16, *(0:16bit)
MOV loc16, *(0:16bit) SYNTAX OPTIONS MOV loc16, *(0:16bit) OPCODE

Move Value OBJMODE RPT X Y CYC N+2
Operands
loc16 *(0:16bit)
Addressing mode (see Chapter 5) Immediate direct memory address, access low 64K range of data space only (0x00000000 to 0x0000FFFF) Move the content of the location specified by the constant direct memory address 0:16bit into the location pointed to by the loc16 addressing mode:
[loc16] = [0x0000:16bit];
Description
Flags and Modes
If (loc16 = @AX), then the load to AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the (0:16bit) data-memory address is post-incremented by 1 during each repetition. Only the lower 16 bits of the address are affected.
; ; ; ; ; Copy the contents of Array1 to Array2: int16 Array1[N]; // Located in low 64K of data space int16 Array2 N]; for(i=0; i < N; i++) Array2[i] = Array1[i];
Repeat
Example
MOVL XAR2,#Array2 RPT #(N1) ||MOV *XAR2++,*(0:Array1) ; ; ; ; XAR2 = pointer to Array2 Repeat next instruction N times Array2[i] = Array1[i], i++
6-165
MOV loc16, #0
MOV loc16, #0 SYNTAX OPTIONS MOV loc16, #0 Operands

loc16 #0
Clear 16-bit Location OPCODE

0010 1011 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Addressing mode (see Chapter 5) Immediate constant value of zero Load the location pointed to by the loc16 addressing mode with the value 0x0000:
[loc16] = 0x0000;
Description
Flags and Modes
N Z
If (loc16 = @AX), then the load to AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared. This instruction is repeatable. If the operation is follows a RPT instruction, then it will be executed N+1 times.
Repeat
Example
; Initialize the contents of Array1 with zero: ; int16 Array1[N]; ; for(i=0; i < N; i++) ; Array1[i] = 0; MOVL XAR2,#Array1 RPT #(N1) ||MOV *XAR2++,#0 ; ; ; ; XAR2 = pointer to Array1 Repeat next instruction N times Array1[i] = 0, i++
6-166
MOV loc16,ACC << 1..8
MOV loc16,ACC << 1..8 SYNTAX OPTIONS MOV loc16, ACC << 1 MOV loc16, ACC << 2..8
Save Low Word of Shifted Accumulator OPCODE

1011 0001 LLLL LLLL 0101 0110 0010 1101 0000 0SHF LLLL LLLL 1011 1SHF LLLL LLLL
OBJMODE RPT 1 1 0 Y Y
CYC N+1 N+1 1
Operands
loc16 ACC #1..8
Addressing mode (see Chapter 5) Accumulator register Shift value Load the content of the location pointed to by the loc16 addressing mode with the low word of the ACC register after leftshifting by the specified value. The ACC register is not modified:
[loc16] = ACC >> (16 shift value); [loc16] = low (ACC <<1...8)
Description
Flags and Modes
If (loc16 = @AX), then after the load AX is checked for a negative condition. The N flag is set if bit 15 of the AX is 1; else N is cleared. If (loc16 = @AX) then after the load AX is checked for a zero condition. The Z flag is set if AX is zero; else Z is cleared. If the operation is repeatable, then the instruction will be executed N+1 times. The state of the Z and N flags will reflect the final result. If the operation is not repeatable, the instruction will execute only once.
Repeat
Example
; Multiply two Q15 numbers (VarA and VarB) and store result in ; VarC as a Q15 number: MOV T,@VarA ; T = VarA (Q15) MPY ACC,T,@VarB ; ACC = VarA * VarB (Q30) MOVH @VarC,ACC << 1 ; VarC = ACC >> (161) (Q15) ; VarC as a Q31 number: MOV T,@VarA ; T = VarA (T = Q14) MPY ACC,T,@VarB ; ACC = VarA * VarB (ACC = Q28) MOV @VarC+0,ACC << 3 ; VarC low = ACC << 3 MOVH @VarC+1,ACC << 3 ; VarC high = ACC >> (161) (VarC = Q31)
6-167
MOV loc16, ARn
MOV loc16, ARn SYNTAX OPTIONS MOV loc16, ARn Operands

loc16 ARn
Store 16-bit Auxiliary Register OPCODE

0111 1nnn LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) AR0 to AR7, lower 16 bits of auxiliary registers Load the contents of the 16-bit location with ARn:
[loc16] = ARn;
Description
If(loc16 = @ARn), then only the lower 16 bits of the selected auxiliary register is modified. The upper 16 bits is unchanged. Flags and Modes
N
If (loc16 = @AX), then the load to AX is tested for a negative condition. Bit-15 of the AX register is the sign bit, 0 for positive, 1 for negative. The negative flag bit is set if the operation on the AX register generates a negative value, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared This instruction is not repeatable. If the operation is follows a RPT instruction, it resets the repeat counter (RPTC) and only executes once.
Repeat
Example
MOV
@AL, AR3
; ; ; ;
Load AL with the 16-bit contents of AR3. If bit 15 of AL is 1, set the N flag, else clear it. If AL is 0, set the Z flag.
MOV
@AR4,AR3
; Load AR4 with the value in AR3. ; Upper 16 bits of XAR4 are ; unchanged. ; Push the contents of AR3 onto the ; stack. Post increment SP. ; Store contents of AR4 into location ; specified by XAR4. Post-increment ; the contents of XAR4. ; Pre-decrement the contents of XAR5. ; Store the contents of AR5 into the ; location specified by XAR5.
MOV
*SP++,AR3
MOV
*XAR4++,AR4
MOV
*XAR5,AR5
6-168
MOV loc16, AX
MOV loc16, AX SYNTAX OPTIONS MOV loc16, AX Operands

loc16 AX
Store AX OPCODE
1001 011A LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Load the addressed location pointed to by the loc16 addressing mode with the 16-bit content of the specified AX register (AH or AL):
[loc16] = AX;
Description
Flags and Modes
If (loc16 = @AX), then the load to AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared. If this operation follows a RPT instruction, then it will be executed N+1 times. The state of the N and Z flags will reflect the final result.
Repeat
Example
; Initialize all Array1 elements with the value 0xFFFF: MOV AH,#0xFFFF ; Load AH with the value 0xFFFF MOVL XAR2,#Array1 ; Load XAR2 with address of Array1 RPT #9 ; Repeat next instruction 10 times. || MOV *XAR2++, AH ; Store contents of AH into location ; pointed by XAR2 and post-increment ; XAR2.
6-169
MOV loc16, AX, COND
MOV loc16, AX, COND SYNTAX OPTIONS MOV loc16, AX, COND Operands
loc16 AX COND
Store AX Register Conditionally OPCODE

0101 0110 0010 101A 0000 COND LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Conditional codes:
COND Syntax Description Flags Tested
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description
NEQ EQ GT GEQ LT LEQ HI HIS, C LO, NC LOS NOV OV NTC TC NBIO UNC
Not Equal To Equal To Greater Then Greater Then Or Equal To Less Then Less Then Or Equal To Higher Higher Or Same, Carry Set Lower, Carry Clear Lower Or Same No Overflow Overflow Test Bit Not Set Test Bit Set BIO Input Equal To Zero Unconditional
Z=0 Z=1 Z = 0 AND N = 0 N=0 N=1 Z = 1 OR N = 1 C = 1 AND Z = 0 C=1 C=0 C = 0 OR Z = 1 V=0 V=1 TC = 0 TC = 1 BIO = 0
If the specified condition being tested is true, then the location pointed to by the loc16 addressing mode will be loaded with the contents of the specified AX register (AH or AL):
if(COND = true) [loc16] = AX; Note: Addressing modes are not conditionally executed. Hence, if an addressing mode performs a pre or post modification, the modification will occur, regardless of whether the condition is true or not.
Flags and Modes
If (COND = true AND loc16 = @AX), AX is tested for a negative condition after the move and if bit 15 of AX is 1, the negative flag bit is set. If (COND = true AND loc16 = @AX), after the move, AX is tested for a zero condition and the zero flag bit is set if AX = 0, otherwise, it is cleared. If the V flag is tested by the condition, then V is cleared.
6-170
MOV loc16, AX, COND
Repeat Example
; Swap the contents of VarA and VarB if VarB is higher then VarA: MOV AL,@VarA ; AL = VarA, XAR2 points to VarB MOV AH,@VarB ; AH = VarB, XAR2 points to VarA CMP AH,@AL ; Compare AH and AL MOV @VarA,AH,HI ; Store AH in VarA if higher MOV @VarB,AL,HI ; Store AL in VarB if higher
6-171
MOV loc16,IER
MOV loc16,IER SYNTAX OPTIONS MOV loc16,IER Operands

loc16 IER
Store Interrupt-Enable Register OPCODE

0010 0000 LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Interrupt enable register Save the content of the IER register in the location pointed to by the loc16 addressing mode:
[loc16] = IER;
Description
Flags and Modes
N Z
If (loc16 = @AX) and bit 15 of AX is 1, then N is set; otherwise N is cleared. If (loc16 = @AX) and the value of AX is zero, then Z is set; otherwise Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Push the contents of IER on the stack and load IER with the ; contents of VarA: MOV *SP++,IER ; Save IER on stack MOV IER,@VarA ; Load IER with contents of VarA
6-172
MOV loc16,OVC
MOV loc16,OVC SYNTAX OPTIONS MOV loc16,OVC OPCODE

0101 0110 0010 1001 0000 0000 LLLL LLLL
Store the Overflow Counter OBJMODE RPT 1 CYC 1
Operands
loc16 OVC
Addressing mode (see Chapter 5) Overflow counter Store the 6 bits of the overflow counter (OVC) into the upper 6 bits of the location pointed to by the loc16 addressing mode and zero the lower 10 bits of the addressed location:
[loc16(15:10)] = OVC; [loc16(9:0)] = 0;
Description
Flags and Modes
N Z
If (loc16 = @AX) and bit 15 of AX is 1, then set N; otherwise clear N. If (loc16 = @AX) and AX is zero, then set Z; otherwise clear Z. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Save and restore contents of ACC and OVC bits: MOV *SP++,OVC ; Save OVC on stack MOV *SP++,AL ; Save AL on stack MOV *SP++,AH ; Save AH on stack . . . . MOV AH,*SP ; Restore AH from stack MOV AL,*SP ; Restore AL from stack MOV OVC,*SP ; Restore OVC from stack
6-173
MOV loc16,P
MOV loc16,P SYNTAX OPTIONS MOV loc16,P Operands

loc16 P
Store Lower Half of Shifted P Register OPCODE

0011 1111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Addressing mode (see Chapter 5) Product register The contents of the P register are shifted by the amount specified in the product shift mode (PM), and the lower half of the shifted value is stored into the 16-bit location pointed to by the loc16 addressing mode. The P register is not modified by the operation:
[loc16] = P << PM;
Description
Flags and Modes
If (loc16 = @AX) and bit 15 of the AX register is 1, then the N bit is set; otherwise, N is cleared. If (loc16 = @AX) and the value of AX after the load is zero, then the Z bit is set; otherwise Z is cleared. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, and N flags will reflect the final result.
PM
Repeat
Example
; Calculate Y32 = M16*X16 >> 6 MOV T,@M16 ; T = MPY P,T,@X16 ; P = SPM 6 ; Set MOV @Y32+0,P ; Y32 MOVH @Y32+1,P
M T * X product shift to >> 6 = P >> 6
6-174
MOV loc16, T
MOV loc16, T SYNTAX OPTIONS MOV, loc16,T Operands

loc16 T
Store the T Register OPCODE

0010 0001 LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register (XT) Store the 16-bit T register contents into the location pointed to by the loc16 addressing mode: [loc16] = T;
Description
Flags and Modes
If (loc16 = @AX) and bit 15 of the AX register is 1, then the N bit is set; otherwise, N is cleared. If (loc16 = @AX) and the value of AX after the load is zero, then the Z bit is set; otherwise Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 MOV T,@X2 ; T = X2 MPY P,T,@C2 ; P = T*C2 MOVP T,@X1 ; T = X1, ACC = X2*C2 >> 2 MPY P,T,@C1 ; P = T*C1 MOV @X2,T ; X2 = X1 MOVA T,@X0 ; T = X0, ACC = X1*C1 >> 2 + X2*C2 >> 2 MPY P,T,@C0 ; P = T*C0 MOV @X1,T ; X1 = X0 ADDL ACC,P << PM ; ACC = X0*C0 >> 2 + X1*C1 >> 2 + X2*C2 >> 2 MOVL @Y,ACC ; Store result into Y
6-175
MOV OVC, loc16
MOV OVC, loc16 SYNTAX OPTIONS MOV OVC, loc16 OPCODE

0101 0110 0000 0010 0000 0000 LLLL LLLL
Load the Overflow Counter OBJMODE RPT 1 CYC 1
OVC
6-bit overflow counter Load the overflow counter (OVC) with the upper 6 bits of the location pointed to by the loc16 addressing mode:
OVC = [loc16(15:10)];
OVC
The 6-bit overflow counter is modified.
; Save and restore contents of ACC and OVC bits: MOV *SP++,OVC ; Save OVC on stack MOV *SP++,AL ; Save AL on stack MOV *SP++,AH ; Save AH on stack . . . . MOV AH,*SP ; Restore AH from stack MOV AL,*SP ; Restore AL from stack MOV OVC,*SP ; Restore OVC from stack
Example
6-176
MOV PH, loc16
MOV PH, loc16 SYNTAX OPTIONS MOV PH, loc16 Operands

PH loc16
Load the High Half of the P Register OPCODE

0010 1111 LLLL LLLL
OBJMODE RPT X
CYC 1
Upper 16 bits of the product register (P) Addressing mode (see Chapter 5) Load the high 16 bits of the P register (PH) with the 16-bit location pointed to by the loc16 addressing mode; leave the lower 16 bits (PL) unchanged:
PH = [loc16]; PL = unchanged;
Description
None
; Swap the contents of AH and AL: MOV PH,@AL ; Load PH with AL MOV PL,@AH ; Load PL with AH MOV ACC,@P ; Load ACC with P (AH and AL swapped)
Example
6-177
MOV PL, loc16
MOV PL, loc16 SYNTAX OPTIONS MOVL PL, loc16 Operands

PL loc16
Load the Low Half of the P Register OPCODE

0010 0111 LLLL LLLL
OBJMODE RPT X
CYC 1
Lower 16 bits of the product register (P) Addressing mode (see Chapter 5) Load the high 16 bits of the P register (PL) with the 16-bit location pointed to by the loc16 addressing mode; leave the lower 16 bits (PH) unchanged:
PL = [loc16]; PH = unchanged;
Description
None
; Swap the contents of AH and AL: MOV PH,@AL ; Load PH with AL MOV PL,@AH ; Load PL with AH MOV ACC,@P ; Load ACC with P (AH and AL swapped)
Example
6-178
MOV PM, AX
MOV PM, AX SYNTAX OPTIONS MOV PM, AX Operands Description

AX
Load Product Shift Mode OPCODE

0101 0110 0011 100A
OBJMODE RPT 1
CYC 1
Accumulator high (AH) or accumulator low (AL) registers. Load the product shift mode (PM) bits with the 3 least significant bits of register AX.
PM = AX(2:0);
PM
The product shift mode bits are loaded with the 3 least significant bits of AX.
; Calculate: Y32 = (M16*X16 >> Shift) + B32, Shift = 0 to 6 CLRC AMODE ; Make sure AMODE = 0 MOV AL,@Shift ; Load AL with contents of Shift ADDB AL,#1 ; Convert Shift to PM encoding MOV PM,AX ; Load PM bits with encoded Shift value MOV T,@X16 ; T = X16 MPY P,XT,@M16 ; P = X16*M16 MOVL ACC,@B32 ; ACC = B32 ADDL ACC,P << PM ; ACC = ACC + (P >> Shift) MOVL @Y32,ACC ; Store result into Y32
Example
6-179
MOV T, loc16
MOV T, loc16 SYNTAX OPTIONS MOV T, loc16 Operands

T loc16
Load the Upper Half of the XT Register OPCODE

0010 1101 LLLL LLLL
OBJMODE RPT X
CYC 1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the T register with the 16-bit contents of the location pointed to by the loc16 addressing mode:
T = [loc16];
Description
None
Example
6-180
MOV TL, #0
MOV TL, #0 SYNTAX OPTIONS MOV TL, #0 Operands

T #0
Clear the Lower Half of the XT Register OPCODE

0101 0110 0101 0110
OBJMODE RPT 1
CYC 1
Upper 16 bits of the multiplicand register (XT) Immediate constant value of zero Load the lower half of the multiplicand register (TL) with zero, leaving the upper half (T) unchanged:
TL = 0x0000; T = unchanged;
Description
None
; Calculate and keep low 32-bit result: Y32 = M32*X16 >> 32 MOV TL,#0 ; TL = 0 MOV T,@X16 ; T = X16 IMPYL P,XT,@M32 ; P = XT * M32 (high 32-bit of result) MOVL @Y32,P ; Store result into Y32
Example
6-181
MOV XARn, PC
MOV XARn, PC SYNTAX OPTIONS MOV XARn, PC Operands

XARn loc32 PC
Save the Current Program Counter OPCODE 0011 1110 0101 1nnn XAR0 to XAR7, 32-bit auxiliary registers Addressing mode (see Chapter 5) 22-bit program counter Load XARn with the contents of the PC:
XARn = 0:PC;
OBJMODE 1
RPT
CYC 1
Description
None
TableA: .long CONST1 .long CONST2 .long CONST3 . FuncA: MOV XAR5,PC SUBB XAR5,#($TableA) MOVL ACC,*+XAR5[2] MOVL @VarA,ACC ; Location of TableA is relative to ; the current program
Example
; ; ; ;
XAR5 = current PC location XAR5 = TableA start location Load ACC with CONST2 Store CONST2 in VarA
6-182
MOVA T,loc16
MOVA T,loc16 SYNTAX OPTIONS MOVA, T,loc16 Operands

T loc16
Load T Register and Add Previous Product OPCODE

0001 0000 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the T register with the 16-bit content of the location pointed to by the loc16 addressing mode. Also, the content of the P register, shifted by the amount specified by the product shift mode (PM) bits, is added to the content of the ACC register:
T = [loc16]; ACC = ACC + P << PM;
Description
Flags and Modes
After the operation, if bit 31 of the ACC register is 1, the N bit is set; otherwise, N is cleared. After the operation, if the value of ACC is zero, the Z bit is set; otherwise Z is cleared. If the addition generates a carry, then C is set; otherwise, C is cleared. If an overflow occurs, V is set; otherwise V is not affected If overflow mode is disabled; and if the operation generates a positive overflow, the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, the counter is decremented. If overflow mode bit is set; the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, it will be executed N+1 times. The state of the Z, N, C and OVC flags reflect the final result. The V flag will be set if an intermediate overflow occurs.
Z
C V OVC
OVM
PM
Repeat
6-183
MOVA T,loc16
Example
6-184
MOVAD T, loc16
MOVAD T, loc16 SYNTAX OPTIONS MOVAD T, loc16 Operands

T loc16
Load T Register OPCODE

1010 0111 LLLL LLLL
OBJMODE RPT 1 N
CYC 1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5)
Note: For this operation, register-addressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T. An illegal instruction trap will be generated.
Description
Load the T register with the 16-bit content of the location pointed to by the loc16 addressing mode and then load the next highest 16-bit location pointed to by loc16 with the content of T. In addition, add the content of the P register, shifted by the amount specified by the product shift mode (PM) bits, to the content of the ACC register:
T = [loc16]; [loc16 + 1] = T; ACC = ACC + P << PM;
Flags and Modes
After the operation, if bit 31 of the ACC register is 1, then the N bit is set; otherwise, N is cleared. After the operation, if the value of ACC is zero, then the Z bit is set; otherwise Z is cleared. If the addition generates a carry, the C bit is set; otherwise, C is cleared. If an overflow occurs, V is set; otherwise V is not affected If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V OVC
OVM
PM
Repeat
6-185
MOVAD T, loc16
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 MOVP T,@X2 ; T = X2 MPYS P,T,@C2 ; P = T*C2, ACC = 0 MOVAD T,@X1 ; T = X1, ACC = X2*C2>>2, X2 = X1 MPY P,T,@C1 ; P = T*C1 MOVAD T,@X0 ; T = X0, ACC = X1*C1>>2 + X2*C2>>2, X1 = X0 MPY P,T,@C0 ; P = T*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
6-186
MOVB ACC,#8bit
MOVB ACC,#8bit SYNTAX OPTIONS MOVB ACC,#8bit Operands

ACC #8bit
Load Accumulator With 8-bit Value OPCODE

0000 0010 CCCC CCCC
OBJMODE 1
RPT
CYC 1
Accumulator register 8-bit immediate unsigned constant value Load the ACC register with the specified 8-bit, zero-extended immediate constant:
ACC = 0:8bit;
Description
Flags and Flags and Repeat
N Z
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the load, the Z flag is set if the ACC value is zero, else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Increment contents of 32-bit location VarA: MOVB ACC,#1 ; Load ACC with the value 0x0000 0001 ADDL ACC,@VarA ; Add to ACC the contents of VarA MOVL @VarA,ACC ; Store result back into VarA
6-187
MOVB AR6/7, #8bit
MOVB AR6/7, #8bit SYNTAX OPTIONS MOVB AR6, #8bit MOVB AR7, #8bit Operands
XARn #8bit
Load Auxiliary Register With an 8-bit Constant OPCODE

1101 0110 CCCC CCCC 1101 0111 CCCC CCCC
OBJMODE RPT X X
CYC 1 1
XAR6 OR XAR7, 32-bit auxiliary registers 8-bit immediate constant value Load AR6 or AR7 with an 8-bit unsigned constant and upper 16 bits of XAR6 and XAR7 are unchanged:
AR6/7 = 0:8bit; AR6/7H = unchanged;
Description
None
6-188
MOVB AX, #8bit
MOVB AX, #8bit SYNTAX OPTIONS MOVB AX, #8bit Operands

AX #8bit
Load AX With 8-bit Constant OPCODE

1001 101A CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate constant value Load accumulator high register (AH) or accumulator low register (AL) with an unsigned 8-bit constant zero extended, leaving the other half of the accumulator register unchanged:
AX = 0:8bit;
Description
Flags and Modes
Flag always set to zero. The load to AX is tested for a zero condition. The bit is set if the operation results in AX = 0, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
MOVB AL, #0xF0 CMP AL,*+XAR0[0] SB Dest,EQ
; ; ; ;
Load AL with the value 0x00F0. Compare contents pointed to by XAR0 with AL. Branch if values are equal.
6-189
MOVB AX.LSB, loc16
MOVB AX.LSB, loc16 SYNTAX OPTIONS MOVB AX.LSB, loc16 Operands OPCODE
1100 011A LLLL LLLL
Load Byte Value OBJMODE RPT X CYC 1
AX.LSB Least significant byte of accumulator high (AH.LSB) or accumulator low
(AL.LSB) register
loc16
Addressing mode (see Chapter 5) Load the least significant byte of the specified AX register (AH.LSB or AL.LSB) with 8 bits from the location pointed to by the loc16 addressing mode. The most significant byte of AX is cleared. The form of the loc16 operand determines which of its 8 bits are used to load AX.LSB:
if(loc16 = *+XARn[offset]) { if(offset is an even number) AX.LSB = [loc16.LSB]; if(offset is an odd value) AX.LSB = [loc16.MSB]; } else AX.LSB = [loc16.LSB]; AX.MSB = 0x00; Note: offset = 3-bit immediate or AR0 or AR1 indexed addressing modes only.
Description
For the following address modes, the returned result is undefined: *AR6%++ *0++ *0 *BR0++ *BR0 *0++, ARPn *0, ARPn *BR0++, ARPn *BR0, ARPn Flags and Modes
Z
(AMODE = 0) (AMODE = x) (AMODE = x) (AMODE = x) (AMODE = x) (AMODE = 1) (AMODE = 1) (AMODE = 1) (AMODE = 1)
After the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0; otherwise it is cleared After the move, AX is tested for a negative condition. The bit is set if bit 15 of AX is 1; otherwise it is cleared.
6-190
MOVB AX.LSB, loc16
Repeat
; Swap the byte order in the 32-bit Var32 location. ; Before operation: Var32 = B3 | B2 | B1 | B0 ; After operation: Var32 = B0 | B1 | B2 | B3 MOVL XAR2,#Var32 ; Load XAR2 with address of Var32 MOVB ; ACC(B0) = Var32(B3), ACC(B1) = 0 AL.LSB,*+XAR2[3] MOVB ; ACC(B2) = Var32(B1), ACC(B3) = 0 AH.LSB,*+XAR2[1] MOVB ; ACC(B1) = Var32(B2), ACC(B1) = unch AL.MSB,*+XAR2[2] MOVB ; ACC(B3) = Var32(B0), ACC(B1) = unch AH.MSB,*+XAR2[0] MOVL @Var32,ACC ; Store swapped result in Var32
Example
6-191
MOVB AX.MSB, loc16
MOVB AX.MSB, loc16 SYNTAX OPTIONS MOVB AX.MSB, loc16 Operands

AX.MS B loc16
Load Byte Value OPCODE

0011 100A LLLL LLLL
OBJMODE RPT X
CYC 1
Most significant byte of accumulator high (AH.MSB) or accumulator low (AL.MSB) register Addressing mode (see Chapter 5) Load the most significant byte of the specified AX register (AH.MSB or AH.LSB) with 8 bits from the location pointed to by the loc16 addressing mode. The least significant byte of AX is left unchanged. The form of the loc16 operand determines which of its 8 bits are used to load AX.MSB
if(loc16 = *+XARn[offset]) { if(offset is an even value) AX.MSB = [loc16.LSB]; if(offset is an odd value) AX.MSB = [loc16.MSB]; } else AX.MSB = [loc16.LSB]; AX.LSB = unchanged; Note: offset = 3-bit immediate or AR0 or AR1 indexed addressing modes only.
Description
For the following address modes, the returned result is undefined: *AR6%++ *0++ *0 *BR0++ *BR0 *0++, ARPn *0, ARPn *BR0++, ARPn *BR0, ARPn Flags and Modes
N
After the move AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1; otherwise it is cleared. After the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0; otherwise it is cleared.
6-192
MOVB AX.MSB, loc16
Repeat
; Swap the byte order in the 32-bit Var32 location. ; Before operation: Var32 = B3 | B2 | B1 | B0 ; After operation: Var32 = B0 | B1 | B2 | B3 MOVL XAR2,#Var32 ; Load XAR2 with address of Var32 MOVB ; ACC(B0) = Var32(B3), ACC(B1) = 0 AL.LSB,*+XAR2[3] MOVB ; ACC(B2) = Var32(B1), ACC(B3) = 0 AH.LSB,*+XAR2[1] MOVB ; ACC(B1) = Var32(B2), ACC(B1) = unch AL.MSB,*+XAR2[2] MOVB ; ACC(B3) = Var32(B0), ACC(B1) = unch AH.MSB,*+XAR2[0] MOVL @Var32,ACC ; Store swapped result in Var32
Example
6-193
MOVB loc16,#8bit,COND
Conditionally Save 8-bit Constant
SYNTAX OPTIONS MOVB loc16,#8bit,COND
OPCODE
0101 0110 1011 COND CCCC CCCC LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
loc16 #8bit COND
Addressing mode (see Chapter 5) 8-bit immediate constant value Conditional codes:
Description
If the specified condition being tested is true, then the 8-bit zero extended constant is stored in the location pointed to by the loc16 addressing mode:
if(COND = true) [loc16] = 0:8bit;
Note: Addressing modes are not conditionally executed; therefore, if an addressing mode performs a pre- or post-modification, it will execute regardless of whether the condition is true or not.
Flags and Modes
If (COND = true AND loc16 = @AX), then after the move AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (COND = true AND loc16 = @AX), then after the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0, otherwise it is cleared. If the V flag is tested by the condition, then V is cleared.
6-194
Repeat
; Calculate: ; if( VarA > 20 ) ; VarA = 0; CMP @VarA,#20 MOVB @VarA,#0,GT
Example
; Set flags on (VarA 20) ; Zero VarA if greater then
6-195
MOVB loc16, AX.LSB
MOVB loc16, AX.LSB SYNTAX OPTIONS MOVB loc16, AX.LSB Operands

loc16
Store LSB of AX Register OPCODE

0011 110A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) (AL.LSB) register
AX.LSB Least significant byte of accumulator high (AH.LSB) or accumulator low
Description
Load 8 bits of the location pointed to by the loc16 addressing mode with the least significant byte of the specified AX register (AH.LSB or AL.LSB). The form of the loc16 operand determines which of its 8 bits are loaded and which of its 8 bits are left unchanged:
if(loc16 = *+XARn[offset]) { if(offset is an even value) [loc16.LSB] = AX.LSB; [loc16.MSB] = unchanged; if(offset is an odd value) [loc16.LSB] = unchanged; [loc16.MSB] = AX.LSB; } else [loc16.LSB] = AX.LSB; [loc16.MSB] = unchanged; Note: offset = 3-bit immediate or AR0 or AR1 indexed addressing modes only.
This is a read-modify-write operation. For the following address modes, the returned result is undefined: *AR6%++ *0++ *0 *BR0++ *BR0 *0++, ARPn *0, ARPn *BR0++, ARPn *BR0, ARPn Flags and Modes
N Z
If (loc16 = @AX), then after the move AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then after the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0, otherwise it is cleared.
6-196
MOVB loc16, AX.LSB
Repeat
; Store the 32-bit contents of the ACC into the ; 32-bit contents of Var32 location in reverse byte order: ; Before operation: ACC = B3 | B2 | B1 | B0 ; After operation: Var32 = B0 | B1 | B2 | B3 MOVL XAR2,#Var32 ; Load XAR2 with address of Var32 MOVB ; Var32(B0) = ACC(B3) *+XAR2[0],AH.MSB MOVB ; Var32(B1) = ACC(B2) *+XAR2[1],AH.LSB MOVB ; Var32(B2) = ACC(B1) *+XAR2[2],AL.MSB MOVB ; Var32(B3) = ACC(B0) *+XAR2[3],AL.LSB
Example
6-197
MOVB loc16, AX.MSB
MOVB loc16, AX.MSB SYNTAX OPTIONS MOVB loc16, AX.MSB Operands

loc16 AX.MS B
Store MSB of AX Register OPCODE

1100 100A LLLL LLLL Addressing mode (see Chapter 5) Most significant byte of accumulator high (AH.MSB) or accumulator low (AL.MSB) register
OBJMODE RPT X
CYC 1
Description
Load 8 bits of the location pointed to by the loc16 addressing mode with the most significant byte of the specified AX register (AH.MSB or AL.MSB). The form of the loc16 operand determines which of its 8 bits are loaded and which of its 8 bits are left unchanged:
if(loc16 = *+XARn[offset]) { if( offset is an even number ) [loc16.LSB] = AX.MSB; [loc16.MSB] = unchanged; if( offset is an odd number ) [loc16.LSB] = unchanged; [loc16.MSB] = AX.MSB; } else [loc16.LSB] = AX.MSB; [loc16.MSB] = unchanged; Note: offset = 3-bit immediate or AR0 or AR1 indexed addressing modes only.
This is a read-modify-write operation. For the following address modes, the returned result is undefined: *AR6%++ *0++ *0 *BR0++ *BR0 *0++, ARPn *0, ARPn *BR0++, ARPn *BR0, ARPn Flags and Modes
N
If (loc16 = @AX), then after the move AX is tested for a negative condition. The negative flag bit is set if bit 15 of AX is 1, otherwise it is cleared. If (loc16 = @AX), then after the move, AX is tested for a zero condition. The zero flag bit is set if AX = 0, otherwise it is cleared.
6-198
MOVB loc16, AX.MSB
Repeat
; Store the 32-bit contents of the ACC into the ; 32-bit contents of Var32 location in reverse byte order: ; Before operation: ACC = B3 | B2 | B1 | B0 ; After operation: Var32 = B0 | B1 | B2 | B3 MOVL XAR2,#Var32 ; Load XAR2 with address of Var32 MOVB ; Var32(B0) = ACC(B3) *+XAR2[0],AH.MSB MOVB ; Var32(B1) = ACC(B2) *+XAR2[1],AH.LSB MOVB ; Var32(B2) = ACC(B1) *+XAR2[2],AL.MSB MOVB ; Var32(B3) = ACC(B0) *+XAR2[3],AL.LSB
Example
6-199
MOVB XARn, #8bit
MOVB XARn, #8bit SYNTAX OPTIONS MOVB XAR05, #8bit MOVB XAR6, #8bit MOVB XAR7, #8bit Operands
XARn #8bit
Load Auxiliary Register With 8-bit Value OPCODE

1101 0nnn CCCC CCCC 1011 1110 CCCC CCCC 1011 0110 CCCC CCCC
OBJMODE RPT X 1 1
CYC 1 1 1
XAR0 to XAR7, 32-bit auxiliary registers 8-bit immediate constant value Load XARn with the 8-bit unsigned immediate value: XARn = 0:8bit;
Description
None
MOVB XAR0, #F2h ; Load XAR0 with 0x0000 00F2
Example
6-200
MOVDL XT,loc32
MOVDL XT,loc32 SYNTAX OPTIONS MOVDL XT,loc32 Operands

XT loc32
Store XT and Load New XT OPCODE

1010 0110 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Multiplicand register Addressing mode (see Chapter 5)

Note: For this operation, register-addressing modes cannot be used. The modes are: @XARn, @ACC, @P, @XT. An illegal instruction trap will be generated.
Description
Load the XT register with the 32-bit content of the location pointed to by the loc32 addressing mode and then load the next highest 32-bit location pointed to by loc32 with the content of XT:
XT = [loc32]; [loc32 + 2] = XT;
None
This instruction is repeatable. If this instruction follows the RPT instruction, then it will be executed N+1 times.
; Calculate using 32-bit multiply, retaining high result: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 ZAPA ; Zero ACC, P, OVC MOVL XT,@X2 ; XT = X2 QMPYL P,XT,@C2 ; P = XT*C2 MOVDL XT,@X1 ; XT = X1, X2 = X1 QMPYAL P,XT,@C1 ; P = XT*C1, ACC = X2*C2>>2 MOVDL XT,@X0 ; XT = X0, X1 = X0 QMPYAL P,XT,@C0 ; P = XT*C0, ACC = X1*C1>>2 + X2*C2>>2 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
Example
6-201
MOVH loc16,ACC << 1..8
MOVH loc16,ACC << 1..8 SYNTAX OPTIONS MOVH loc16, ACC << 1 MOVH loc16, ACC << 2..8
Save High Word of Shifted Accumulator OPCODE

1011 0011 LLLL LLLL 0101 0110 0010 1111 0000 0SHF LLLL LLLL 1011 0SHF LLLL LLLL
OBJMODE RPT 1 1 0 Y Y
CYC N+1 N+1 1
Operands
loc16 ACC #1..8
Addressing mode (see Chapter 5) Accumulator register Shift value Load the content of the location pointed to by the loc16 addressing mode with the high word of the ACC register after leftshifting by the specified value. The ACC register is not modified:
[loc16] = ACC >> (16 shift value);
Description
Flags and Modes
If (loc16 = @AX), then after the load AX is checked for a negative condition. The N flag is set if bit 15 of the AX is 1; else N is cleared. If (loc16 = @AX) then after the load AX is checked for a zero condition. The Z flag is set if AX is zero; else Z is cleared. If the operation is repeatable, then the instruction will be executed N+1 times. The state of the Z and N flags will reflect the final result. If the operation is not repeatable, the instruction will execute only once.
Repeat
Example
; Multiply two Q15 numbers (VarA and VarB) and store result in ; VarC as a Q15 number: MOV T,@VarA ; T = VarA (Q15) MPY ACC,T,@VarB ; ACC = VarA * VarB (Q30) MOVH @VarC,ACC << 1 ; VarC = ACC >> (161) (Q15) ; VarC as a Q31 number: MOV T,@VarA ; T = VarA (T = Q14) MPY ACC,T,@VarB ; ACC = VarA * VarB (ACC = Q28) MOV @VarC+0,ACC << ; VarC low = ACC << 3 3 MOVH @VarC+1,ACC << ; VarC high = ACC >> (161) (VarC = Q31) 3
6-202
MOVH loc16, P
MOVH loc16, P SYNTAX OPTIONS MOVH loc16,P Operands

loc16 P
Save High Word of the P Register OPCODE

0101 0111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Addressing mode (see Chapter 5) Product register The contents of the P register are shifted by the amount specified in the product shift mode (PM), and the upper half of the shifted value is stored into the 16-bit location pointed to by the loc16 addressing mode. The P register is not modified by the operation:
[loc16] = (P << PM) >> 16;
Description
Flags and Modes
If (loc16 = @AX) and bit 15 of the AX register is 1, then the N bit is set; otherwise, N is cleared. If (loc16 = @AX) and the value of AX after the load is zero, then the Z bit is set; otherwise Z is cleared. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, and N flags will reflect the final result.
PM
Repeat
Example
; Calculate Y32 = M16*X16 >> 6 MOV T,@M16 ; T = M MPY P,T,@X16 ; P = T * X SPM 6 ; Set product shift to >> 6 MOV @Y32+0,P ; Y32 = P >> 6 MOVH @Y32+1,P
6-203
MOVL ACC,loc32
MOVL ACC,loc32 SYNTAX OPTIONS MOVL ACC,loc32 Operands

ACC loc32 Accumulator register Addressing mode (see Chapter 5)
Load Accumulator With 32 Bits OPCODE

0000 0110 LLLL LLLL
OBJMODE RPT X
CYC 1
Description
Load the ACC register with the content of the location pointed to by the loc32 addressing mode.
ACC = [loc32];
Flags and Modes
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
After the load, the Z flag is set if the ACC is zero, else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
Calculate the 32-bit value: VarC = VarA + VarB; MOVL ACC,@VarA ; Load ACC with contents of VarA ADDL ACC,@VarB ; Add to ACC the contents of VarB MOVL @VarC,ACC ; Store result into VarC
6-204
MOVL ACC,P << PM
MOVL ACC,P << PM SYNTAX OPTIONS MOVL ACC,P << PM
Load the Accumulator With Shifted P OPCODE

0001 0110 1010 1100
OBJMODE RPT X
CYC 1
Note: This instruction is an alias for the MOVP T,loc16 operation with loc16 = @T addressing mode.
Operands
ACC P << PM
Accumulator register Product register Product shift mode Load the ACC register with the content of the P register shifted as specified by the product shift mode (PM):
ACC = P << PM;
Description
Flags and Modes
After the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the load, the Z flag is set if the ACC is zero, else Z is cleared. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z PM
Repeat
Example
; Calculate: Y = Y + (M*X >> 4) ; Y is a 32-bit value, M and X are 16-bit values SPM 4 ; Set product shift to >> 4 MOV T,@M ; T = M MPY P,T,@X ; P = M * X MOVL ACC,P << PM ; ACC = M*X >> 4 ADDL @Y,ACC ; Y = Y + ACC
6-205
MOVL loc32, ACC
MOVL loc32, ACC SYNTAX OPTIONS MOVL loc32, ACC Operands

ACC loc32
Store 32-bit Accumulator OPCODE

0001 1110 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Addressing mode (see Chapter 5) Store the contents of the ACC register into the location pointed to by the loc32 addressing mode:
[loc32] = ACC;
Description
Flags and Modes
If (loc32 = @ACC) then after the load, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If (loc32 = @ACC) then after the load, the Z flag is set if ACC is zero, else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
Calculate the 32-bit value: VarC = VarA + VarB; MOVL ACC,@VarA ; Load ACC with contents of VarA ADDL ACC,@VarB ; Add to ACC the contents of VarB MOVL @VarC,ACC ; Store result into VarC
6-206
MOVL loc32,ACC,COND
MOVL loc32,ACC,COND SYNTAX OPTIONS MOVL loc32,ACC,COND

Operands loc32 ACC COND
Conditionally Store the Accumulator OPCODE

0101 0110 0100 1000 0000 COND LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Accumulator register Conditional codes:

COND 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Syntax Description Flags Tested
NEQ EQ GT GEQ LT LEQ HI HIS, C LOS NOV OV NTC TC NBIO UNC
Not Equal To Equal To Greater Then Greater Then Or Equal To Less Then Less Then Or Equal To Higher Higher Or Same, Carry Set Lower Or Same No Overflow Overflow Test Bit Not Set Test Bit Set BIO Input Equal To Zero Unconditional
Z=0 Z=1 Z = 0 AND N = 0 N=0 N=1 Z = 1 OR N = 1 C = 1 AND Z = 0 C=1 C=0 C = 0 OR Z = 1 V=0 V=1 TC = 0 TC = 1 BIO = 0
LO, NC Lower, Carry Clear
Description
If the specified condition being tested is true, then the location pointed to by the loc32 addressing mode will be loaded with the contents of the ACC register:
if(COND = true) [loc32] = ACC; Note: Addressing modes are not conditionally executed. Hence, if an addressing mode performs a pre or post modification, the modification will occur regardless of whether the condition is true or not.
6-207
MOVL loc32,ACC,COND
Flags and Modes
If (COND = true AND loc32 = @ACC), then after the move if bit 31 of ACC is 1, N is set; otherwise N cleared. If (COND = true AND loc32 = @ACC), then after the move if (ACC = 0), then the Z bit is set; otherwise it is cleared. If the V flag is tested by the condition, then V is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Swap the contents of 32-bit VarA and VarB if VarB is higher: MOVL ACC,@VarB ; ACC = VarB MOVL P,@VarA ; P = VarA CMPL ACC,@P ; Set flags on (VarB VarA) MOVL @VarA,ACC,HI ; VarA = ACC if higher MOVL @P,ACC,HI ; P = ACC if higher MOVL @VarA,P ; VarA = P
6-208
MOVL loc32,P
MOVL loc32,P SYNTAX OPTIONS MOVL loc32,P Operands

loc32 P
Store the P Register OPCODE

1010 1001 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Product register Store the P register contents into the location pointed to by the loc32 addressing mode:
[loc32] = P;
Description
Flags and Modes
If (loc32 = @ACC) and bit 31 of the ACC register is 1, then the N bit is set; otherwise, N is cleared. If (loc32 = @ACC) and the value of ACC after the load is zero, then the Z bit is set; otherwise Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Add MOVL MOVL ADDUL ADDCL ADDUL ADDCL MOVL MOVL
64-bit VarA, VarB and VarC, and store result in VarD: P,@VarA+0 ; Load P with low 32 bits of VarA ACC,@VarA+2 ; Load ACC with high 32 bits of VarA P,@VarB+0 ; Add to P unsigned low 32 bits of VarB ACC,@VarB+2 ; Add to ACC with carry high 32 bits of VarB P,@VarC+0 ; Add to P unsigned low 32 bits of VarC ACC,@VarC+2 ; Add to ACC with carry high 32 bits of VarC @VarD+0,P ; Store low 32-bit result into VarD @VarD+2,ACC ; Store high 32-bit result into VarD
6-209
MOVL loc32, XARn
MOVL loc32, XARn SYNTAX OPTIONS MOVL loc32, XAR0 MOVL loc32, XAR1 MOVL loc32, XAR2 MOVL loc32, XAR3 MOVL loc32, XAR4 MOVL loc32, XAR5 MOVL loc32, XAR6 MOVL loc32, XAR7 Operands
loc32 XARn
Store 32-bit Auxiliary Register OPCODE

0011 1010 LLLL LLLL 1011 0010 LLLL LLLL 1010 1010 LLLL LLLL 1010 0010 LLLL LLLL 1010 1000 LLLL LLLL 1010 0000 LLLL LLLL 1100 0010 LLLL LLLL 1100 0011 LLLL LLLL
OBJMODE RPT 1 1 1 1 1 1 X X
CYC 1 1 1 1 1 1 1 1
Addressing mode (see Chapter 5) XAR0 to XAR7, 32-bit auxiliary registers Load the contents of the 32-bit addressed location with the contents of XARn:
[loc32] = XARn;
Description
Flags and Modes
If (loc32 = @ACC), then the load to ACC is tested for a negative condition. Bit-31 of the ACC register is the sign bit, 0 for positive, 1 for negative. The negative flag bit is set if the operation on the ACC register generates a negative value, otherwise it is cleared. If (loc32 = @ACC), then the load to ACC is tested for a zero condition. The bit is set if the result of the operation on the ACC register generates a 0 value, otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
MOVL
@ACC, XAR0
MOVL MOVL
*XAR1, XAR7 *XAR6++,XAR6
MOVL
*XAR5,XAR5
; ; ; ; ; ; ; ; ; ; ;
Move the 32-bit contents of XAR0 into ACC. If bit 31 of the ACC is 1 set N. If ACC = 0, set Z. Move the 32-bit contents of XAR7 into the location pointed to by XAR1. Move the 32-bit contents of XAR6 into the location pointed to by XAR6. Post-increment the contents of XAR6. Predecrement the contents of XAR5. Move the 32-bit contents of XAR5 into the location pointed to by ; XAR5.
6-210
MOVL loc32,XT
MOVL loc32,XT SYNTAX OPTIONS MOVL loc32,XT Operands

loc32 XT
Store the XT Register OPCODE

1010 1011 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Multiplicand register Store the XT register into 32-bit location pointed to by the loc32 addressing mode:
[loc32] = XT;
Description
Flags and Modes
N Z
If (loc32 = @ACC) and bit 31 of the ACC register is 1, then the N bit is set; otherwise, N is cleared. If (loc32 = @ACC) and the value of ACC after the load is zero, then the Z bit is set; otherwise Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate using 32-bit multiply, retaining high result: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 ZAPA ; Zero ACC, P, OVC MOVL XT,@X2 ; XT = X2 QMPYL P,XT,@C2 ; P = XT*C2 MOVL XT,@X1 ; XT = X1, ACC = X2*C2 >> 2 QMPYAL P,XT,@C1 ; P = XT*C1 MOVL @X2,XT ; X2 = X1 MOVL XT,@X0 ; XT = X0, ACC = X1*C1 >> 2 + X2*C2 >> 2 QMPYAL P,XT,@C0 ; P = XT*C0 MOVL @X1,XT ; X1 = X0 ADDL ACC,P << PM ; ACC = X0*C0 >> 2 + X1*C1 >> 2 + X2*C2 >> 2 MOVL @Y,ACC ; Store result into Y
6-211
MOVL P,ACC
MOVL P,ACC SYNTAX OPTIONS MOVL P,ACC Operands

P ACC
Load P From the Accumulator OPCODE

1111 1111 0101 1010
OBJMODE RPT X
CYC 1
Product register Accumulator register Load the P register with the content of the ACC register:
P = ACC;
Description
None
Calculate the 32-bit value: VarC = abs(VarA) + abs(VarB) MOVL ACC,@VarA ; Load ACC with contents of VarA ABS ACC ; Take absolute value of VarA MOVL P,ACC ; Temp save ACC in P register MOVL ACC,@VarB ; Load ACC with contents of VarB ABS ACC ; Take absolute value of VarB ADDL ACC,@P ; Add contents of P to ACC MOVL @VarC,ACC ; Store result into VarC
Example
6-212
MOVL P,loc32
MOVL P,loc32 SYNTAX OPTIONS MOVL P,loc32 Operands

P loc32
Load the P Register OPCODE

1010 0011 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Addressing mode (see Chapter 5) Load the P register with the 32-bit location pointed to by the loc32 addressing mode:
P = [loc32];
Description
None
; Add MOVL MOVL ADDUL ADDCL ADDUL ADDCL MOVL MOVL 64-bit VarA, VarB and VarC, and store result in VarD: P,@VarA+0 ; Load P with low 32 bits of VarA ACC,@VarA+2 ; Load ACC with high 32 bits of VarA P,@VarB+0 ; Add to P unsigned low 32 bits of VarB ACC,@VarB+2 ; Add to ACC with carry high 32 bits of VarB P,@VarC+0 ; Add to P unsigned low 32 bits of VarC ACC,@VarC+2 ; Add to ACC with carry high 32 bits of VarC @VarD+0,P ; Store low 32-bit result into VarD @VarD+2,ACC ; Store high 32-bit result into VarD
Example
6-213
MOVL XARn, loc32
MOVL XARn, loc32 SYNTAX OPTIONS MOVL XAR0, loc32 MOVL XAR1, loc32 MOVL XAR2, loc32 MOVL XAR3, loc32 MOVL XAR4, loc32 MOVL XAR5, loc32 MOVL XAR6, loc32 MOVL XAR7, loc32 Operands
XARn loc32
Load 32-bit Auxiliary Register OPCODE

1000 1110 LLLL LLLL 1000 1011 LLLL LLLL 1000 0110 LLLL LLLL 1000 0010 LLLL LLLL 1000 1010 LLLL LLLL 1000 0011 LLLL LLLL 1100 0100 LLLL LLLL 1100 0101 LLLL LLLL
CYC 1 1 1 1 1 1 1 1
XAR0 to XAR7, 32-bit auxiliary registers Addressing mode (see Chapter 5) Load XARn with the contents of the 32-bit addressed location:
XARn = [loc32];
Description
None
MOVL MOVL XAR0,@ACC XAR2,*XAR0++ ; ; ; ; ; ; ; ; ; ; ; Move the 32-bit contents of ACC into XAR0 Move the 32-bit value pointed to by XAR0 into XAR2. Post increment XAR0 by 2 Move the 32-bit value pointed to by XAR3 into XAR3. Address modification of XAR3 is ignored. Predecrement the contents of XAR4. Move the 32-bit value pointed to by XAR4 into XAR4.
Example
MOVL
XAR3,*XAR3++
MOVL
XAR4,*XAR4
6-214
MOVL XARn, #22bit
MOVL XARn, #22bit SYNTAX OPTIONS MOVL XAR0, #22bit MOVL XAR1, #22bit MOVL XAR2, #22bit MOVL XAR3, #22bit MOVL XAR4, #22bit MOVL XAR5, #22bit MOVL XAR6, #22bit MOVL XAR7, #22bit Operands
XARn #22bit
Load 32-bit Auxiliary Register With Constant Value OPCODE

1000 1101 00CC CCCC CCCC CCCC CCCC CCCC 1000 1101 01CC CCCC CCCC CCCC CCCC CCCC 1000 1101 10CC CCCC CCCC CCCC CCCC CCCC 1000 1101 11CC CCCC CCCC CCCC CCCC CCCC 1000 1111 00CC CCCC CCCC CCCC CCCC CCCC 1000 1111 01CC CCCC CCCC CCCC CCCC CCCC 0111 0110 10CC CCCC CCCC CCCC CCCC CCCC 0111 0110 11CC CCCC CCCC CCCC CCCC CCCC
OBJMODE 1 1 1 1 1 1 X X
RPT
CYC 1 1 1 1 1 1 1 1
XAR0 to XAR7, 32-bit auxiliary registers 22-bit immediate constant value Load XARn with a 22-bit unsigned constant:
XARn = 0:22bit;
Description
None
MOVL XAR4,#VarA ; Initialize XAR4 pointer with the ; 22-bit address of VarA
Example
6-215
MOVL XT,loc32
MOVL XT,loc32 SYNTAX OPTIONS MOVL XT, loc32 Operands

T loc32
Load the XT Register OPCODE

1000 0111 LLLL LLLL
OBJMODE RPT 1
CYC 1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the XT register with the 32-bit content of the location pointed to by the loc32 addressing mode:
Description
XT = [loc32];
None
; Calculate using 32-bit multiply, retaining high result: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 ZAPA ; Zero ACC, P, OVC MOVL XT,@X2 ; XT = X2 QMPYL P,XT,@C2 ; P = XT*C2 MOVL XT,@X1 ; XT = X1, ACC = X2*C2 >> 2 QMPYAL P,XT,@C1 ; P = XT*C1 MOVL @X2,XT ; X2 = X1 MOVL XT,@X0 ; XT = X0, ACC = X1*C1 >> 2 + X2*C2 >> 2 QMPYAL P,XT,@C0 ; P = XT*C0 MOVL @X1,XT ; X1 = X0 ADDL ACC,P << PM ; ACC = X0*C0 >> 2 + X1*C1 >> 2 + X2*C2 >> 2 MOVL @Y,ACC ; Store result into Y
Example
6-216
MOVP T,loc16
MOVP T,loc16 SYNTAX OPTIONS MOVP T,loc16 Operands

T loc16
Load the T Register and Store P in the Accumulator OPCODE

0001 0110 LLLL LLLL
OBJMODE RPT X
CYC 1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the T register with the 16-bit content of the location pointed to by the loc16 addressing mode. Also, the content of the P register, shifted by the amount specified by the product shift mode (PM) bits, is loaded into the ACC register:
T = [loc16]; ACC = P << PM;
Description
Flags and Modes
After the operation if bit 31 of the ACC register is 1, then the N bit is set; otherwise, N is cleared. After the operation, if the value of ACC is zero, then the Z bit is set; otherwise Z is cleared. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
PM
Repeat
Example
6-217
MOVS T,loc16
MOVS T,loc16 SYNTAX OPTIONS MOVS, T,loc16 Operands

T loc16
Load T and Subtract P From the Accumulator OPCODE

0001 0001 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Upper 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the T register with the 16-bit content of the location pointed to by the loc16 addressing mode. Also, the content of the P register, shifted by the amount specified by the product shift mode (PM) bits, is subtracted from the content of the ACC register:
T = [loc16]; ACC = ACC P << PM;
Description
Flags and Modes
After the operation, if bit 31 of the ACC register is 1, then the N bit is set; otherwise, N is cleared. After the operation, if the value of ACC is zero, then the Z bit is set; otherwise Z is cleared. If the subtraction generates a borrow, the C bit is cleared; otherwise, C is set. If an overflow occurs, V is set; otherwise V is not affected If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflows. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
C V OVC
OVM
PM
Repeat
6-218
MOVS T,loc16
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 MOVP T,@X2 ; T = X2 MPYS P,T,@C2 ; P = T*C2, ACC = 0 MOVS T,@X1 ; T = X1, ACC = X2*C2 >> 2 MPY P,T,@C1 ; P = T*C1 MOV @X2,T ; X2 = X1 MOVA T,@X0 ; T = X0, ACC = X1*C1 >> 2 X2*C2 >> 2 MPY P,T,@C0 ; P = T*C0 MOV @X1,T ; X1 = X0 SUBL ACC,P << PM ; ACC = X0*C0 >> 2 X1*C1 >> 2 X2*C2 >> 2 MOVL @Y,ACC ; Store result into Y
6-219
MOVU ACC,loc16
MOVU ACC,loc16 SYNTAX OPTIONS MOVU ACC,loc16 Operands

ACC loc16
Load Accumulator With Unsigned Word OPCODE

0000 1110 LLLL LLLL
OBJMODE X
RPT
CYC 1
Accumulator register Addressing mode (see Chapter 5) Load the low half of the accumulator (AL) with the 16-bit contents of the addressed location pointed to by the loc16 addressing mode and fill the high half of the accumulator (AH) with 0s:
AL = [loc16]; AH = 0x0000;
Description
Flags and Modes
Clear flag. After the load, the Z flag is set if the ACC value is zero, else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Add MOVU ADD << 16 ADDU ADD << 16 ADDCU ADD << 16
three 32-bit unsigned variables by 16-bit parts: ACC,@VarAlow ; AH = 0, AL = VarAlow ACC,@VarAhigh ; AH = VarAhigh, AL = VarAlow ACC,@VarBlow ACC,@VarBhigh ACC,@VarClow ACC,@VarChigh ; ACC = ACC + 0:VarBlow ; ACC = ACC + VarBhigh << 16 ; ACC = ACC + VarClow + Carry ; ACC = ACC + VarChigh << 16
6-220
MOVU loc16,OVC
MOVU loc16,OVC SYNTAX OPTIONS MOVU loc16,OVC
Store the Unsigned Overflow Counter OPCODE

0101 0110 0010 1000 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
loc16 OVC
Addressing mode (see Chapter 5) Overflow counter Store the 6 bits of the overflow counter (OVC) into the lower 6 bits of the location pointed to by the loc16 addressing mode and zero the upper 10 bits of the addressed location:
[loc16(15:6)] [loc16(5:0)] = 0; = OVC;
Description
Flags and Modes
If (loc16 = @AX) and bit 15 of AX is 1, then set N; otherwise clear N. If (loc16 = @AX) and AX is zero, then set Z; otherwise clear Z. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Save MOVU MOV MOV . . . . MOV MOV MOVU
and restore contents of ACC and OVC bits: *SP++,OVC ; Save OVC on stack *SP++,AL ; Save AL on stack *SP++,AH ; Save AH on stack
AH,*SP AL,*SP OVC,*SP
; Restore AH from stack ; Restore AL from stack ; Restore OVC from stack
6-221
MOVU OVC,loc16
MOVU OVC,loc16 SYNTAX OPTIONS MOVU OVC,loc16
Load Overflow Counter With Unsigned Value OPCODE

0101 0110 0110 0010 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
OVC
6-bit overflow counter Load the overflow counter (OVC) with the lower 6 bits of the location pointed to by the loc16 addressing mode:
OVC = [loc16(5:0)]
OVC
The 6-bit overflow counter is modified.
; Save MOVU MOV MOV . . . . MOV MOV MOVU and restore contents of ACC and OVC bits: *SP++,OVC ; Save OVC on stack *SP++,AL ; Save AL on stack *SP++,AH ; Save AH on stack
Example
AH,*SP AL,*SP OVC,*SP
; Restore AH from stack ; Restore AL from stack ; Restore OVC from stack
6-222
MOVW DP, #16bit
MOVW DP, #16bit SYNTAX OPTIONS MOVW DP, #16bit OPCODE

Load the Entire Data Page OBJMODE RPT X CYC 1
Operands
DP #16bit
Data page register 16-bit immediate constant value Load the data page register with a 16-bit constant:
DP(15:0) = 16bit;
Description
None
MOVW DP, #VarA ; ; ; ; Load DP with the data page that contains VarA. Assumes VarA is in the lower 0x003F FFC0 of memory Load DP with data page number 0xF012
Example
MOVW
DP, #0F012h
6-223
MOVX TL,loc16
MOVX TL,loc16 SYNTAX OPTIONS MOVX TL,loc16 Operands

TL loc16
Load Lower Half of XT With Sign Extension OPCODE

OBJMODE RPT 1
CYC 1
Lower 16 bits of the multiplicand register (XT) Addressing mode (see Chapter 5) Load the lower 16 bits of the multiplicand register (TL) with the 16-bit contents of the location pointed to by the loc16 addressing mode and then sign extend that value into the upper upper 16 bits of XT:
TL = [loc16]; T = sign extension of TL;
Description
None
; Calculate and keep low 32-bit result: Y32 = M32*X16 MOVX TL,@X16 ; XT = S:X16 IMPYL P,XT,@M32 ; P = XT * M32 (low 32 bits of result) MOVL @Y32,P ; Store result into Y32
Example
6-224
MOVZ ARn, loc16
MOVZ ARn, loc16
Load Lower Half of XARn and Clear Upper Half OBJMODE X 1 1
SYNTAX OPTIONS MOVZ AR05, loc16 MOVZ AR6, loc16 MOVZ AR7, loc16 Operands
ARn loc16
OPCODE 0101 1nnn LLLL LLLL 1000 1000 LLLL LLLL 1000 0000 LLLL LLLL
RPT
CYC 1 1 1
AR0 to AR7, lower 16 bits of auxiliary registers Addressing modes (See chapter 5) Load ARn with the contents of the 16-bit location and clear ARnH:
ARn = [loc16]; ARnH = 0;
Description
None
MOVL XAR7, #ArrayA MOVZ AR0, *+XAR2[0] MOVZ AR7, *SP[1] ; ; ; ; ; Initialize XAR2 pointer Load 16-bit value pointed to by XAR2 into AR0. XAR0(31:16) = 0. Load the first 16-bit value off of the stack into AR7. XAR7(31:16) = 0.
Example
6-225
MOVZ DP, #10bit
MOVZ DP, #10bit SYNTAX OPTIONS MOVZ DP, #10bit Operands

DP #10bit
Load Data Page and Clear High Bits OPCODE

1011 10CC CCCC CCCC
OBJMODE RPT 1
CYC 1
Data page register 10-bit immediate constant value Load the data page register with a 10-bit constant and clear the upper 6 bits:
DP(9:0) = 10bit; DP(15:10) = 0;
Description
None
MOVZ DP, #VarA ; ; ; ; Load DP with the data page that contains VarA. Assumes VarA is in the lower 0x0000 FFC0 of memory Load DP with page number 0x03FF.
Example
MOVZ
DP, #3FFh
6-226
MPY ACC,loc16, #16bit
MPY ACC,loc16, #16bit SYNTAX OPTIONS MPY ACC, loc16,#16bit OPCODE

0011 0100 LLLL LLLL CCCC CCCC CCCC CCCC Accumulator register
16 X 16-bit Multiply OBJMODE RPT X CYC 1
Operands
ACC loc16
Addressing mode (see Chapter 5) 16-bit immediate constant value
Description
Load the T register with the 16-bit content of the location pointed to by the loc16 addressing mode; then, multiply the signed 16-bit content of the T register by the specified signed 16-bit constant value:
T = [loc16]; ACC = signed T * signed 16bit;
Flags and Modes
After the operation, the Z flag is set if the ACC is zero, else Z is cleared. After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate signed using 16-bit multiply: ; Y32 = Y32 + X16 * 2000 MPY ACC,@X16,#2000 ; T = X16, ACC = X16 * 2000 ADDL @Y32,ACC ; Y32 = Y32 + ACC
6-227
MPY ACC, T, loc16
MPY ACC, T, loc16 SYNTAX OPTIONS MPY ACC,T,loc16 Operands

ACC T loc16
16 X 16-bit Multiply OPCODE

0001 0010 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the loc16 addressing mode and store the result in the ACC register:
ACC = signed T * signed [loc16];
Description
Flags and Modes
Repeat
Example
; Calculate signed using ; Y32 = Y32 + X16*M16 MOV T,@X16 ; MPY ACC,T,@M16 ; ADDL @Y32,ACC ;
16-bit multiply: T = X16 ACC = T * M16 Y32 = Y32 + ACC
6-228
MPY P,loc16,#16bit
MPY P,loc16,#16bit SYNTAX OPTIONS MPY P,loc16,#16bit OPCODE

16 X 16-Bit Multiply OBJMODE RPT 1 CYC 1
Operands
P loc16 #16bit
Product register Addressing mode (see Chapter 5) 16-bit immediate constant value Multiply the signed 16-bit contents of the location pointed to by the loc16 addressing mode by the 16-bit immediate value and store the 32-bit result in the P register:
P = signed [loc16] * signed 16bit;
Description
None
; ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2), ; C0, C1 and C2 are constants SPM 2 ; Set product shift to >> 2 MOVB ACC,#0 ; Zero ACC MPY P,@X2,#C2 ; P = X2*C2 MPYA P,@X1,#C1 ; ACC = X2*C2>>2, P = X1*C1 MPYA P,@X0,#C0 ; ACC = X1*C1>>2 + X2*C2>>2, P = X0*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
Example
6-229
MPY P,T,loc16
MPY P,T,loc16 SYNTAX OPTIONS MPY P,T,loc16 Operands

P T loc16
16 X 16 Multiply OPCODE
0011 0011 LLLL LLLL
OBJMODE RPT X
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the loc16 addressing mode and store the 32-bit result in the P register:
P = signed T * signed [loc16];
Description
None
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 SPM 2 ; Set product shift to >> 2 MOVP T,@X2 ; T = X2 MPYS P,T,@C2 ; P = T*C2, ACC = 0 MOVAD T,@X1 ; T = X1, ACC = X2*C2>>2, X2 = X1 MPY P,T,@C1 ; P = T*C1 MOVAD T,@X0 ; T = X0, ACC = X1*C1>>2 + X2*C2>>2, X1 = X0 MPY P,T,@C0 ; P = T*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
Example
6-230
MPYA P,loc16,#16bit
MPYA P,loc16,#16bit SYNTAX OPTIONS MPYA P,loc16,#16bit Operands

P loc16 #16bit
16 X 16-Bit Multiply and Add Previous Product OPCODE

OBJMODE RPT X
CYC 1
Product register Addressing mode (see Chapter 5) 16-bit immediate constant value Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM) bits, to the ACC register. Load the T register with the content of the location pointed to by the loc16 addressing mode. Multiply the signed 16-bit content of the T register by the signed 16-bit constant value and store the 32-bit result in the P register:
ACC = ACC + P << PM; T = [loc16]; P = signed T * signed 16bit;
Description
Flags and Modes
After the operation, the Z flag is set if the ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
N C V OVC
OVM
PM
Repeat
6-231
MPYA P,loc16,#16bit
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2), ; C0, C1 and C2 are constants SPM 2 ; Set product shift to >> 2 MOVB ACC,#0 ; Zero ACC MPY P,@X2,#C2 ; P = X2*C2 MPYA P,@X1,#C1 ; ACC = X2*C2>>2, P = X1*C1 MPYA P,@X0,#C0 ; ACC = X1*C1>>2 + X2*C2>>2, P = X0*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
6-232
MPYA P,T,loc16
MPYA P,T,loc16 SYNTAX OPTIONS MPYA P,T,loc16 Operands

P T loc16
16 X 16-bit Multiply and Add Previous Product OPCODE

0001 0111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Product register Multiplicand register Addressing mode (see Chapter 5) Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. Multiply the signed 16-bit content of T by the signed 16-bit content of the location pointed to by the loc16 addressing mode and store the 32-bit result in the P register:
ACC = ACC + P << PM; P = signed T * signed [loc16];
Description
Flags and Modes
After the operation, the Z flag is set if the ACC is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
N C V OVC
OVM
PM
Repeat
6-233
MPYA P,T,loc16
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) SPM 2 ; Set product shift to >> 2 MOVP T,@X2 ; ACC = P, T = X2 MPYS P,T,@C2 ; ACC = ACC P = 0, P = T*C2 MOV T,@X1 ; T = X1 MPYA P,T,@C1 ; ACC = X2*C2>>2, P = T*C1 MOV T,@X0 ; T = X0 MPYA P,T,@C0 ; ACC = X1*C1>>2 + X2*C2>>2, P = T*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
6-234
MPYB ACC,T,#8bit
MPYB ACC,T,#8bit SYNTAX OPTIONS MPYB ACC,T,#8bit Operands

ACC T #8bit
Multiply by 8-bit Constant
OPCODE
0011 0101 CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator register Multiplicand register 8-bit immediate constant value Multiply the signed 16-bit content of the T register by the unsigned 8-bit constant value zero extended and store the result in the ACC register:
ACC = signed T * 0:8bit
Description
Flags and Modes
Repeat
Example
; Calculate signed using 16-bit multiply: ; Y32 = Y32 + (X16 * 5) MOV T,@X16 ; T = X16 MPYB ACC,T,#5 ; ACC = T * 5 ADDL @Y32,ACC ; Y32 = Y32 + ACC
6-235
MPYB P,T,#8bit
MPYB P,T,#8bit SYNTAX OPTIONS MPYB P,T,#8bit Operands

P T #8bit
Multiply Signed Value by Unsigned 8-bit Constant OPCODE

0011 0001 CCCC CCCC
OBJMODE RPT X
CYC 1
Product register Multiplicand register 8-bit immediate constant value Multiply the signed 16-bit content of the T register by the unsigned 8-bit immediate constant value zero extended and store the 32-bit result in the P register:
P = signed T * 0:8bit;
Description
None
; Calculate: Y32 = X16 * 5; MOV T,@X16 ; T = X16 MPYB P,T,#5 ; P = T * #5 MOVL @Y,P ; Store result into Y32
Example
6-236
MPYS P,T,loc16
MPYS P,T,loc16 SYNTAX OPTIONS MPYS P,T,loc16 Operands

P T loc16
16 X 16-bit Multiply and Subtract OPCODE

0001 0011 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Product register Multiplicand register Addressing mode (see Chapter 5) Subtract the previous product (stored in the P register), shifted as specified by the product shift mode (PM), from the ACC register. In addition, multiply the signed 16-bit content of the T register by the signed 16-bit constant value and store the result in the P register:
ACC = ACC P << PM; P = signed T * signed [loc16];
Description
Flags and Modes
After the operation, the Z flag is set if the ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
C V OVC
OVM
PM
Repeat
6-237
MPYS P,T,loc16
Example
; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) SPM 2 ; Set product shift to >> 2 MOVP T,@X2 ; ACC = P, T = X2 MPYS P,T,@C2 ; ACC = ACC P = 0, P = T*C2 MOV T,@X1 ; T = X1 MPYA P,T,@C1 ; ACC = X2*C2>>2, P = T*C1 MOV T,@X0 ; T = X0 MPYA P,T,@C0 ; ACC = X1*C1>>2 + X2*C2>>2, P = T*C0 ADDL ACC,P << PM ; ACC = X0*C0>>2 + X1*C1>>2 + X2*C2>>2 MOVL @Y,ACC ; Store result into Y
6-238
MPYU P,T,loc16
MPYU P,T,loc16 SYNTAX OPTIONS MPYU P,T,loc16 Operands

P T loc16
Unsigned 16 X 16 Multiply OPCODE

0011 0111 LLLL LLLL
OBJMODE RPT X
CYC 1
P = unsigned T * unsigned [loc16];
Description
None
; Calculate unsigned value: Y32 = X16 * M16; MOV T,@X16 ; T = X16 MPYU P,T,@M16 ; P = T * M16 MOVL @Y,P ; Store result into Y32
Example
6-239
MPYU ACC,T,loc16
MPYU ACC,T,loc16 SYNTAX OPTIONS MPYU ACC,T,loc16 Operands

ACC T loc16
16 X 16-bit Unsigned Multiply OPCODE

0011 0110 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Multiplicand register Addressing mode (see Chapter 5) Multiply the unsigned 16-bit content of the T register by the unsigned 16-bit content of the location pointed to by the loc16 addressing mode and store the 32-bit results in the ACC register:
ACC = unsigned T * unsigned [loc16];
Description
Flags and Modes
Repeat
Example
; Calculate unsigned using 16-bit multiply: ; Y32 = Y32 + X16*M16 MOV T,@X16 ; T = X16 MPYU ACC,T,@M16 ; ACC = T * M16 ADDL @Y32,ACC ; Y32 = Y32 + ACC
6-240
MPYXU ACC, T, loc16
MPYXU ACC, T, loc16 SYNTAX OPTIONS MPYXU ACC, T, loc16 Operands

ACC T loc16
Multiply Signed Value by Unsigned Value OBJMODE RPT

0011 0000 LLLL LLLL
CYC 1
Accumulator register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 16-bit content of the T register by the unsigned 16-bit content of the location pointed to by the loc16 addressing mode and store the result in the ACC register:
ACC = signed T * unsigned [loc16];
Description
Flags and Modes
Repeat
Example
; Calculate signed using 16-bit multiply: ; Y32 = Y32 + (signed) X16 * (unsigned) M16 MOV T,@X16 ; T = X16 MPYXU ACC,T,@M16 ; ACC = T * M16 ADDL @Y32,ACC ; Y32 = Y32 + ACC
6-241
MPYXU P,T,loc16
MPYXU P,T,loc16 SYNTAX OPTIONS MPYXU P,T,loc16 Operands

P T loc16
Multiply Signed Value by Unsigned Value OPCODE

0011 0010 LLLL LLLL
OBJMODE RPT X
CYC 1
P = signed T * unsigned [loc16];
Description
None
; Calculate Y32 = X32 MOV T,@X32+0 MPYU ACC,T,@M32+0 MOV @Y32+0,AL MOVU ACC,@AH MOV T,@X32+1 MPYXU P,T,@M32+0 MOVA T,@M32+1 MPYXU P,T,@X32+0 ADDL ACC,@P MOV @Y32+1,AL * ; ; ; ; ; ; ; ; ; ; M32 by parts using 16-bit multiply: T = unsigned low X32 ACC = T * unsigned low M32 Store low result into Y32 Logical shift right ACC by 16 T = signed high X32 ACC = T * low unsigned M32 T = signed high M32, ACC += P ACC = T * low unsigned X32 Add P to ACC Store high result into Y32
Example
6-242
NASP
NASP SYNTAX OPTIONS NASP Operands Description None OPCODE

0111 0110 0001 0111
Unalign Stack Pointer OBJMODE RPT X CYC 1
If the SPA bit is 1, the NASP instruction decrements the stack pointer (SP) by 1 and then clears the SPA status bit. This undoes a stack pointer alignment performed earlier by the ASP instruction. If the SPA bit is 0, then the NASP instruction performs no operation.
if( SPA = 1 ) { SP = SP 1; SPA = 0; }
SPA
If (SPA = 1), then SPA is cleared.
; Alignment of stack pointer in interrupt service routine: ; Vector table: INTx: .long INTx; INTx interrupt vector Service . . INTxService: ASP ; Align stack pointer . . . NASP ; Realign stack pointer IRET ; Return from interrupt.
Example
6-243
NEG ACC
NEG ACC SYNTAX OPTIONS NEG ACC Operands Description

ACC
Negate Accumulator OPCODE

1111 1111 0101 0100
OBJMODE RPT X
CYC 1
Accumulator register Negate the contents of the ACC register:

if(ACC = 0x8000 0000) { V = 1; if(OVM = 1) ACC = 0x7FFF FFFF; else ACC = 0x8000 0000; } else ACC = ACC; if(ACC = 0x0000 0000) C = 1; else C = 0;
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. If (ACC = 0), set C; otherwise, clear C. If (ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value and V is set. Otherwise, V is not affected. If (ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value, and the ACC value after the operation depends on the state of OVM: If OVM is cleared, ACC will be filled with 0x8000 0000. If OVM is set ACC will be saturated to 0x7FFF FFFF. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C V
OVM
Repeat
Example
; Negate contents of VarA, make sure value is saturated: MOVL ACC,@VarA ; Load ACC with contents of VarA SETC OVM ; Turn overflow mode on NEG ACC ; Negate ACC and saturate MOVL @VarA,ACC ; Store result into VarA
6-244
NEG AX
NEG AX SYNTAX OPTIONS NEG AX Operands Description

AX
Negate AX Register OPCODE

1111 1111 0101 110A
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Replace the contents of the specified AX register with the negative of AX:
if(AX = 0x8000) { AX = 0x8000; V flag = 1; } else AX = AX; if(AX = 0x0000) C flag = 1; else C flag = 0;
Flags and Modes
After the operation, if bit 15 of AX is 1, then the negative flag bit is set; otherwise, it is cleared. After the operation, if AX is 0, then the Z bit is set, otherwise it is cleared. If AX is 0, C is set; otherwise, it is cleared. If AX is 0x8000 at the start of the operation, then this is considered an overflow and V is set. Otherwise V is not affected. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C V
Repeat
Example
; Take the absolute value of VarA: MOV AL,@VarA ; Load AL with contents of VarA NEG AL ; If Al = 8000h, then V = 1 SB NoOver; Branch and save AL if no overflow flow,NOV MOV ; Save 7FFF if overflow @VarA,0x7FFFh NoOverflow: MOV @VarA,AL ; Save NEG AL if no overflow
6-245
NEG64 ACC:P
NEG64 ACC:P SYNTAX OPTIONS NEG64 ACC:P Operands Description

ACC:P
Negate Accumulator Register and Product Register OPCODE

0101 0110 0101 1000
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Negate the 64-bit content of the combined ACC:P registers:
if(ACC:P = 0x8000 0000 0000 0000) { V = 1; if(OVM = 1) ACC:P = 0x7FFF FFFF FFFF FFFF; else ACC:P = 0x8000 0000 0000 0000; } else ACC:P = ACC:P; if(ACC:P = 0x0000 0000 0000 0000) C = 1; else C = 0;
Flags and Mode
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the operation, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. If (ACC:P= = 0) then the C bit is set; otherwise C is cleared. if(ACC:P = 0x8000 0000 0000 0000) then the V flag is set; otherwise, V is not modified. If at the start of the operation, ACC:P = 0x8000 0000 0000 0000, then this is considered an overflow value and the ACC:P value after the operation depends on OVM. If (OVM = 1) ACC:P is filled with its greatest positive number (0x7FFF FFFF FFFF FFFF). If (OVM = 0) then ACC:P is not modified. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
OVM
Repeat
6-246
NEG64 ACC:P
Example
; Negate the contents of the 64-bit Var64 and saturate: MOVL ACC,@Var64+2 ; Load ACC with high 32-bits of Var64 MOVL P,@Var64+0 ; Load P with low 32-bits of Var64 SETC OVM ; Enable overflow mode (saturate) NEG64 ACC:P ; Negate ACC:P with saturation MOVL @Var64+2,ACC ; Store high 32-bit result into Var64 MOVL @Var64+0,P ; Store low 32-bit result into Var64
6-247
NEGTC ACC
NEGTC ACC SYNTAX OPTIONS NEGTC ACC Operands Description

ACC
If TC is Equivalent to 1, Negate ACC OPCODE

0101 0110 0011 0010
OBJMODE RPT 1
CYC 1
Accumulator register Based on the state of the test control (TC) bit, conditionally replace the content of the ACC register with its negative:
if( TC = 1 ) { if(ACC = 0x8000 0000) { V = 1; if(OVM = 1) ACC = 0x7FFF FFFF; else ACC = 0x8000 0000 } else ACC = ACC; if(ACC = 0x0000 0000) C = 1; else C = 0; }
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. If (TC = 1 AND ACC = 0) set C; if (TC = 1 AND ACC != 0) clear C; otherwise C is not modified. If (TC = 1 AND ACC = 0x8000 0000) at the start of the operation, this is considered an overflow value and V is set. Otherwise, V is not affected. The state of the TC bit is used as a test condition for the operation. If at the start of the operation, ACC = 0x8000 0000, then this is considered an overflow value and the ACC value after the operation depends on OVM. If OVM is cleared and TC = 1, ACC will be filled with 0x8000 0000. If OVM is set and TC = 1, ACC will be saturated to 0x7FFF FFFF. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Z C
TC OVM
Repeat
6-248
NEGTC ACC
Example
; Calculate signed: Quot16 = Num16/Den16, Rem16 = Num16%Den16 CLRC TC ; Clear TC flag, used as sign flag MOV ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOV T,@AH ; Temp save Den16 in T register MOV ACC,@Num16 << 16 ; AH = Num16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOVU ACC,@AH ; AH = 0, AL = Num16 RPT #15 ; Repeat operation 16 times ||SUBCU @T ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV ACC,@AL << 16 ; AH = Quot16, AL = 0 NEGTC ACC ; Negate if TC = 1 MOV @Quot16,AH ; Store quotient in Quot16
6-249
NOP {*ind}{ARPn}
NOP {*ind}{ARPn} SYNTAX OPTIONS NOP {*ind}{,ARPn} Operands {*ind} ARPn Description
No Operation With Optional Indirect Address Modification OPCODE

0111 0111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Indirect address mode (see chapter 5) Auxiliary register pointer (ARP0 to ARP7) Modify the indirect address operand as specified and change the auxiliary register pointer (ARP) to the given auxiliary register. If no operands are given, then do nothing. None
This instruction is repeatable. If this instruction follows the RPT instruction, it will execute N+1 times.
; Copy the contents of Array1 to Array2: ; int32 Array1[N]; ; int32 Array2[N]; ; for(i=0; i < N; i++) ; Array2[i] = Array1[i]; ; This example only works for code located in upper 64K ; of program space: XAR2,#Array1 ; XAR2 = pointer to Array1 XAR3,#Array2 ; XAR3 = pointer to Array2 @AR0,#(N1) ; Repeat loop N times *,ARP2 ; Point to XAR2 (ARP = 2) AMODE ; Full C2xLP address mode compatible ACC,* *++,ARP3 #19 *++,ACC,ARP0 Loop,*,ARP2 ; ACC = Array1[i] ; Increment XAR2 and point to XAR3 ; Do nothing for 20 cycles ; Array2[i] = ACC, point to XAR0 ; Loop if AR[ARP] != 0, AR[ARP], ; point to XAR2
Example
MOVL MOVL MOV NOP SETC Loop: MOVL NOP RPT ||NOP MOVL XBANZ
6-250
NORM ACC, *ind
NORM ACC, *ind SYNTAX OPTIONS NORM ACC, * NORM ACC, *++ NORM ACC, * NORM ACC, *0++ NORM ACC, *0 Operands
ACC *ind
Normalize ACC and Modify Selected Auxiliary Register OPCODE

0101 0110 0010 0100 0101 0110 0101 1010 0101 0110 0010 0000 0101 0110 0111 0111 0101 0110 0011 0000
OBJMODE RPT 1 1 1 1 1 Y Y Y Y Y
CYC N+4 N+4 N+4 N+4 N+4
Accumulator register *, *++, *, *0++, *0 indirect addressing modes (see Chapter 5) Normalize the signed content of the ACC register and modify, as specified by the indirect addressing mode, the auxiliary register (XAR0 to XAR7) pointed to by the auxiliary register pointer (ARP):
Note: The NORM instruction normalizes a signed number in the ACC register by finding the magnitude of the number. An XOR operation is performed on ACC bits 31 and 30. If the bits are the same, then the content of the ACC register is logically shifted left by 1 to eliminate the extra sign bit and the selected pointer is modified. If the bits are different, the ACC is not shifted and the selected pointer is not modified. The selected pointer does not access any memory location.
Description
Flags and Modes
Z N TC
After the operation, the Z flag is set if the ACC value is zero, else Z is cleared. After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the operation set TC, no normalization was needed (ACC did not need to be modified). If the operation cleared TC, bits 31 and 30 were the same and, as a result, the ACC register was logically shifted left by 1. Auxiliary register pointer selects which pointer to modify as part of the operation (XAR0 to XAR7). This instruction is repeatable. If the operation follows a RPT instruction, then the NORM instruction will be executed N+1 times. The state of the Z, N, and TC flags will reflect the final result. Note: If you only want the NORM instruction to execute until normalization is done, you can create a loop that checks the value of the TC bit. When TC = 1, normalization is complete.
ARP
Repeat
6-251
NORM ACC, *ind
Example
; Normalize the contents of VarA, ; XAR2 will contain shift value at the end of the operation: MOVL ACC,@VarA ; ACC = VarA MOVB XAR2,#0 ; Initialize XAR2 to zero NOP *,ARP2 ; Set ARP pointer to point to XAR2 SBF Skip,EQ ; Skip if ACC value is zero RPT #31 ; Repeat next operation 32 times ||NORM ACC,*++ ; Normalize contents of ACC Skip:
6-252
NORM ACC,XARn++/
NORM ACC,XARn++/ SYNTAX OPTIONS NORM ACC,XARn++ NORM ACC,XARn Operands

ACC XARn ++/
Normalize ACC and Modify Selected Auxiliary Register. OPCODE

1111 1111 0111 1nnn 1111 1111 0111 0nnn
OBJMODE RPT X X Y Y
CYC N+4 N+4
Accumulator register XAR0 to XAR7, auxiliary registers post incremented or decremented
Description
Normalize the signed content of the ACC register and modify the specified auxiliary register (XAR0 to XAR7):
if(ACC != 0x0000 0000) { if((ACC(31) XOR ACC(30)) = 0) { ACC = ACC << 1, TC = 0; if(XARn++ addressing mode) XARn += 1; if(XARn addressing mode) XARn = 1; } else TC = 1; } else TC = 1; Note: The NORM instruction normalizes a signed number in the ACC register by finding the magnitude of the number. An XOR operation is performed on ACC bits 31 and 30. If the bits are the same, then the content of the ACC register is logically shifted left by 1 to eliminate the extra sign bit and the selected pointer is modified. If the bits are different, the ACC is not shifted and the selected pointer is not modified. The selected pointer does not access any memory location.
Flags and Modes
Z N TC
After the operation, the Z flag is set if the ACC value is zero, else Z is cleared. After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the operation set TC, no normalization was needed (ACC did not need to be modified). If the operation cleared TC, bits 31 and 30 were the same and, as a result, the ACC register was logically shifted left by 1. This instruction is repeatable. If the operation follows a RPT instruction, then the NORM instruction will be executed N+1 times. The state of the Z, N, and TC flags will reflect the final result. Note: If you only want the NORM instruction to execute until normalization is done, you can create a loop that checks the value of the TC bit. When TC = 1, normalization is complete.
Repeat
6-253
NORM ACC,XARn++/
Example
; Normalize the contents of VarA, ; XAR2 will contain shift value at the end of the operation: MOVL ACC,@VarA ; ACC = VarA MOVB XAR2,#0 ; Initialize XAR2 to zero SBF Skip,EQ ; Skip if ACC value is zero RPT #31 ; Repeat next operation 32 times ||NORM ACC,XAR2++ ; Normalize contents of ACC Skip:
6-254
NOT ACC
NOT ACC SYNTAX OPTIONS NOT ACC Operands Description

ACC
Complement Accumulator OPCODE

1111 1111 0101 0101
OBJMODE RPT X
CYC 1
Accumulator register The content of the ACC register is replaced with its complement:
ACC = ACC XOR 0xFFFFFFFF;
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Complement the contents of VarA: MOVL ACC,@VarA ; ACC = VarA NOT ACC ; Complement ACC contents MOVL @VarA,ACC ; Store result into VarA
6-255
NOT AX
NOT AX SYNTAX OPTIONS NOT AX Operands Description

AX
Complement AX Register OPCODE

1111 1111 0101 111A
OBJMODE X
RPT
CYC 1
Accumulator high (AH) or accumulator low (AL) register Replace the contents of the specified AX register (AH or AL) with its complement:
AX = AX XOR 0xFFFF;
Flags and Modes
After the operation, if bit 15 of AX is 1 then the negative flag bit is set; otherwise it is cleared. After the operation, if AX is 0, then the Z bit is set, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Complement the contents of VarA: MOV AL,@VarA ; Load AL with contents of VarA NOT AL ; Complement contents of AL MOV @VarA,AL ; Store result in VarA
6-256
OR ACC, loc16
OR ACC, loc16 SYNTAX OPTIONS OR ACC, loc16 Operands

ACC loc16
Bitwise OR OPCODE
1010 1111 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Perform a bitwise OR operation on the ACC register with the zero-extended content of the location pointed to by the loc16 address mode. The result is stored in the ACC register:
ACC = ACC OR 0:[loc16];
Description
Flags and Modes
The load to ACC is tested for a negative condition. If bit 31 of ACC is 1, then the negative flag bit is set; otherwise it is cleared. The load to ACC is tested for a zero condition. The zero flag bit is set if the operation generates ACC = 0; otherwise it is cleared This operation is repeatable. If the operation follows a RPT instruction, then the OR instruction will be executed N+1 times. The state of the Z and N flags will reflect the final result.
Repeat
Example
; Calculate the 32-bit value: VarA = VarA OR 0:VarB MOVL ACC,@VarA ; Load ACC with contents of VarA OR ACC,@VarB ; OR ACC with contents of 0:VarB MOVL @VarA,ACC ; Store result in VarA
6-257
OR ACC,#16bit << #0..16
OR ACC,#16bit << #0..16 SYNTAX OPTIONS OR ACC,#16bit << #0..15 OR ACC,#16bit << #16 OPCODE
Bitwise OR OBJMODE RPT 1 1 CYC 1 1
Operands
ACC #16bit #0..16
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Perform a bitwise OR operation on the ACC register with the given 16-bit unsigned constant value left shifted as specified. The value is zero extended and lower order bits are zero filled before the OR operation. The result is stored in the ACC register:
ACC = ACC OR (0:16bit << shift value);
Description
Flags and Modes
N Z
Repeat
Example
; Calculate the 32-bit value: MOVL ACC,@VarA ; OR ACC,#0x8000 << 12 ; MOVL @VarA,ACC ;
VarA = VarA OR 0x08000000 Load ACC with contents of VarA OR ACC with 0x08000000 Store result in VarA
6-258
OR AX, loc16
OR AX, loc16 SYNTAX OPTIONS OR AX, loc16 Operands

AX loc16
Bitwise OR OPCODE
1100 101A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Perform a bitwise OR operation on the specified AX register with the contents of the location pointed to by the loc16 addressing mode. The result is stored in AX:
AX = AX OR [loc16];
Description
Flags and Modes
The load to AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set; otherwise it is cleared. The load to AX is tested for a zero condition. The zero flag bit is set if the operation generates AX = 0, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; OR the contents of VarA and VarB and store in VarC: MOV AL,@VarA ; Load AL with contents of VarA OR AL,@VarB ; OR AL with contents of VarB MOV @VarC,AL ; Store result in VarC
6-259
OR IER,#16bit
OR IER,#16bit SYNTAX OPTIONS OR IER,#16bit OPCODE

0111 0110 0010 0011 CCCC CCCC CCCC CCCC IER #16bitMask
Bitwise OR OBJMODE RPT X CYC 2
Operands
Interrupt enable register 16-bit immediate constant value
Description
Enable specific interrupts by performing a bitwise OR operation with the IER register and the 16-bit immediate value. The result is stored in the IER register:
IER = IER OR #16bit;
None
; Enable INT1 and INT6 only. Do not modify state of other ; interrupts enable: OR IER,#0x0061 ; Enable INT1 and INT6
Example
6-260
OR IFR,#16bit
OR IFR,#16bit SYNTAX OPTIONS OR IFR,#16bit OPCODE

0111 0110 0010 0111 CCCC CCCC CCCC CCCC IFR #16bit
Operands
Interrupt flag register 16-bit immediate constant value Enable specific interrupts by performing a bitwise OR operation with the IFR register and the 16-bit immediate value. The result of the OR operation is stored in the IFR register.
IFR = IFR OR #16bit; Note: Interrupt hardware has priority over CPU instruction operation in cases where the interrupt flag is being simultaneously modified by the hardware and the instruction.
Description
This instruction should not be used with interrupts 112 when the peripheral interrupt expansion (PIE) block is enabled. Flags and Modes Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
; Trigger INT1 and INT6 only. Do not modify state of other ; interrupts flags: OR IFR,#0x0061 ; Trigger INT1 and INT6
None
Example
6-261
OR loc16,#16bit
OR loc16,#16bit SYNTAX OPTIONS OR loc16,#16bit OPCODE

Operands
loc16 #16bit
Addressing mode (see Chapter 5) 16-bit immediate constant value Perform a bitwise OR operation on the content of the location pointed to by the loc16 addressing mode and the 16-bit immediate constant value. The result is stored in the location pointed to by loc16: [loc16] = [loc16] OR 16bit; Smart Encoding: If loc16 = AH or AL and #16bit is an 8-bit number, then the assembler will encode this instruction as ORB AX, #8bit to improve efficiency. To override this encoding, use the ORW AX, #16bit instruction alias.
Description
Flags and Modes
Repeat
Example
; Set Bits 4 and 7 of VarA: ; VarA = VarA OR #(1 << 4 | 1 << 7) OR @VarA,#(1 << 4 | 1 << 7) ; Set bits 4 and 7 of VarA
6-262
OR loc16, AX
OR loc16, AX SYNTAX OPTIONS OR loc16, AX Operands

loc16 AX
Bitwise OR OPCODE
1001 100A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Aaccumulator high (AH) or accumulator low (AL) register Perform a bitwise OR operation on the contents of location pointed to by the loc16 addressing mode with the specified AX register. The result is stored in the addressed location specified by loc16:
[loc16] = [loc16] OR AX;
Description
This instruction performs a read-modify-write operation. Flags and Modes

Z N
The load to [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set; otherwise it is cleared. The load to [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; OR the contents of VarA with VarB and store in VarB: MOV AL,@VarA ; Load AL with contents of VarA OR @VarB,AL ; VarB = VarB OR AL
6-263
ORB AX,#8bit
ORB AX,#8bit SYNTAX OPTIONS ORB AX, #8bit Operands

AX #8bit
Bitwise OR 8-bit Value OPCODE

0101 000A CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate constant value Perform a bitwise OR operation on the specified AX register with the 8-bit unsigned immediate constant zero extended. The result is stored in AX:
AX = AX OR 0x00:8bit;
Description
Flags and Modes
Repeat
Example
; Set bit 7 of VarA and store result in VarB: MOV AL,@VarA ; Load AL with contents of VarA ORB AL,#0x80 ; OR contents of AL with 0x0080 MOV @VarB,AL ; Store result in VarB
6-264
OUT *(PA),loc16
OUT *(PA),loc16 SYNTAX OPTIONS OUT *(PA),loc16 OPCODE

Output Data to Port OBJMODE RPT 1 CYC 4
Operands
*(PA) loc16
Immediate I/O space memory address Addressing mode (see Chapter 5) Store the 16-bit value from the location pointed to by the loc16 addressing mode into the I/O space location pointed to by the *(PA) operand):
IOspace[0x0000PA] = [loc16];
Description
I/O Space is limited to 64K range (0x0000 to 0xFFFF). On the external interface (XINTF), if available on a particular device, the I/O strobe signal (XISn) is toggled during the operation. The I/O address appears on the lower 16 XINTF address lines (XA(15:0)) and the upper address lines are zeroed. The data appears on the lower 16 data lines (XD(15:0).
Note: The UOUT operation is not pipeline protected. Hence, if an IN instruction immediately follows a UOUT instruction, the IN will occur before the UOUT. To be certain of the sequence of operation, use the OUT instruction, which is pipeline protected. Note: The UOUT operation is not pipeline protected. Therefore, if an IN instruction immediately follows a UOUT instruction, the IN will occur before the UOUT. To be certain of the sequence of operation, use the OUT instruction, which is pipeline protected. I/O space may not be implemented on all C28x devices. See the data sheet for your particular device for details.
None
; IORegA address = 0x0300; ; IOREgB address = 0x0301; ; IOREgC address = 0x0302; ; IORegA = 0x0000; ; IORegB = 0x0400; ; IORegC = VarA; ; if( IORegC = 0x2000 ) ; IORegC = 0x0000; IORegA .set 0x0300
Example
; Define IORegA address
6-265
OUT *(PA),loc16
IORegB IORegC MOV UOUT MOV UOUT OUT IN CMP SB MOV UOUT $10:
.set 0x0301 .set 0x0302 @AL,#0 *(IORegA),@AL @AL,#0x0400 *(IORegB),@AL *(IORegC),@VarA @AL,*(IORegC) @AL,#0x2000 $10,NEQ @AL,#0 *(IORegC),@AL
; ; ; ; ; ; ; ; ; ; ; ;
Define IORegB address Define IORegC address AL = 0 IOspace[IORegA] = AL AL = 0x0400 IOspace[IORegB] = AL IOspace[IORegC] = VarA AL = IOspace[IORegC] Set flags on (AL 0x2000) Branch if not equal AL = 0 IOspace[IORegC] = AL
6-266
POP ACC
POP ACC SYNTAX OPTIONS POP ACC Operands Description

ACC
Pop Top of Stack to Accumulator OPCODE

0000 0110 1011 1110
OBJMODE RPT X
CYC 1
Accumulator Predecrement SP by 2. Load ACC with the 32-bit value pointed to by SP:
SP = 2; ACC = [SP];
Flags and Modes
The load to ACC is tested for a negative condition. Bit-31 of the ACC register is the sign bit, 0 for positive, 1 for negative. The negative flag bit is set if the operation on the ACC register generates a negative value, otherwise it is cleared. The load to ACC is tested for a zero condition. The bit is set if the result of the operation on the ACC register generates a 0 value, otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
6-267
POP ARn:ARm
POP ARn:ARm SYNTAX OPTIONS POP AR1:AR0 POP AR3:AR2 POP AR5:AR4 Operands
ARn: ARm
Pop Top of Stack to 16-bit Auxiliary Registers OPCODE

0111 0110 0000 0111 0111 0110 0000 0101 0111 0110 0000 0110
OBJMODE RPT X X X
CYC 1 1 1
AR1:AR0 or AR3:AR2 or AR5:AR4 auxiliary registers
Description
AR1:AR0 or AR3:AR2 or AR5:AR4 Predecrement SP by 2. Load the contents of two 16-bit auxiliary registers (ARn and ARm)with the value pointed to by SP and SP+1.
POP AR1:AR0 SP = 2; AR0 = [SP]; AR1 = [SP+1]; AR1H:AR0H = unchanged; POP AR3:AR2 SP = 2; AR2 = [SP]; AR3 = [SP+1]; AR3H:AR2H = unchanged; POP AR5:AR4 SP = 2; AR4 = [SP]; AR5 = [SP+1]; AR5H:AR4H = unchanged;
None
6-268
POP AR1H:AR0H
POP AR1H:AR0H SYNTAX OPTIONS POP AR1H:AR0H Operands

AR1H: AR0H
Pop Top of Stack to Upper Half of Auxiliary Registers OPCODE

0000 0000 0000 0011
OBJMODE RPT X
CYC 1
Upper 16-bits of XAR1 and XAR0 auxiliary registers
Description
Predecrement SP by 2. Load the contents of AR0H with the value pointed to by SP and AR1H with the value pointed to by SP+1. The lower 16 bits of the auxiliary registers (AR0 and AR1) are left unchanged.
SP = 2; AR0H = [SP]; AR1H = [SP+1]; AR1:AR0 = unchanged;
None
. . . POP XT POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H IRET ; Full context restore for an ; interrupt or trap function ; ; ; ; ; ; ; ; 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 16-bit XT restore XAR7 restore XAR6 restore XAR5 restore XAR4 restore XAR5 restore XAR2 restore AR1H and 16-bit AR0H restore
Example
6-269
POP DBGIER
POP DBGIER SYNTAX OPTIONS POP DBGIER Operands Description

DBGIER
Pop Top of Stack to DBGIER OPCODE

0111 0110 0001 0010
OBJMODE RPT X
CYC 5
Debug interrupt-enable register Predecrement SP by 1. Load the contents of DBGIER with the value pointed to by SP:
SP = 1; DBGIER = [SP];
None
6-270
POP DP
POP DP SYNTAX OPTIONS POP DP Operands Description

DP
Pop Top of Stack to the Data Page OPCODE

0111 0110 0000 0011
OBJMODE RPT X
CYC 1
Data-page register Predecrement SP by 1. Load the contents of DP with the value pointed to by SP:
SP = 1; DP = [SP];
None
6-271
POP DP:ST1
POP DP:ST1 SYNTAX OPTIONS POP DP:ST1 Operands Description

DP:ST1
Pop Top of Stack to DP and ST1 OPCODE

0111 0110 0000 0001
OBJMODE RPT X
CYC 5
data page register and status register 1 Predecrement SP by 2. Load ST1 with the value pointed to by SP and load DP with the value pointed to by SP+1:
SP = 2; ST1 = [SP]; DP = [SP+1];
None
6-272
POP IFR
POP IFR SYNTAX OPTIONS POP IFR Operands Description

IFR
Pop Top of Stack to IFR OPCODE

0000 0000 0000 0010
OBJMODE RPT X
CYC 5
Interrupt flag register Predecrement SP by 1. Load the contents of IFR with the value pointed to by SP:
SP = 1; IFR = [SP];
None
6-273
POP loc16
POP loc16 SYNTAX OPTIONS POP loc16 Operands Description

loc16
Pop Top of Stack OPCODE

0010 1010 LLLL LLLL
OBJMODE RPT X
CYC 2
Addressing mode (See Chapter 5) Predecrement SP by 1. Load the contents of loc16 with the 16-bit value pointed to by SP.
SP -= 1; [loc16] = [SP];
Flags and Modes
If (loc16 = @AX), then the load to AX is tested for a negative condition. Bit-15 of the AX register is the sign bit, 0 for positive, 1 for negative. The negative flag bit is set if the operation on the AX register generates a negative value, otherwise it is cleared. If (loc16 = @AX), then the load to AX is tested for a zero condition. The bit is set if the result of the operation on the AX register generates a 0 value, otherwise it is cleared This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
POP @T
POP @AL
POP @AR4
POP *XAR4++
; Predecrement SP by 1. Load ; XT(31:15) with the ; contents of the location pointed to ; by SP. TL is unchanged. ; Predecrement SP by 1. Load AL with ; the contents of the location pointed ; to by SP. AH is unchanged. ; Predecrement SP by 1. Load AR4 with ; the contents of the location pointed ; to by SP. AR4H is unchanged. ; Predecrement SP by 1. Load the ; 16-bit location pointed to by XAR4 ; with the contents of the location ; pointed to by SP. Post-increment ; XAR4 by 1
6-274
POP P
POP P SYNTAX OPTIONS POP P Operands Description

P
Pop top of Stack to P OPCODE

0111 0110 0001 0001
OBJMODE RPT X
CYC 1
Product register Predecrement SP by 2. Load P with the 32-bit value pointed to by SP:
SP = 2; P = [SP];
None
6-275
POP RPC
POP RPC SYNTAX OPTIONS POP RPC Operands Description

RPC
Pop RPC Register From Stack OPCODE

0000 0000 0000 0111
OBJMODE RPT X
CYC 3
Return program counter register Predecrement SP by 2. Load the contents of RPC with the value pointed to by SP:
SP = 2; RPC = [SP];
None
6-276
POP ST0
POP ST0 SYNTAX OPTIONS POP ST0 Operands Description

ST0
Pop Top of Stack to ST0 OPCODE

0111 0110 0001 0011
OBJMODE RPT X
CYC 1
status register 0 Predecrement SP by 1. Load the contents of ST0 with the value pointed to by SP:
SP = 1; ST0 = [SP];
Flags and Modes
The bit value of each flag and mode listed is replaced by the value popped off of the stack
N V Z TC SXM OVC PM
Repeat
6-277
POP ST1
POP ST1 SYNTAX OPTIONS POP ST1 Operands Description

ST1
Pop Top of Stack to ST1 OPCODE

0111 0110 0000 0000
OBJMODE RPT X
CYC 5
Status register 1 Predecrement SP by 1. Load the contents of ST0 with the value pointed to by SP:
SP = 1; ST1 = [SP];
Flags and Modes
DBGM
The bit values for each flag and mode listed is replaced by the value popped off of the stack
INTM VMAP SPA PAGE0 AMODE ARP EALLOW OBJMODE XF
Repeat
6-278
POP T:ST0
POP T:ST0 SYNTAX OPTIONS POP T:ST0 Operands Description

T:ST0
Pop Top of Stack to T and ST0 OPCODE

0111 0110 0001 0101
OBJMODE RPT X
CYC 1
The upper 16-bits of the multiplicand register and status register 0 Predecrement SP by 2. Load ST0 with the value pointed to by SP and load T with the value pointed to by SP+1. The low 16 bits of the XT Register (TL) are left unchanged:
SP = 2; T = [SP]; ST0 = [SP+1]; TL = unchanged;
None
6-279
POP XARn
POP XARn SYNTAX OPTIONS POP XAR0 POP XAR1 POP XAR2 POP XAR3 POP XAR4 POP XAR5 POP XAR6 POP XAR7 Operands Description
XARn
Pop Top of Stack to 32-bit Auxiliary Register OPCODE

0011 1010 1011 1110 1011 0010 1011 1110 1010 1010 1011 1110 1010 0010 1011 1110 1010 1000 1011 1110 1010 0000 1011 1110 1100 0010 1011 1110 1100 0011 1011 1110
CYC 1 1 1 1 1 1 1 1
XAR0 to XAR7, 32-bit auxiliary registers Predecrement SP by 2. Load XARn with the 32-bit value pointed to by SP:
SP = 2; XARn = [SP];
None
. . . POP XT POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H IRET ; Full context restore for an ; interrupt or trap function ; ; ; ; ; ; ; ; 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 16-bit XT restore XAR7 restore XAR6 restore XAR5 restore XAR4 restore XAR3 restore XAR2 restore AR1H and 16-bit AR0H restore
Example
6-280
POP XT
POP XT SYNTAX OPTIONS POP XT Operands Description

XT
Pop Top of Stack to XT OPCODE

1000 0111 1011 1110
OBJMODE RPT X
CYC 1
Multiplicand register Predecrement SP by 2. Load XT with the 32-bit value pointed to by SP:
SP = 2; XT = [SP];
None
6-281
PREAD loc16,*XAR7
PREAD loc16,*XAR7 SYNTAX OPTIONS PREAD loc16,*XAR7 Operands

loc16 *XAR7
Read From Program Memory OPCODE

0010 0100 LLLL LLLL
OBJMODE RPT X Y
CYC N+2
Addressing mode (see Chapter 5) Indirect programmemory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Load the data memorylocation pointed to by the loc16 addressing mode with the 16-bit content of the programmemory location pointed to by *XAR7:
[loc16] = Prog[*XAR7];
Description
On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *XAR7 addressing mode can be used to access data space variables that fall within the program space address range. With some addressing mode combinations, you can get conflicting references. In such cases, the C28x will give the loc16/loc32 field priority on changes to XAR7. For example:
PREAD PREAD *XAR7,*XAR7 *XAR7++,*XAR7 ; *XAR7 given priority ; *XAR7++ given priority
Flags and Modes
If (loc16 = @AX) and bit 15 of AX is 1, then N is set; otherwise N is cleared. If (loc16 = @AX) and the value of AX is zero, then Z is set; otherwise Z is cleared. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *XAR7 programmemory address is copied to an internal shadow register and the address is postincremented by 1 during each repetition.
Repeat
Example
; Copy the contents of Array1 to Array2:

; ; ; ; ; ; int16 Array1[N] // Located in program space int16 Array [N] // Located in data space for(i=0; i N; i++) Array2[i] = Array1[i]; MOVL XAR7,#Array1 ; XAR7 = pointer to Array1 MOVL XAR2,#Array2 ; XAR2 = pointer to Array2
6-282
PREAD loc16,*XAR7
RPT ||PREAD
#(N1) *XAR2++,*XAR7
; Repeat next instruction N times ; Array2[i] = Array1[i], ; i++
6-283
PUSH ACC
PUSH ACC SYNTAX OPTIONS PUSH ACC OPCODE
Push Accumulator Onto Stack OBJMODE RPT X CYC 2
0001 1110 1011 1101
Note: This instruction is an alieas for the MOV*SP++, ACC instruction.
ACC
Accumulator register Push the 32-bit contents of ACC onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = ACC; SP += 2;
None
MOVL XAR4, #VarA MOVL ACC, *+XAR4[0] PUSH ACC ; ; ; ; ; ; ; Initialize XAR4 pointer with the 22-bit address of VarA Load the 32-bit contents of VarA into ACC Push the 32-bit ACC into the location pointed to by SP. Post-increment SP by 2
Example
6-284
PUSH ARn:ARm
PUSH ARn:ARm SYNTAX OPTIONS PUSH AR1:AR0 PUSH AR3:AR2 PUSH AR5:AR4 Operands
ARn: ARm
Push 16-bit Auxiliary REgisters Onto Stack OPCODE

0111 0110 0000 1101 0111 0110 0000 1111 0111 0110 0000 1100
OBJMODE RPT X X X
CYC 1 1 1
AR1:AR0 or AR3:AR2 or AR5:AR4 auxiliary registers
Description
Push the contents of two 16-bit auxiliary registers (ARn and ARm) onto the stack pointed to by SP. Post-increment SP by 2:
PUSH AR1:AR0 [SP] = AR0; [SP+1] = AR1; SP += 2; PUSH AR3:AR2 [SP] = AR2; [SP+1] = AR3; SP += 2; PUSH AR5:AR4 [SP] = AR4; [SP+1] = AR5; SP += 2;
None
6-285
PUSH AR1H:AR0H
PUSH AR1H:AR0H SYNTAX OPTIONS PUSH AR1H:AR0H Operands

AR1H: AR0H
Push AR1H and Ar0H Registers on Stack OPCODE

0000 0000 0000 0101
OBJMODE RPT X
CYC 1
Upper 16-bits of XAR1 and XAR0 auxiliary registers
Description
Push the contents of AR0H followed by the contents of AR1H onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = AR0H; [SP+1] = AR1H; SP += 2;
None
IntX: ; Full context save code for an ; interrupt or trap function AR1H:AR0H XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 XT ; ; ; ; ; ; ; ; 16-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit AR1H and store of store of store of store of store of store of store of 16-bit AR0H store XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 XT
Example
PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH . . .
6-286
PUSH DBGIER
PUSH DBGIER SYNTAX OPTIONS PUSH DBGIER Operands Description

DBGIER
Push DBGIER Register Onto Stack OPCODE

0111 0110 0000 1110
OBJMODE RPT X
CYC 1
Debug interrupt enable register Push the 16-bit contents of DBGIER onto the stack pointed to by SP. Post-increment SP by 1:
[SP] = DBGIER; SP += 1;
None
6-287
PUSH DP
PUSH DP SYNTAX OPTIONS PUSH DP Operands Description

DP
Push DP Register Onto Stack OPCODE

0111 0110 0000 1011
OBJMODE RPT X
CYC 1
Data-page register Push the 16-bit contents of DP onto the stack pointed to by SP. Post-increment SP by 1:
[SP] = DP; SP += 1;
None
6-288
PUSH DP:ST1
PUSH DP:ST1 SYNTAX OPTIONS PUSH DP:ST1 Operands Description

DP:ST1
Push DP and ST1 Onto Stack OPCODE

0111 0110 0000 1001
OBJMODE RPT X
CYC 1
Data-page register and status register 1 Push the 16- bit contents of ST1 followed by the 16-bit contents of DP onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = ST1; [SP+1] = DP; SP += 2;
None
6-289
PUSH IFR
PUSH IFR SYNTAX OPTIONS PUSH IFR Operands Description

IFR
Push IFR Onto Stack OPCODE

0111 0110 0000 1010
OBJMODE RPT X
CYC 1
Interrupt flag register Push the 16-bit contents of IFR onto the stack pointed to by SP. Post-increment SP by 1:
[SP] = IFR; SP += 1;
None
6-290
PUSH loc16
PUSH loc16 SYNTAX OPTIONS PUSH loc16 Operands Description

loc16
Push 16-bit Value on Stack OPCODE

0010 0010 LLLL LLLL
OBJMODE RPT X
CYC 2
Addressing mode (see Chapter 5) Push a 16-bit value pointed to by the loc16 operand on the stack pointed to by SP. Post-increment SP by 1:
[SP] = [loc16]; SP += 1;
None
PUSH @T ; ; ; ; ; ; ; ; ; ; ; ; ; Push the contents of XT(31:15) into the location pointed to by SP. Post-increment SP by 1 Push the contents of AL onto into the location pointed to by SP. Post-increment SP by 1 Push the lower 16-bits of XAR4 into the location pointed to by SP. Post-increment SP by 1 Push the value pointed to by XAR4 into the location pointed to by SP. Post-increment SP and XAR4 by 1
Example
PUSH @AL
PUSH @AR4
PUSH *XAR4++
6-291
PUSH P
PUSH P SYNTAX OPTIONS PUSH P Operands Description

P
Push P Onto Stack OPCODE

0111 0110 0001 1101
OBJMODE RPT X
CYC 1
Product register Push the 32-bit contents of P onto the stack pointed to by SP Post-increment SP by 2:
[SP] = P; SP += 2;
None
MOVL XAR5, #VarA MOVL P, PUSH P *+XAR5[0] ; ; ; ; ; ; ; Initialize XAR5 pointer with the 22-bit address of VarA Load the 32-bit contents of VarA into P Push the 32-bit P into the location pointed to by SP. Post-increment SP by 2
6-292
PUSH RPC
PUSH RPC SYNTAX OPTIONS PUSH RPC Operands Description

RPC
Push RPC Onto Stack OPCODE

0000 0000 0000 0100
OBJMODE RPT X
CYC 1
Return program counter register Push the contents of the RPC register onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = RPC; SP += 2;
None
6-293
PUSH ST0
PUSH ST0 SYNTAX OPTIONS PUSH ST0 Operands Description

ST0
Push ST0 Onto Stack OPCODE

0111 0110 0001 1000
OBJMODE RPT X
CYC 1
Status register 0 Push the 16-bit contents of ST0 onto the stack pointed to by SP. Post-increment SP by 1:
[SP] = ST0; SP += 1;
None
6-294
PUSH ST1
PUSH ST1 SYNTAX OPTIONS PUSH ST1 Operands Description

ST1
Push ST1 Onto Stack OPCODE

0111 0110 0000 1000
OBJMODE RPT X
CYC 1
Status register 1 Push the 16-bit contents of ST1 onto the stack pointed to by SP. Post-increment SP by 1:
[SP] = ST1; SP += 1;
None
6-295
PUSH T:ST0
PUSH T:ST0 SYNTAX OPTIONS PUSH T:ST0 Operands Description

T:ST0
Push T and ST0 Onto Stack OPCODE

0111 0110 0001 1001
OBJMODE RPT X
CYC 1
The upper 16-bits of the multiplicand register and status register 0 Push the 16- bit contents of ST0 followed by the 16-bit contents of T onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = ST0; [SP+1] = T; SP += 2;
None
6-296
PUSH XARn
PUSH XARn SYNTAX OPTIONS PUSH XAR0 PUSH XAR1 PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 Operands Description
XARn
Push 32-bit Auxiliary Register Onto Stack OPCODE

0011 1010 1011 1101 1011 0010 1011 1101 1010 1010 1011 1101 1010 0010 1011 1101 1010 1000 1011 1101 1010 0000 1011 1101 1100 0010 1011 1101 1100 0011 1011 1101
CYC 1 1 1 1 1 1 1 1
XAR0 to XAR7, 32-bit auxiliary register Push the 32-bit contents of XARn onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = XARn; SP += 2;
None
IntX:
Example
; Full context save code for an ; interrupt or trap function
PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH . . .
AR1H:AR0H XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 XT
; 16-bit AR1H and 16-bit AR0H store ; 32-bit store of XAR2 ; 32-bit store of XAR3 ; 32-bit store of XAR4 ; 32-bit store of XAR5 ; 32-bit store of XAR6 ; 32-bit store of XAR7 ; 32-bit store of XT
6-297
PUSH XT
PUSH XT SYNTAX OPTIONS PUSH XT Operands Description

XT
Push XT Onto Stack OPCODE

1010 1011 1011 1101
OBJMODE RPT X
CYC 1
Multiplicand register Push the 32-bit contents of XT onto the stack pointed to by SP. Post-increment SP by 2:
[SP] = XT; SP += 2;
None
MOVL XAR1, #VarA MOVL XT, *+XAR5[0] PUSH XT ; ; ; ; ; ; ; Initialize XAR1 pointer with the 22-bit address of VarA Load the 32-bit contents of VarA into XT Push the 32-bit XT into the location pointed to by SP. Post-increment SP by 2
Example
6-298
PWRITE *XAR7,loc16
PWRITE *XAR7,loc16 SYNTAX OPTIONS PWRITE *XAR7, loc16 Operands

*XAR7
Write to Program Memory OPCODE

0010 0110 LLLL LLLL
OBJMODE RPT X Y
CYC N+5
Indirect programmemory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF)
loc16
Addressing mode (see Chapter 5) Load the programmemory location pointed to by the *XAR7 with the content of the location pointed to by the loc16 addressing mode:
Prog[*XAR7] = [loc16];
Description
On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *XAR7 addressing mode can be used to access data space variables that fall within the program space address range. With some addressing mode combinations, you can get conflicting references. In such cases, the C28x will give the loc16/loc32 field priority on changes to XAR7. For example:
PWRITE PWRITE *XAR7,*XAR7 *XAR7,*XAR7++ ; *XAR7 given priority ; *XAR7++ given priority
None
This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *XAR7 programmemory address is copied to an internal shadow register and the address is postincremented by 1 during each repetition. ; Copy the contents of Array1 to Array2:
; int16 Array1[N]; // Located in data space ; int16 Array2[N]; // Located in program space ; for(i=0; i < N; i++) ; Array2[i] = Array1[i]; MOVL XAR2,#Array1 ; XAR2 = pointer to Array1 MOVL XAR7,#Array2 ; XAR7 = pointer to Array2 RPT #(N1) ; Repeat next instruction N times ||PWRITE *XAR7,*XAR2++ ; Array2[i] = Array1[i], ; i++
Example
6-299
QMACL P,loc32,*XAR7/++
QMACL P,loc32,*XAR7/++ SYNTAX OPTIONS QMACL P,loc32,*XAR7 QMACL P,loc32,*XAR7++
Signed 32 X 32-bit Multiply and Accumulate (Upper Half) OPCODE

OBJMODE RPT 1 1 Y Y
CYC N+2 N+2
Operands
P loc32

Note: The @ACC addressing mode cannot be used when the instruction is repeated. No illegal instruction trap will be generated if used (assembler will flag an error).
*XAR7/ ++
Indirect programmemory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) 32-bit x 32-bit signed multiply and accumulate. First, add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. Then, multiply the signed 32-bit content of the location pointed to by the loc32 addressing mode by the signed 32-bit content of the programmemory location pointed to by the XAR7 register and store the upper 32bits of the 64-bit result in the P register. If specified, post-increment the XAR7 register by 2:
ACC = ACC + P << PM; P = (signed T * signed Prog[*XAR7 or *XAR7++]) >> 32;
Description
QMACL QMACL QMACL P,*XAR7,*XAR7++ P,*XAR7++,*XAR7 P,*XAR7,*XAR7++ ; XAR7 given priority ; *XAR7++ given priority ; *XAR7++ given priority
Flags and Modes
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
6-300
QMACL P,loc32,*XAR7/++
C V OVC
If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result in the ACC. The V flag will be set if an intermediate overflow occurs in the ACC.
OVM
PM
Repeat
Example
; ; ; ; ; ; ;
Calculate sum of product using 32-bit multiply and retain high result: int32 X[N]; // Data information int32 C[N]; // Coefficient information (located in low 4M) int32 sum = 0; for(i=0; i < N; i++) sum = sum + ((X[i] * C[i]) >> 32) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #(N1) ; Repeat next instruction N times ||QMACL P,*XAR2++,*XAR7++ ; ACC = ACC + P >> 5, ; P = (X[i] * C[i]) >> 32 ADDL MOVL ACC,P << PM @sum,ACC ; i++ ; Perform final accumulate ; Store final result into sum
6-301
QMPYAL P,XT,loc32
QMPYAL P,XT,loc32 SYNTAX OPTIONS QMPYAL P,XT,loc32 Operands

P XT loc32
Signed 32-bit Multiply (Upper Half) and Add Previous P OPCODE

0101 0110 0100 0110 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Signed 32-bit x 32-bit multiply and accumulate the previous product. Add the previous signed product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. In addition, multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode and store the upper 32bits of the 64-bit result in the P register:
ACC = ACC + P << PM; P = (signed T * signed [loc32]) >> 32;
Description
Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
OVM
PM
Repeat
6-302
QMPYAL P,XT,loc32
Example
; Calculate signed result: ; Y32 = (X0*C0 + X1*C1 + X2*C2) >> (32 + 2) SPM 2 ; Set product shift mode to >> 2 ZAPA ; Zero ACC, P, OVC MOVL XT,@X0 ; XT = X0 QMPYL P,XT,@C0 ; P = high 32bits of (X0*C0) MOVL XT,@X1 ; XT = X0 QMPYAL P,XT,@C1 ; ACC = ACC + P >> 2, ; P = high 32bits of (X1*C1) MOVL XT,@X2 ; XT = X0 QMPYAL P,XT,@C2 ; ACC = ACC + P >> 2, ; P = high 32bits of (X2*C2) ADDL ACC,P << PM ; ACC = ACC + P >> 2 MOVL @Y32,ACC ; Store result into Y32
6-303
QMPYL P,XT,loc32
QMPYL P,XT,loc32 SYNTAX OPTIONS QMPYL P,XT,loc32
Signed 32 X 32-bit Multiply (Upper Half) OPCODE

0101 0110 0110 0111 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
P XT loc32
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode and store the upper 32bits of the 64-bit result (a Q30 number) in the P register:
P = (signed XT * signed [loc32]) >> 32;
Description
None
; Calculate signed result: Y64 = M32*X32 + B64 MOVL XT,@M32 ; XT = M32 IMPYL P,XT,@X32 ; P = low 32bits of (M32*X32) MOVL ACC,@B64+2 ; ACC = high 32bits of B64 ADDUL P,@B64+0 ; P = P + low 32bits of B64 MOVL @Y64+0,P ; Store low 32-bit result into Y64 QMPYL P,XT,@X32 ; P = high 32bits of (M32*X32) ADDCL ACC,@P ; ACC = ACC + P + carry MOVL @Y64+2,ACC ; Store high 32-bit result into Y64
Example
6-304
QMPYL ACC,XT,loc32
QMPYL ACC,XT,loc32 SYNTAX OPTIONS QMPYL ACC,XT,loc32
Signed 32 X 32-bit Multiply (Upper Half)OPCODE

0101 0110 0110 0011 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 2
Operands
P XT ACC
Product register Multiplicand register Accumulator register Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the loc32 addressing mode and store the upper 32-bits of the 64-bit result (a Q30 number) in the ACC register:
ACC = (signed XT * signed [loc32]) >> 32;
Description
Flags and Modes
After the operation, the Z flag is set if the ACC value is zero, else Z is cleared. After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate signed result: Y64 = M32*X32 MOVL XT,@M32 ; XT = M32 IMPYL P,XT,@X32 ; P = low 32bits of (M32*X32) QMPYL ACC,XT,@X32 ; ACC = high 32bits of (M32*X32) MOVL @Y64+0,P ; Store result into Y64 MOVL @Y64+2,ACC
6-305
QMPYSL P,XT,loc32
QMPYSL P,XT,loc32 SYNTAX OPTIONS QMPYSL P,XT,loc32 Operands

P XT loc32
Signed 32-bit Multiply (Upper Half) and Subtract Previous P OPCODE

0101 0110 0100 0101 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Signed 32-bit x 32-bit multiply and subtract the previous product. Subtract the previous signed product (stored in the P register), shifted as specified by the product shift mode (PM), from the ACC register. In addition, multiply the signed 32-bit content of the XT register by the signed 32-bit constant value and store the upper 32bits of the 64-bit result in the P register:
ACC = ACC P << PM; P = (signed T * signed [loc32]) >> 32;
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V OVC
OVM
PM
Repeat
6-306
QMPYSL P,XT,loc32
Example
; Calculate signed result: ; Y32 = (X0*C0 + X1*C1 + X2*C2) >> (32 + 2) SPM 2 ; Set product shift mode to >> 2 ZAPA ; Zero ACC, P, OVC MOVL XT,@X0 ; XT = X0 QMPYL P,XT,@C0 ; P = high 32bits of (X0*C0) MOVL XT,@X1 ; XT = X0 QMPYSL P,XT,@C1 ; ACC = ACC P >> 2, ; P = high 32bits of (X1*C1) MOVL XT,@X2 ; XT = X0 QMPYSL P,XT,@C2 ; ACC = ACC P >> 2, ; P = high 32bits of (X2*C2) SUBL ACC,P << PM ; ACC = ACC P >> 2 MOVL @Y32,ACC ; Store result into Y32
6-307
QMPYUL P,XT,loc32
QMPYUL P,XT,loc32 SYNTAX OPTIONS QMPYUL P,XT,loc32
Unsigned 32 X 32-bit Multiply (Upper Half) OPCODE

0101 0110 0100 0111 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Operands
P XT loc32
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the unsigned 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the loc32 addressing mode and store the upper 32bits of the 64-bit result in the P register:
P = (unsigned XT * unsigned [loc32]) >> 32;
Description
None
; Calculate unsigned result: Y64 = M32*X32 + B64 MOVL XT,@M32 ; XT = M32 IMPYL P,XT,@X32 ; P = low 32bits of (M32*X32) MOVL ACC,@B64+2 ; ACC = high 32bits of B64 ADDUL P,@B64+0 ; P = P + low 32bits of B64 MOVL @Y64+0,P ; Store low 32-bit result into Y64 QMPYUL P,XT,@X32 ; P = high 32bits of (M32*X32) ADDCL ACC,@P ; ACC = ACC + P + carry MOVL @Y64+2,ACC ; Store high 32-bit result into Y64
Example
6-308
QMPYXUL P,XT,loc32
QMPYXUL P,XT,loc32 SYNTAX OPTIONS QMPYXUL P,XT,loc32 Operands

P XT loc32
Signed X Unsigned 32-bit Multiply (Upper Half) OPCODE

0101 0110 0100 0010 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Product register Multiplicand register Addressing mode (see Chapter 5) Multiply the signed 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the loc32 addressing mode and store the upper 32bits of the 64-bit result in the P register:
P = (signed XT * unsigned [loc32]) >> 32;
Description
None
; Calculate signed result: Y64 = (M64*X64) >> 64 + B64 ; Y64 = Y1:Y0, M64 = M1:M0, X64 = X1:X0, B64 = B1:B0 MOVL XT,@X1 ; XT = X1 QMPYXUL P,XT,@M0 ; P = high 32bits of (uns M0 * sign X1) MOV @T,#32 ; T = 32 LSL64 ACC:P,T ; ACC:P = ACC:P << T ASR64 ACC:P,T ; ACC:P = ACC:P >> T MOVL @XAR4,P ; XAR5:XAR4 = ACC:P MOVL @XAR5,ACC MOVL XT,@M1 ; XT = M1 QMPYXUL P,XT,@X0 ; P = high 32bits of (sign M1 * uns X0) MOV @T,#32 ; T = 32 LSL64 ACC:P,T ; ACC:P = ACC:P << T ASR64 ACC:P,T ; ACC:P = ACC:P >> T MOVL @XAR6,P ; XAR7:XAR6 = ACC:P MOVL @XAR7,ACC IMPYL P,XT,@X1 ; P = low 32bits of (sign M1 * sign X1) QMPYL ACC,XT,@X1 ; ACC = high 32bits of (sign M1 * sign X1) ADDUL P,@XAR4 ; ACC:P = ACC:P + XAR5:XAR4 ADDCL ACC,@XAR5 ADDUL P,@XAR6 ; ACC:P = ACC:P + XAR7:XAR6 ADDCL ACC,@XAR7 ADDUL P,@B0 ; ACC:P = ACC:P + B64 ADDCL ACC,@B1 MOVL @Y0,P ; Store result into Y64 MOVL @Y1,ACC
6-309
ROL ACC
ROL ACC SYNTAX OPTIONS ROL ACC Operands Description

ACC
Rotate Accumulator Left OPCODE

1111 1111 0101 0011
OBJMODE RPT X Y
CYC N+1
Accumulator register Rotate the content of the ACC register left by one bit, filling bit 0 with the content of the carry flag and loading the carry flag with the bit shifted out:
ACC
Rotate Left
ACC
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. The value in bit 31 of the ACC register is transferred to C. The value in C before the rotation is transferred to bit 0 of the ACC. This instruction is repeatable. If the operation follows a RPT instruction, then the ROL instruction will be executed N+1 times. The state of the Z, N, and C flags will reflect the final result.
Z C
Repeat
Example
; Rotate contents of VarA left by 5: MOVL ACC,@VarA ; ACC = VarA RPT #4 ; Repeat next instruction 5 times ||ROL ACC ; Rotate ACC left MOVL @VarA,ACC ; Store result into VarA
6-310
ROR ACC
ROR ACC SYNTAX OPTIONS ROR ACC Operands Description

ACC
Rotate Accumulator Right OPCODE

1111 1111 0101 0010
OBJMODE RPT X Y
CYC N+1
Accumulator register Rotate the content of the ACC register right by one bit, filling bit 31 with the content of the carry flag and loading the carry flag with the bit shifted out:
ACC
Rotate Right
ACC
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. The value in bit 0 of the ACC register is transferred to C. The value in C before the rotation is transferred to bit 31 of the ACC. This instruction is repeatable. If the operation follows a RPT instruction, then the ROR instruction will be executed N+1 times. The state of the Z, N, and C flags will reflect the final result.
Z C
Repeat
Example
; Rotate contents of VarA right by 5: MOVL ACC,@VarA ; ACC = VarA RPT #4 ; Repeat next instruction 5 times ||ROR ACC ; Rotate ACC right MOVL @VarA,ACC ; Store result into VarA
6-311
RPT #8bit/loc16
RPT #8bit/loc16 SYNTAX OPTIONS RPT #8bit RPT loc16 Operands

#8bit loc16
Repeat Next Instruction OPCODE

1111 0110 CCCC CCCC 1111 0111 LLLL LLLL
OBJMODE RPT X X
CYC 1 4
8-bit constant immediate value (0 to 255 range) Addressing mode (see Chapter 5) Repeat the next instruction. An internal repeat counter (RPTC) is loaded with a value N that is either the specified #8bit constant value or the content of the location pointed to by the loc16 addressing mode. After the instruction that follows the RPT is executed once, it is repeated N times; that is, the instruction following the RPT executes N + 1 times. Because the RPTC cannot be saved during a context switch, repeat loops are regarded as multicycle instructions and are not interruptible. Note on syntax: Parallel bars (||) before the repeated instruction are used as a reminder that the instruction is repeated and is not interruptable. When writing inline assembly, use the syntax
asm(|| RPT #8bt/ loc16 || instruction);
Description
Not all instructions are repeatable. If an instruction that is not repeatable follows the RPT instruction, the RPTC counter is reset to 0 and the instruction only executes once. The 28x Assembly Language tools check for this condition and issue warnings. Flags and Modes Repeat Example None
; ; ; ; ; ; Copy the number of elements specified in VarA from Array1 to Array2: int16 Array1[N]; // Located in high 64K of program space int16 Array2[N]; // Located in data space for(i=0; i < VarA; i++) Array2[i] = Array1[i]; MOVL XAR2,#Array2 ; XAR2 = pointer to Array2 RPT @VarA ; Repeat next instruction ; [VarA] + 1 times ; Array2[i] = Array1[i], ; i++
|| XPREAD *XAR2++,*(Array1)
6-312
SAT ACC
SAT ACC SYNTAX OPTIONS SAT ACC Operands Description

ACC
Saturate Accumulator OPCODE

1111 1111 0101 0111
OBJMODE RPT X
CYC 1
Accumulator register Saturate the ACC register to reflect the net overflow represented in the 6-bit overflow counter (OVC):
if( OVC > 0 ) ACC = 0x7FFF FFFF; V = 1; if( OVC < 0 ) ACC = 0x8000 0000; V = 1; if( OVC = 0 ) ACC = unchanged; OVC = 0; V = 0;
Flags and Modes
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. After the operation, the Z flag is set if the ACC is zero, else Z is cleared. C is cleared. If (OVC != 0) at the start of the operation, V is set; otherwise, V is cleared If (OVC > 0) then ACC is saturated to its maximum positive value. If (OVC < 0) then ACC is saturated to its maximum negative value. if (OVC = 0) then ACC is not modified. After the operation, OVC is cleared.
Z C V OVC
Repeat
; Add VarA, VarB and VarC and saturate result and store in VarD: ZAP OVC ; Clear overflow counter MOVL ACC,@VarA ; Load ACC with contents of VarA ADDL ACC,@VarB ; Add to ACC contents of VarB ADDL ACC,@VarC ; Add to ACC contents of VarC SAT ACC ; Saturate ACC based on OVC value MOVL @VarD,ACC ; Store result into VarD
Example
6-313
SAT64 ACC:P
SAT64 ACC:P SYNTAX OPTIONS SAT64 ACC:P Operands Description

ACC:P
Saturate 64-bit Value ACC:P OPCODE

0101 0110 0011 1110
OBJMODE RPT 1
CYC 1
Accumulator register (ACC) and product register (P) Saturate the 64-bit content of the combined ACC:P registers to reflect the net overflow represented in the overflow counter (OVC):
if(OVC > ACC:P V=1; if(OVC < ACC:P V=1; if(OVC = ACC:P OVC = 0; 0) = 0x7FFF FFFF FFFF FFFF; 0) = 0x8000 0000 0000 0000; 0) = unchaged;
Flags and Modes
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the N bit is set; otherwise N is cleared. After the operation, the Z flag is set if the combined 64-bit value of the ACC:P is zero; otherwise, Z is cleared. The C bit is cleared. At the start of the operation, if (OVC = 0) then V is cleared; otherwise, V is set. If (OVC = 0), then no saturation takes place: ACC:P is unchanged. If(OVC > 0), then saturate ACC:P the maximum positive value: ACC:P = 0x7FFF FFFF FFFF FFFF If( OVC < 0), then saturate ACC:P to the maximum negative value: ACC = 0x8000 0000 or ACC:P = 0x8000 0000 0000 0000 At the end of the operation, OVC is cleared.
C V
OVC
Repeat
6-314
SAT64 ACC:P
Example
; Add ZAP MOVL ADDUL ADDUL MOVU
64-bit VarA, VarB and VarC, sat and store result in VarD: OVC ; Clear overflow counter P,@VarA+0 ; Load P with low 32-bits of VarA P,@VarB+0 ; Add to P unsigned low 32-bits of VarB P,@VarC+0 ; Add to P unsigned low 32-bits of VarC @AL,OVC ; Store overlow (repeated carry) in the ACC ; and then add higher portion of the 64 bit ; variables MOVB AH,#0 ; Store overlow (repeated carry) in the ACC ; and then add higher portion of the 64 bit ; variables ZAP OVC ; Clear overflow counter ADDL ACC,@VarA+2 ; Add to ACC with carry high 32-bits of VarA ADDL ACC,@VarB+2 ; Add to ACC with carry high 32-bits of VarB ADDL ACC,@VarC+2 ; Add to ACC with carry high 32-bits of VarC SAT64 ACC:P ; Saturate ACC:P based on OVC value MOVL @VarD+0,P ; Store low 32-bit result into VarD MOVL @VarD+2,ACC ; Store high 32-bit result into VarD
6-315
SB 8bitOffset,COND
SB 8bitOffset,COND
SYNTAX OPTIONS SB 8bitOffset,COND Operands

8bitOffset COND
OPCODE
0110 COND CCCC CCCC
OBJMODE RPT X
CYC 7/4
8-bit signed immediate constant offset value (128 to +127 range) Conditional codes: COND Syntax Description Flags Tested 0000 NEQ Not Equal To Z = 0 0001 EQ Equal To Z = 1 0010 GT Greater Then Z = 0 AND N = 0 0011 GEQ Greater Then Or Equal To N = 0 0100 LT Less Then N = 1 0101 LEQ Less Then Or Equal To Z = 1 OR N = 1 0110 HI Higher C = 1 AND Z = 0 0111 HIS, C Higher Or Same, Carry C = 1 Set 1000 LO, NC Lower, Carry Clear C = 0 1001 LOS Lower Or Same C = 0 OR Z = 1 1010 NOV No Overflow V = 0 1011 OV Overflow V = 1 1100 NTC Test Bit Not Set TC = 0 1101 TC Test Bit Set TC = 1 1110 NBIO BIO Input Equal To Zero BIO = 0 1111 UNC Unconditional
Description
Short conditional branch. If the specified condition is true, then branch by adding the signed 8-bit constant value to the current PC value; otherwise continue execution without branching:
If (COND = true) PC = PC + signed 8-bit offset; If (COND = false) PC = PC + 1; Note: If (COND = true) then the instruction takes 7 cycles. If (COND = false) then the instruction takes 4 cycles. If (COND = UNC) then the instruction takes 4 cycles.
6-316
SBBU ACC,loc16
SBBU ACC,loc16 SYNTAX OPTIONS SBBU ACC,loc16 Operands

ACC loc16
Subtract Unsigned Value Plus Inverse Borrow OPCODE

0001 1101 LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator register Addressing mode (see Chapter 5) Subtract the 16-bit contents of the location pointed to by the loc16 addressing mode, zero extended, and subtract the compliment of the carry flag bit from the ACC register:
ACC = ACC 0:[loc16] ~C;
Description
Flags and Modes
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The state of the carry bit before execution is included in the subtraction. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
V OVC
OVM
Repeat
Example
; Subtract three 32-bit unsigned variables by 16-bit parts: MOVU ACC,@VarAlow ; AH = 0, AL = VarAlow ADD ACC,@VarAhigh << 16 ; AH = VarAhigh, AL = VarAlow SUBU ACC,@VarBlow ; ACC = ACC 0:VarBlow SUB ACC,@VarBhigh << 16 ; ACC = ACC VarBhigh << 16 SBBU ACC,@VarClow ; ACC = ACC VarClow ~Carry SUB ACC,@VarChigh << 16 ; ACC = ACC VarChigh << 16
6-317
SBF 8bitOffset,EQ/NEQ/TC/NTC
SBF 8bitOffset,EQ/NEQ/TC/NTC SYNTAX OPTIONS SBF 8bitOffset,EQ SBF 8bitOffset,NEQ SBF 8bitOffset,TC SBF 8bitOffset,NTC Operands
8bitOffset
Short Branch Fast OPCODE

1110 1100 CCCC CCCC 1110 1101 CCCC CCCC 1110 1110 CCCC CCCC 1110 1111 CCCC CCCC
OBJMODE RPT 1 1 1 1
CYC 4/4 4/4 4/4 4/4
8-bit signed immediate constant offset value (128 to +127 range) Syntax NEQ EQ NTC TC Description Not Equal To Equal To Test Bit Not Set Test Bit Set Flags Tested Z=0 Z=1 TC = 0 TC = 1
Description
Short fast conditional branch. If the specified condition is true, then branch by adding the signed 8-bit constant value to the current PC value; otherwise continue execution without branching:
If (tested condition = true) PC = PC + signed 8-bit offset; If (tested condition = false) PC = PC + 1; Note: The short branch fast (SBF) instruction takes advantage of dual prefetch queue on the C28x core that reduces the cycles for a taken branch from 7 to 4: If (tested condition = true) then the instruction takes 4 cycles. If (tested condition = false) then the instruction takes 4 cycles.
None
6-318
SBRK #8bit
SBRK #8bit SYNTAX OPTIONS SBRK,#8bit Operands Description

#8bit
Subtract From Current Auxiliary Register OPCODE

1111 1101 CCCC CCCC
OBJMODE RPT X
CYC 1
8-bit constant immediate value Subtract the 8-bit unsigned constant from the XARn register pointed to by ARP:
XAR(ARP) = XAR(ARP) 0:8bit;
ARP
The 3-bit ARP points to the current valid auxiliary register, XAR0 to XAR7. This pointer determines which auxiliary register is modified by the operation.
.word 0xEEEE .word 0x0000 TableA: .word 0x1111 .word 0x2222 .word 0x3333 .word 0x4444 FuncA: MOVL MOVZ XAR1,#TableA AR2,*XAR1 ; Initialize XAR1 pointer ; Load AR2 with the 16bit value ; pointed to by XAR1 (0x1111) ; Set ARP = 1
Example
SBRK MOVZ
#2 AR3,*XAR1
; Decrement XAR1 by 2 ; Load AR3 with the 16bit value ; pointed to by XAR1 (0xEEEE)
6-319
SETC Mode
SETC Mode SYNTAX OPTIONS SETC Mode SETC SXM SETC OVM SETC TC SETC C SETC INTM SETC DBGM SETC PAGE0 SETC VMAP Operands Description Mode bit 0 1 2 3 4 5 6 7
Mode
Set Multiple Status Bits OPCODE

0011 1011 CCCC CCCC 0011 1011 0000 0001 0011 1011 0000 0010 0011 1011 0000 0100 0011 1011 0000 1000 0011 1011 0001 0000 0011 1011 0010 0000 0011 1011 0100 0000 0011 1011 1000 0000
OBJMODE RPT X X X X X X X X X
CYC 1,2 1 1 1 1 2 2 1 1
8-bit immediate mask (0x00 to 0xFF) Set the specified status bits. The mode operand is a mask value that relates to the status bits in this way: Status Register ST0 ST0 ST0 ST0 ST1 ST1 ST1 ST1 Flag SXM OVM TC C INTM DBGM PAGE0 VMAP Cycles 1 1 1 1 2 2 1 1
Note: The assembler will accept any number of flag names in any order. For example: SETC INTM,TC ; Set INTM and TC bits to 1 SETC TC,INTM,OVM,C ; Set TC, INTM, OVM, C bits to 1
Flags and Modes
SXM OVM TC C INTM DBGM PAGE0 VMAP
Any of the specified bits can be set by the instruction.
Repeat
6-320
SETC Mode
Example
; Modify flag settings: SETC INTM,DBGM CLRC TC,C,SXM,OVM CLRC #0xFF SETC #0xFF SETC C,SXM,TC,OVM CLRC DBGM,INTM
; ; ; ; ; ;
Set INTM and DBGM bits to 1 Clear TC, C, SXM, OVM bits to 0 Clear all bits to 0 Set all bits to 1 Set TC, C, SXM, OVM bits to 1 Clear INTM and DBGM bits to 0
6-321
SETC M0M1MAP
SETC M0M1MAP SYNTAX OPTIONS SETC M0M1MAP Operands Description

M0M1MAP Status bit
Set the M0M1MAP Status Bit OPCODE

0101 0110 0001 1010
OBJMODE RPT X
CYC 5
Set the M0M1MAP status bit, configuring the mapping of the M0 and M1 memory blocks for C28x/C2XLP operation. The memory blocks are mapped as follows:
Data Space Program Space
M0M1MAP bit
0 (C27x) 1 (C28x/C2XLP)
M0: 0x000 to 0x3FF M1: 0x400 to 0x7FF
M0: 0x400 to 0x7FF M1: 0x000 to 0x3FF M0: 0x000 to 0x3FF M1: 0x400 to 0x7FF
M0M1MAP The M0M1MAP bit is set.
; Set the device mode from reset to C28x: Reset: SETC OBJMODE ; Enable C28x Object Mode CLRC AMODE ; Enable C28x Address Mode .c28_amode ; Tell assembler we are in C28x address mode SETC M0M1MAP ; Enable C28x Mapping Of M0 and M1 blocks . .
Example
6-322
SETC OBJMODE
SETC OBJMODE SYNTAX OPTIONS SETC OBJMODE Operands Description

OBJMODE Status bit
Set the OBJMODE Status Bit OPCODE

0101 0110 0001 1111
OBJMODE RPT X
CYC 5
Set the OBJMODE status bit, putting the device in C28x object mode (supports C2XLP source):
OBJMODE Set the OBJMODE bit.
Reset: SETC OBJMODE CLRC AMODE .c28_amode SETC M0M1MAP . . ; ; ; ; Enable C28x Object Mode Enable C28x Address Mode Tell assembler we are in C28x address mode Enable C28x Mapping Of M0 and M1 blocks
Example
6-323
SETC XF
SETC XF SYNTAX OPTIONS SETC XF Operands Description Flags and Modes Repeat
XF XF
Set XF Bit and Output Signal OPCODE

0101 0110 0010 0110
OBJMODE RPT X
CYC 1
Status bit and output signal Set the XF status bit and pull the corresponding output signal high. The XF status bit is set.
; Pulse XF MOV SB SETC CLRC . . Dest: . signal high if branch not taken: AL,@VarA ; Load AL with contents of VarA Dest,NEQ ; ACC = VarA XF ; Set XF bit and signal high XF ; Clear XF bit and signal low
Example
6-324
SFR ACC,#1..16
SFR ACC,#1..16 SYNTAX OPTIONS SFR ACC,#1..16 Operands

ACC #1..16
Shift Accumulator Right OPCODE

1111 1111 0100 SHFT
OBJMODE RPT X Y
CYC N+1
Accumulator register Shift value Right shift the content of the ACC register by the amount specified in the shift field. The type of shift (arithmetic or logical) is determined by the state of the sign extension mode (SXM) bit:
if(SXM = 1) // sign extension mode enabled ACC = S:ACC >> shift value; // arithmetic shift right else //sign extension mode disabled ACC = 0:ACC >> shift value; // logical shift right
Description
Flags and Modes
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The last bit shifted out is loaded into the C flag bit. If (SXM = 1), then the operation behaves like an arithmetic right shift. If (SXM = 0), then the operation behaves like a logical right shift. This instruction is repeatable. If the operation follows a RPT instruction, then the SFR instruction will be executed N+1 times. The state of the Z, N and C flags will reflect the final result.
N C SXM
Repeat
Example
; Arithmetic shift right contents of VarA by 10: MOVL ACC,@VarA ; ACC = VarA SETC SXM ; Enable sign extension mode SFR ACC,#10 ; Arithmetic shift right ACC by 10 MOVL @VarA,ACC ; Store result into VarA
6-325
SFR ACC,T
SFR ACC,T SYNTAX OPTIONS SFR ACC,T Operands

ACC T
Shift Accumulator Right OPCODE

1111 1111 0101 0001
OBJMODE RPT X Y
CYC N+1
Accumulator register Upper 16-bits of the multiplicand (XT) register Right shift the content of the ACC register by the amount specified in the four least significant bits of the T register, T(3:0) = 0..15. Higher order bits are ignored. The type of shift (arithmetic or logical) is determined by the state of the sign extension mode (SXM) bit:
if(SXM = 1) ACC = S:ACC >> T(3:0); else ACC = 0:ACC >> T(3:0); // // // // sign extension mode enabled arithmetic shift right sign extension mode disabled logical shift right
Description
Flags and Modes
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the zero condition and Z is affected. After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even if the T register specifies a shift of 0, the content of the ACC register is still tested for the negative condition and N is affected. If (T(3:0) = 0) then C is cleared; otherwise, the last bit shifted out is loaded into the C flag bit. if (SXM = 1), then the operation behaves like an arithmetic right shift. If (SXM = 0), then the operation behaves like a logical right shift.
SXM
Repeat
This instruction is repeatable. If the operation follows a RPT instruction, then the SFR instruction will be executed N+1 times. The state of the Z, N and C flags will reflect the final result.
; Arithmetic shift right contents of VarA by VarB: MOVL ACC,@VarA ; ACC = VarA MOV T,@VarB ; T = VarB (shift value) SETC SXM ; Enable sign extension mode SFR ACC,T ; Arithmetic shift right ACC by T(3:0) MOVL @VarA,ACC ; Store result into VarA
Example
6-326
SPM shift
SPM shift SYNTAX OPTIONS SPM +1 SPM 0 SPM 1 SPM 2 SPM 3 SPM 4 (Valid only when AMODE = 0) SPM +4 (Valid only when AMODE = = 1) SPM 5 SPM 6 Operands Description shift OPCODE
1111 1111 0110 1000 1111 1111 0110 1001 1111 1111 0110 1010 1111 1111 0110 1011 1111 1111 0110 1100 1111 1111 0110 1101 1111 1111 0110 1110 1111 1111 0110 1111
Set Product Mode Shift Bits OBJMODE RPT X X X X X X X X CYC 1 1 1 1 1 1 1 1
Product shift mode (+4, +1, 0, 1, 2, 3, 4, 5, 6) Specify a product shift mode. A negative value indicates an arithmetic right shift; positive numbers indicate a logical left shift. The following table shows the relationship between the shift operand and the 3-bit value that gets loaded into the product shift mode (PM) bits in ST0. The address mode bit (AMODE) selects between two types of shift decodes as shown in the table below:
AMODE = 1 AMODE = 0
PM Bits
000 001 010 011 100 101 110 111 Flags and Modes Repeat
PM
SPM +1 SPM 0 SPM 1 SPM 2 SPM 3 SPM +4 SPM 5 SPM 6
SPM +1 SPM 0 SPM 1 SPM 2 SPM 3 SPM 4 SPM 5 SPM 6
PM is loaded with the 3-bit value specified by the selected shift value.
This instruction is not repeatable. If the operation follows a RPT instruction, it resets the repeat counter (RPTC) and executes once.
6-327
SPM shift
Example
; Calculate: Y32 = M16*X16 >> 4 + B32 CLRC AMODE ; Make sure AMODE = SPM 4 ; Set product shift MOV T,@X16 ; T = X16 MPY P,XT,@M16 ; P = X16*M16 MOVL ACC,@B32 ; ACC = B32 ADDL ACC,P << PM ; ACC = ACC + (P >> MOVL @Y32,ACC ; Store result into
0 mode to >> 4
4) Y32
6-328
SQRA loc16
SQRA loc16 SYNTAX OPTIONS SQRA loc16 OPCODE
Square Value and Add P to ACC OBJMODE RPT 1 Y CYC N+1
0101 0110 0001 0101 0000 0000 LLLL LLLL loc16
Addressing mode (see Chapter 5) Add the previous product (stored in the P register), shifted by the amount specified by the product shift mode (PM), to the ACC register. Then the content of the location pointed to by the loc16 addressing mode is loaded into the T register, squared, and stored in the P register:
ACC = ACC + P << PM; T = [loc16]; P = T * [loc16];
Flags and Modes
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag is set if an intermediate overflow occurs.
N C V OVC
OVM
PM
Repeat
6-329
SQRA loc16
Example
; ; ; ; ;
Calculate sum of squares using 16-bit multiply: int16 X[N] ; Data information sum = 0; for(i=0; i < N; i++) sum = sum + (X[i] * X[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #N1 ; Repeat next instruction N times ||SQRA *XAR2++ ; ACC = ACC + P >> 5, ; P = (*XAR2++)^2 ADDL ACC,P << PM ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-330
SQRS loc16
SQRS loc16 SYNTAX OPTIONS SQRS loc16
Square Value and Subtract P From ACC OPCODE

OBJMODE RPT 1 Y
CYC N+1
loc16
Addressing mode (see Chapter 5) Subtract the previous product (stored in the P register), shifted by the amount specified by the product shift mode (PM), from the ACC register. Then the content of the location pointed to by the loc16 addressing mode is loaded into the T register, squared, and stored in the P register:
ACC = ACC P << PM; T = [loc16]; P = T * [loc16];
Flags and Modes
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs.
C V OVC
OVM
PM
Repeat
6-331
SQRS loc16
Example
; ; ; ; ;
Calculate sum of negative squares using 16-bit multiply: int16 X[N] ; Data information sum = 0; for(i=0; i < N; i++) sum = sum (X[i] * X[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #N1 ; Repeat next instruction N times ||SQRS *XAR2++ ; ACC = ACC P >> 5, ; P = (*XAR2++)^2 SUBL ACC,P << PM ; Perform final subtraction MOVL @sum,ACC ; Store final result into sum
6-332
SUB ACC,loc16 << #0...16
SUB ACC,loc16 << #0...16 SYNTAX OPTIONS SUB ACC,loc16 << #0 SUB ACC,loc16 << #1..15
Subtract Shifted Value From Accumulator OPCODE

1010 1110 LLLL LLLL 1000 0000 LLLL LLLL 0101 0110 0000 0000 0000 SHFT LLLL LLLL 1000 SHFT LLLL LLLL
OBJMODE RPT 1 0 1 0 X Y Y Y
CYC N+1 1 N+1 1 N+1
SUB ACC,loc16 << #16 Operands

ACC loc16 #0..16
0000 0100 LLLL LLLL
Accumulator register Addressing mode (see Chapter 5) Shift value (default is << #0 if no value specified) Subtract the left-shifted 16-bit location pointed to by the loc16 addressing mode from the ACC register. The shifted value is sign extended if sign extension mode is turned on (SXM=1) else the shifted value is zero extended (SXM= 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign ACC = ACC S:[loc16] << else // sign ACC = ACC 0:[loc16] << extension mode enabled shift value; extension mode disabled shift value;
Description
Flags and Modes
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else Z is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. Exception: If a shift of 16 is used, the SUB instruction can clear C but not set it.
V OVC
If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the addition. Else, the value will be zero extended.
SXM
6-333
SUB ACC,loc16 << #0...16
OVM
If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFF FFFF) or maximum negative (0x8000 0000) if the operation overflowed. If the operation is repeatable, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled. If the operation is not repeatable, the instruction will execute only once.
Repeat
Example
; Calculate signed value: ACC = (VarA << 10) (VarB << 6); SETC SXM ; Turn sign extension mode on MOV ACC,@VarA << #10 ; Load ACC with VarA left shifted by 10 SUB ACC,@VarB << #6 ; Subtract VarB left shifted by 6 to ACC0
6-334
SUB ACC,loc16 <<T
SUB ACC,loc16 <<T SYNTAX OPTIONS SUB ACC,loc16 <<T Operands

ACC loc16 T

0101 0110 0010 0111 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Upper 16bits of the multiplicand register, XT(31:16) Subtract from the ACC register the leftshifted contents of the 16-bit location pointed to by the loc16 addressing mode. The shift value is specified by the four least significant bits of the T register, T(3:0) = shift value = 0..15. Higher order bits are ignored. The shifted value is sign extended if sign extension mode is turned on (SXM=1) else the shifted value is zero extended (SXM=0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign ACC = ACC S:[loc16] << else // sign ACC = ACC 0:[loc16] << extension mode enabled T(3:0); extension mode disabled T(3:0);
Description
Flags and Modes
Z N C V OVC
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the addition. Else, the value will be zero extended. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFF FFFF) or maximum negative (0x8000 0000) if the operation overflowed. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
SXM
OVM
Repeat
6-335
SUB ACC,loc16 <<T
Example
; Calculate signed value: ACC = (VarA << SB) (VarB << SB) SETC SXM ; Turn sign extension mode on MOV T,@SA ; Load T with shift value in SA MOV ACC,@VarA << T ; Load in ACC shifted contents of VarA MOV T,@SB ; Load T with shift value in SB SUB ACC,@VarB << T ; Subtract from ACC shifted contents ; of VarB
6-336
SUB ACC,#16bit << #0..15
SUB ACC,#16bit << #0..15 SYNTAX OPTIONS SUB ACC,#16bit << #0..15 Operands
ACC #16bit #0..15

OBJMODE RPT X
CYC 1
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Subtract the left shifted 16-bit immediate constant value from the ACC register. The shifted value is sign extended if sign extension mode is turned on (SXM=1) else the shifted value is zero extended (SXM=0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled ACC = ACC S:16bit << shift value; else // sign extension mode disabled ACC = ACC 0:16bit << shift value;
Description
Smart Encoding: If #16bit is an 8-bit number and the shift is zero, then the assembler will encode this instruction as SUBB ACC, #8bit for improved efficiency. To override this encoding, use the SUBW ACC, #16bit instruction alias. Flags and Modes
Z N C V OVC
SXM
OVM
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If sign extension mode bit is set; then the 16-bit operand, addressed by the loc16 field, will be sign extended before the addition. Else, the value will be zero extended. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat Example
; Calculate signed value: ACC = (VarB << 10) (23 << 6); SETC SXM ; Turn sign extension mode on MOV ACC,@VarB << #10 ; Load ACC with VarB left shifted by 10 SUB ACC,#23 << #6 ; Subtract from ACC 23 left shifted by 6
6-337
SUB AX, loc16
SUB AX, loc16 SYNTAX OPTIONS SUB AX, loc16 Operands

AX loc16
Subtract Specified Location From AX OPCODE

1001 111A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Subtract the 16bit content of the location pointed to by the loc16 addressing mode from the specified AX register (AH or AL) and store the results in AX:
AX = AX [loc16];
Description
Flags and Modes
After the subtraction, AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set; otherwise it is cleared. After the subtraction, AX is tested for a zero condition. The zero flag bit is set if the operation generates AX = 0, otherwise it is cleared If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Subtract the contents of VarA with VarB and store in VarC MOV AL,@VarA ; Load AL with contents of VarA SUB AL,@VarB ; Subtract from AL contents of VarB MOV @VarC,AL ; Store result in VarC
6-338
SUB loc16, AX
SUB loc16, AX SYNTAX OPTIONS SUB loc16, AX Operands

loc16 AX
Reverse-Subtract Specified Location From AX OPCODE

0111 010A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Subtract the content of the specified AX register (AH or AL) from the 16-bit content of the location pointed to by the loc16 addressing mode and store the result in location pointed to by loc16:
[loc16] = [loc16] AX;
Description
Flags and Modes
After the subtraction, [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set; otherwise it is cleared. After the subtraction, [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0; otherwise it is cleared If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Subtract the contents of VarA from index register AR0: MOV AL,@VarA ; Load AL with contents of VarA SUB @AR0,AL ; AR0 = AR0 AL ; Subtract the contents of VarB from VarC: MOV AH,@VarB ; Load AH with contents of VarB SUB @VarC,AH ; VarC = VarC AH
6-339
SUBB ACC,#8bit
SUBB ACC,#8bit SYNTAX OPTIONS SUBB ACC,#8bit Operands

ACC #8bit
Subtract 8-bit Value OPCODE

0001 1001 CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator register 8-bit immediate constant value Subtract the zeroextended, 8-bit constant from the ACC register:
ACC = ACC 0:8bit;
Description
Flags and Modes
Z N C V OVC
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise, V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
OVM
Repeat
Example
; Decrement contents of 32-bit location VarA:

MOVL SUBB MOVL ACC,@VarA ACC,#1 @VarA,ACC ; Load ACC with contents of VarA ; Subtract 1 from ACC ; Store result back into VarA
6-340
SUBB SP,#7bit
SUBB SP,#7bit SYNTAX OPTIONS SUBB SP,#7bit Operands

SP #7bit
OPCODE
1111 1110 1CCC CCCC
OBJMODE RPT X
CYC 1
Stack pointer 7-bit immediate constant value Subtract a 7-bit unsigned constant from SP and store the result in SP:
SP = SP 0:7bit;
Description
None
FuncA: ADDB SP,#N ; ; ; ; Function with local variables on stack. Reserve N 16bit words of space for local variables on stack:
Example
. . . SUBB SP,#N LRETR
; Deallocate reserved stack space. ; Return from function.
6-341
SUBB XARn,#7bit
SUBB XARn,#7bit SYNTAX OPTIONS SUBB XARn, #7bit Operands

XARn #7bit
Subtract 7-Bit From Auxiliary Register OPCODE

1101 1nnn 1CCC CCCC
OBJMODE RPT X
CYC 1
XAR0 to XAR7, 32-bit auxiliary registers 7bit immediate constant value Subtract the 7bit unsigned constant from XARn and store the result in XARn:
XARn = XARn 0:7bit;
Description
None
MOVL XAR1,#VarA MOVL XAR2,*XAR1 SUBB XAR2,#10h ; Initialize XAR1 pointer with address ; of VarA ; Load XAR2 with contents of VarA ; XAR2 = VarA 0x10
Example
6-342
SUBBL ACC, loc32
SUBBL ACC, loc32 SYNTAX OPTIONS SUBBL ACC, loc32 Operands

loc32 ACC
Subtract 32-bit Value Plus Inverse Borrow OPCODE

0101 0110 0101 0100 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator register Subtract from the ACC the 32-bit location pointed to by the loc32 addressing mode and the logical inversion of the value in the carry flag bit:
ACC = ACC [loc32] ~C;
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The state of the carry bit before execution is included in the subtraction. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
V OVC
OVM
Repeat
6-343
SUBBL ACC, loc32
Example
; Subtract two 64-bit values (VarA and VarB) and store result ; in VarC: MOVL ACC,@VarA+0 ; Load ACC with contents of the low ; 32-bits of VarA SUBUL ACC,@VarB+0 ; Subtract from ACC the contents of ; the low 32-bits of VarB MOVL @VarC+0,ACC ; Store low 32-bit result into VarC MOVL ACC,@VarA+2 ; Load ACC with contents of the high ; 32-bits of VarA SUBBL ACC,@VarB+2 ; Subtract from ACC the contents of ; the high 32-bits of VarB with borrow MOVL @VarC+2,ACC ; Store high 32-bit result into VarC
6-344
SUBCU ACC,loc16
SUBCU ACC,loc16 SYNTAX OPTIONS SUBCU ACC,loc16 Operands

ACC loc32
Subtract Conditional 16 Bits OPCODE

0001 1111 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Perform 16-bit conditional subtraction, which can be used for unsigned modulus division:
temp(32:0) = ACC << 1 [loc16] << 16 if( temp(32:0) >= 0 ) ACC = temp(31:0) + 1 else ACC = ACC << 1
Description
To perform 16-bit unsigned modulus division, the AH register is zeroed and the AL register is loaded with the Numerator value prior to executing the SUBCU instruction. The value pointed to be the loc16 addressing mode contains the Denominator value. After executing the SUBCU instruction 16 times, the AH register will contain the Remainder and the AL register will contain the Quotient results. To perform signed modulus division, the Numerator and Denominator values must be converted to unsigned quantities, before executing the SUBCU instruction. The final Quotient result must be negated if the Numerator and Denominator values were of different sign else the quotient is left unchanged. Flags and Modes
Z N C
At the end of the operation, the Z flag is set if the ACC value is zero, else Z is cleared. The calculation of temp(32:0) has no effect on the Z bit. At the end of the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The calculation of temp(32:0) has no effect on the N bit. If the calculation of temp(32:0) generates a borrow, C is cleared; otherwise C is set.
Note: The V and OVC flags are not affected by the operation.
Repeat
If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
; Calculate unsigned: Quot16 = Num16Den16, Rem16 = Num16%Den16 MOVU ACC,@Num16 ; AL = Num16, AH = 0 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@Den16 ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV @Quot16,AL ; Store quotient in Quot16
Example 1
6-345
SUBCU ACC,loc16
Example 2
; Calculate signed: Quot16 = Num16Den16, Rem16 = Num16%Den16 CLRC TC ; Clear TC flag, used as sign flag MOV ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOV T,@AH ; Temp save Den16 in T register MOV ACC,@Num16 << 16 ; AH = Num16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOVU ACC,@AH ; AH = 0, AL = Num16 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@T ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV ACC,@AL << 16 ; AH = Quot16, AL = 0 NEGTC ACC ; Negate if TC = 1 MOV @Quot16,AH ; Store quotient in Quot16 ; Calculate unsigned: Quot32 = Num32/Den16, Rem16 = Num32%Den16 MOVU ACC,@Num32+1 ; AH = 0, AL = high 16-bits of Num32 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@Den16 ; Conditional subtract with Den16 MOV @Quot32+1,AL ; Store high 16-bit in Quot32 MOV AL,@Num32+0 ; AL = low 16-bits of Num32 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@Den16 ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV @Quot32+0,AL ; Store low 16-bit in Quot32 ; Calculate signed: Quot32 = Num32/Den16, Rem16 = Num32%Den16 CLRC TC ; Clear TC flag, used as sign flag MOV ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ACC ; Take abs value, TC = sign ^ TC MOV T,@AH ; Temp save Den16 in T register MOVL ACC,@Num32 ; ACC = Num32 ABSTC ACC ; Take abs value, TC = sign ^ TC MOV P,@ACC ; P = Num32 MOVU ACC,@PH ; AH = 0, AL = high 16-bits of Num32 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@T ; Conditional subtract with Den16 MOV @Quot32+1,AL ; Store high 16-bit in Quot32 MOV AL,@PL ; AL = low 16-bits of Num32 RPT #15 ; Repeat operation 16 times ||SUBCU ACC,@T ; Conditional subtract with Den16 MOV @Rem16,AH ; Store remainder in Rem16 MOV ACC,@AL << 16 ; AH = low 16-bits of Quot32, AL = 0 NEGTC ACC ; Negate if TC = 1 MOV @Quot32+0,AH ; Store low 16-bit in Quot32
Example 3
Example 4
6-346
SUBCUL ACC,loc32
SUBCUL ACC,loc32 SYNTAX OPTIONS SUBCUL ACC,loc32 Operands

ACC loc32
Subtract Conditional 32 Bits OPCODE

0101 0110 0001 0111 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Perform 32-bit conditional subtraction, which can be used for unsigned modulus division:
temp(32:0) = ACC << 1 + P(31) [loc32]; if( temp(32:0) >= 0 ) ACC = temp(31:0); P = (P << 1) + 1; else ACC:P = ACC:P << 1;
Description
To perform 32-bit unsigned modulus division, the ACC register is zeroed and the P register is loaded with the Numerator value prior to executing the SUBCUL instruction. The value pointed to be the loc32 addressing mode contains the Denominator value. After executing the SUBCUL instruction 32 times, the ACC register will contain the Remainder and the P register will contain the Quotient results. To perform signed modulus division, the Numerator and Denominator values must be converted to unsigned quantities, before executing the SUBCUL instruction. The final Quotient result must be negated if the Numerator and Denominator values were of different sign else the quotient is left unchanged. Flags and Modes
Z
At the end of the operation, the Z flag is set if the ACC value is zero, else Z is cleared. The calculation of temp(32:0) has no effect on the Z bit. At the end of the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. The calculation of temp(32:0) has no effect on the N bit. If the calculation of temp(32:0) generates a borrow, C is cleared; otherwise C is set.
Note: The V and OVC flags are not affected by the operation.
Repeat
If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
6-347
SUBCUL ACC,loc32
Example 1
; Calculate unsigned: Quot32 = Num32/Den32, Rem32 = Num32%Den32 MOVB ACC,#0 ; Zero ACC MOVL P,@Num32 ; Load P register with Num32 RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@Den32 ; Conditional subtract with Den32 MOVL @Rem32,ACC ; Store remainder in Rem32 MOVL @Quot32,P ; Store quotient in Quot32 ; Calculate signed: Quot32 = Num32/Den32, Rem32 = Num32%Den32 CLRC TC ; Clear TC flag, used as sign flag MOVL ACC,@Den32 ; Load ACC with contents of Den32 ABSTC ACC ; Take absolute value, TC = sign ^ TC MOVL XT,@ACC ; Temp save denominator in XT register MOVL ACC,@Num32 ; Load ACC register with Num32 ABSTC ACC ; Take abs value, TC = sign ^ TC MOVL P,@ACC ; Load P register with numerator MOVB ACC,#0 ; Zero ACC RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@XT ; Conditional subtract with denominator MOVL @Rem32,ACC ; Store remainder in Rem32 MOVL ACC,@P ; Load ACC with quotient NEGTC ACC ; Negate ACC if TC=1 (negative result) MOVL @Quot32,ACC ; Store quotient in Quot32 ; Calculate unsigned: Quot64 = Num64Den32, Rem32 = Num64%Den32 MOVB ACC,#0 ; Zero ACC MOVL P,@Num64+2 ; Load P with high 32-bits of Num64 RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@Den32 ; Conditional subtract with Den32 MOVL @Quot64+2,P ; Store high 32 bit quotient in Quot64 MOVL P,@Num64+0 ; Load P with low 32-bits of Num64 RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@Den32 ; Conditional subtract with Den32 MOVL @Rem32,ACC ; Store remainder in Rem32 MOVL @Quot64+0,P ; Store low 32 bit quotient in Quot64
Example 2
Example 3
6-348
SUBCUL ACC,loc32
Example 4
; Calculate signed: Quot64 = Num364Den32, Rem32 = Num64%Den32 MOVL ACC,@Num64+2 ; Load ACC:P with 64-bit numerator MOVL P,@Num64+0 TBIT @AH,#15 ; TC = sign of numerator SBF $10,NTC ; Take absolute value of numerator NEG64 ACC:P $10: MOVL @XAR3,P ; Temp save numerator low in XAR3 MOVL P,@ACC ; Load P register with numerator high MOVL ACC,@Den32 ; Load ACC with contents of Den32 ABSTC ACC ; Take absolute value, TC = sign ^ TC MOVL XT,@ACC ; Temp save denominator in XT register MOVB ACC,#0 ; Zero ACC RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@XT ; Conditional subtract with denominator MOVL @XAR4,P ; Store high quotient in XAR4 MOVL P,@XAR3 ; Load P with low numerator RPT #31 ; Repeat operation 32 times ||SUBCUL ACC,@XT ; Conditional subtract with denominator MOVL @Rem32,ACC ; Store remainder in Rem32 MOVL ACC,@XAR4 ; Load ACC with high quotient from XAR4 SBF $20,NTC ; Take absolute value of quotient NEG64 ACC:P $20: MOVL @Quot64+0,P ; Store low quotient into Quot64 MOVL @Quot64+2,ACC ; Store high quotient into Quot64
6-349
SUBL ACC, loc32
SUBL ACC, loc32 SYNTAX OPTIONS SUBL ACC, loc32 Operands

ACC loc32

0000 0011 LLLL LLLL
OBJMODE RPT 1
CYC 1
Accumulator register Addressing mode (see Chapter 5) Subtract the 32-bit location pointed to by the loc32 addressing mode from the ACC register :
ACC = ACC [loc32];
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If OVM = 0 (disabled), then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If OVM = 1 (enabled), then the counter is not affected by the operation.
C V OVC
OVM
If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Calculate the 32-bit value: VarC = VarAVarB MOVL ACC,@VarA ; Load ACC with contents of VarA SUBL ACC,@VarB ; Subtract from ACC the contents of VarB MOVL @VarC,ACC ; Store result into VarC
6-350
SUBL ACC,P << PM
SUBL ACC,P << PM SYNTAX OPTIONS SUBL ACC,P << PM OPCODE

0001 0001 1010 1100
Subtract 32-bit Value OBJMODE RPT X Y CYC N+1
Note: This instruction is an alias for the MOVS T,loc16 operation with loc16 = @T addressing mode.
Operands
ACC P <<PM
Accumulator register Product register Product shift mode Subtract the content of the P register, shifted as specified by the product shift mode (PM), from the content of the ACC register:
ACC = ACC P << PM;
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If OVM = 0 (disabled) and the operation generates a positive overflow, the counter is incremented; if the operation generates a negative overflow, the counter is decremented. If OVM = 1 (enabled), the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
C V OVC
OVM
PM
Repeat
6-351
SUBL ACC,P << PM
Example
; Calculate: Y = ((B << 11) ; Y, M, X, B are Q15 values SPM 4 SETC SXM MOV T,@M MPY P,T,@X MOV ACC,@B << 11 SUBL ACC,P << PM MOVH @Y,ACC << 5
(M*X >> 4)) >> 10 ; ; ; ; ; ; ; Set product shift to >> 4 Enable sign extension mode T = M P = M * X ACC = S:B << 11 ACC = (S:B << 11) (M*X >> 4) Store Q15 result into Y
6-352
SUBL loc32, ACC
SUBL loc32, ACC SYNTAX OPTIONS SUBL loc32, ACC Operands

loc32 ACC

0101 0110 0100 0001 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator register Subtract the content of the ACC register from the location pointed to by the loc32 addressing mode:
[loc32] = [loc32] ACC;
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the [loc32] is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If OVM = 0 (disabled) and the operation generates a positive overflow, the counter is incremented and if the operation generates a negative overflow, the counter is decremented. If OVM = 1 (enabled) the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V OVC
OVM
Repeat
Example
; Decrement the 32-bit value VarA: MOVB ACC,#1 ; Load ACC with 0x00000001 SUBL @VarA,ACC ; VarA = VarA ACC
6-353
SUBR loc16,AX
SUBR loc16,AX SYNTAX OPTIONS SUBR loc16,AX Operands

loc16 AX
Reverse-Subtract Specified Location From AX OPCODE

1110 101A LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Subtract the 16bit content of the location pointed to by the loc16 addressing mode from the specified AX register (AH or AL), and store the result in location pointed to by loc16:
[loc16] = AX [loc16]
Description

N
After the subtraction, [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set; otherwise it is cleared. After the subtraction, [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0, otherwise it is cleared If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. Signed positive overflow occurs if the result crosses the max positive value (0x7FFF) in the positive direction. Signed negative overflow occurs if the result crosses the max negative value (0x8000) in the negative direction. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V
Repeat
Example
; Subtract index register AR0 from VarA and store in AR0: MOV AL,@VarA ; Enable ; Load AL with contents of VarA sign extensio ; with a left shift of 3 SUBR @AR0,AL ; AR0 = AL AR0 ; Subtract the contents of VarC from VarB and store in VarC: MOV AH,@VarB ; Load AH with contents of VarB SUBR @VarC,AH ; VarC = AH VarC
6-354
SUBRL loc32, ACC
SUBRL loc32, ACC SYNTAX OPTIONS SUBRL loc32, ACC Operands

loc32 ACC
Reverse-Subtract Specified Location From ACC OPCODE

0101 0110 0100 1001 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator register Subtract from the ACC register the 32-bit location pointed to by the loc32 addressing mode and store the result in the location pointed to by loc32:
[loc32] = ACC [loc32];
Description
Flags and Modes
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If(OVM = 0, disabled) then if the operation generates a positive overflow, then the counter is incremented and if the operation generates a negative overflow, then the counter is decremented. If(OVM = 1, enabled) then the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
C V OVC
OVM
Repeat
Example
; Calculate the 32-bit value: VarA = VarB VarA MOVL ACC,@VarB ; Load ACC with contents of VarB SUBRL @VarA,ACC ; VarA = ACC VarA
6-355
SUBU ACC, loc16
SUBU ACC, loc16 SYNTAX OPTIONS SUBU ACC, loc16 Operands

ACC loc16
Subtract Unsigned 16-bit Value OPCODE

0000 0001 LLLL LLLL
OBJMODE RPT X Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Subtract the 16-bit contents of the location pointed to by the loc16 addressing mode from the ACC register. The addressed location is zero extended before the add:
ACC = ACC 0:[loc16];
Description
Flags and Modes
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. If OVM = 0 (disabled) and the operation generates a positive overflow, the counter is incremented and if the operation generates a negative overflow, the counter is decremented. If OVM = 1 (enabled), the counter is not affected by the operation. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. If this operation is repeated, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
C V OVC
OVM
Repeat
Example
; Subtract three 32-bit unsigned variables by 16-bit parts: MOVU ACC,@VarAlow ; AH = 0, AL = VarAlow ADD ACC,@VarAhigh << 16 ; AH = VarAhigh, AL = VarAlow SUBU ACC,@VarBlo293w ; ACC = ACC 0:VarBlow SUB ACC,@VarBhigh << 16 ; ACC = ACC VarBhigh << 16 SBBU ACC,@VarClow ; ACC = ACC VarClow ~Carry SUB ACC,@VarChigh << 16 ; ACC = ACC VarChigh << 16
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SUBUL ACC, loc32
SUBUL ACC, loc32 SYNTAX OPTIONS SUBUL ACC, loc32 Operands

loc32 ACC
Subtract Unsigned 32-bit Value OPCODE

0101 0110 0101 0101 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Addressing mode (see Chapter 5) Accumulator register Subtract from the ACC register the 32-bit the location pointed to by the loc32 addressing mode. The subtraction is treated as an unsigned SUBL operation:
ACC = ACC [loc32]; // unsigned subtraction
Description
Note: The difference between a signed and unsigned 32-bit subtract is in the treatment of the overflow counter (OVC). For a signed SUBL, the OVC counter monitors positive/negative overflow. For an unsigned SUBL, the OVC unsigned (OVCU) counter monitors the borrow.
Flags and Modes
Z N C V OVCU
After the subtraction, the Z flag is set if the ACC value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If an overflow occurs, V is set; otherwise V is not affected. The overflow counter is decremented whenever a subtraction operation generates an unsigned borrow. The OVM mode does not affect the OVCU counter. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Subtract two 64-bit values (VarA and VarB) and store result ; in VarC: MOVL ACC,@VarA+0 ; Load ACC with contents of the low ; 32-bits of VarA SUBUL ACC,@VarB+0 ; Subtract from ACC the contents of ; the low 32-bits of VarB MOVL @VarC+0,ACC ; Store low 32-bit result into VarC MOVL ACC,@VarA+2 ; Load ACC with contents of the high ; 32-bits of VarA SUBBL ACC,@VarB+2 ; Subtract from ACC the contents of ; the high 32-bits of VarB with borrow MOVL @VarC+2,ACC ; Store high 32-bit result into VarC
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SUBUL P,loc32
SUBUL P,loc32 SYNTAX OPTIONS SUBUL P,loc32 OPCODE
Subtract Unsigned 32-bit Value OBJMODE RPT 1 CYC 1
0101 0110 0101 1101 0000 0000 LLLL LLLL
Operands
P loc32
Product register Addressing mode (see Chapter 5) Subtract from the P register the 32-bit content of the location pointed to by the loc32 addressing mode. The addition is treated as an unsigned SUB operation:
P = P [loc32]; // unsigned subtract
Description
Note: The difference between a signed and unsigned 32-bit subtract is in the treatment of the overflow counter (OVC). For a signed SUBL, the OVC counter monitors positive/negative overflow. For an unsigned SUBL, the OVC unsigned (OVCU) counter monitors the borrow.
Flags and Modes
After the subtraction, the Z flag is set if the P value is zero, else Z is cleared. After the subtraction, the N flag is set if bit 31 of P is 1, else N is cleared. If the subtraction generates a borrow, C is cleared; otherwise C is set. If a signed overflow occurs, V is set; otherwise V is not affected. The overflow counter is decremented whenever a subtraction operation generates an unsigned borrow. The OVM mode does not affect the OVCU counter. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
N C V OVCU
Repeat
Example
; Subtract 64-bit VarA VarB and store result in VarC: MOVL P,@VarA+0 ; Load P with low 32-bits of VarA MOVL ACC,@VarA+2 ; Load ACC with high 32-bits of VarA SUBUL P,@VarB+0 ; Sub from P unsigned low 32-bits of VarB SUBBL ACC,@VarB+2 ; Sub from ACC with borrow high 32-bits of VarB MOVL @VarC+0,P ; Store low 32-bit result into VarC MOVL @VarC+2,ACC ; Store high 32-bit result into VarC
6-358
TBIT loc16,#bit
TBIT loc16,#bit SYNTAX OPTIONS TBIT loc16,#16bit Operands

loc16 #bit
Test Specified Bit OPCODE

0100 BBBB LLLL LLLL Addressing mode (see Chapter 5) Immediate constant bit index from 0 to 15
OBJMODE RPT X
CYC 1
Description
Test the specified bit of the data value in the location pointed to by the loc16 addressing mode:
TC = [loc16(bit)];
The value specified for the #bit immediate operand directly corresponds to the bit number. For example, if #bit = 0, you will access bit 0 (least significant bit) of the addressed location; if #bit = 15, you will access bit 15 (most significant bit). Flags and Modes Repeat
TC If the bit tested is 1, TC is set; if the bit tested is 0, TC is cleared.
; if( VarA.Bit4 = 1 ) ; VarB.Bit6 = 1; ; else ; VarB.Bit6 = 0; TBIT @VarA,#4 SB $10,NTC TSET @VarB,#6 SB $20,UNC $10: TCLR @VarB,#6 $20:
Example
; ; ; ; ; ; ;
Test bit 4 of VarA contents Branch if TC = 0 Set bit 6 of VarB contents Branch unconditionally Clear bit 6 of VarB contents
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TBIT loc16,T
TBIT loc16,T SYNTAX OPTIONS TBIT loc16,T Operands

loc16 T
Test Bit Specified by Register OPCODE

0101 0110 0010 0101 0000 0000 LLLL LLLL Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register (XT)
OBJMODE RPT 1
CYC 1
Description
Test the bit specified by the four least significant bits of the T register, T(3:0) = 015 of the data value in the location pointed to by the loc16 addressing mode. Upper bits of the T register are ignored:
bit = 15 T(3:0); TC = [loc16(bit)];
A value of 15 in the T register corresponds to bit 0 (least significant bit). A value of 0 in the T register corresponds to bit 15 (most significant bit). The upper 12 bits of the T register are ignored. Flags and Modes Repeat
TC If the bit tested is 1, TC is set; if the bit tested is 0, TC is cleared.
; if( VarA.VarB = 1 ) ; VarC.Bit6 = 1; ; else ; VarC.Bit6 = 0; MOV T,@VarB XOR @T,#15 TBIT @VarA,T SB $10,NTC TSET @VarB,#6 SB $20,UNC $10: TCLR @VarB,#6 $20:
Example
; ; ; ; ; ; ; ; ;
Load T with bit value in VarB Reverse order of bit testing Test bit of VarA selected by VarB Branch if TC = 0 Set bit 6 of VarB contents Branch unconditionally Clear bit 6 of VarB contents
6-360
TCLR loc16,#bit
TCLR loc16,#bit SYNTAX OPTIONS TCLR loc16,#bit Operands

loc16, #bit
Test and Clear Specified Bit OPCODE

0101 0110 0000 1001 0000 BBBB LLLL LLLL Addressing mode (see Chapter 5) Immediate constant bit index from 0 to 15
OBJMODE RPT 1
CYC 1
Description
Test the specified bit of the data value in the location pointed to by the loc16 addressing mode and then clear that same bit to 0:
TC = [loc16(bit)]; [loc16(bit)] = 0;
The value specified for the #bit immediate operand directly corresponds to the bit number. For example, if #bit = 0, you will access bit 0 (least significant bit) of the addressed location; if #bit = 15, you will access bit 15 (most significant bit). TCLR performs a read-modify-write operation. Flags and Modes
N If (loc16 = @AX) and bit 15 (MSB) of @AX is 1, then N flag is set..
Z TC
If (loc16 = @AX) and @AX gets zeroed out, then Z flag is set. If the bit tested is 1, TC is set; if the bit tested is 0, TC is cleared.
Repeat
Example
; ; ; ; ; ; ;
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TEST ACC
TEST ACC SYNTAX OPTIONS TEST ACC Operands Description

ACC
Test for Accumulator Equal to Zero OPCODE

1111 1111 0101 1000
OBJMODE RPT X
CYC 1
Accumulator register Compare the ACC register to zero and set the status flag bits accordingly:
Modify flags on (ACC 0x00000000);
Flags and Modes
If bit 31 of the ACC is 1, N is set; else N is cleared. If ACC is zero, Z is set; else Z is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Test contents of ACC and branch if zero: TEST ACC ; Modify flags on (ACC 0x00000000) SB Zero,EQ ; Branch if zero
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TRAP #VectorNumber
TRAP #VectorNumber SYNTAX OPTIONS TRAP #VectorNumber Operands

Vector Number
Software Trap OPCODE

0000 0000 001C CCCC CPU interrupt vector 0 to 31
OBJMODE RPT X
CYC 8
Description
The TRAP instruction transfers program control to the interrupt service routine that corresponds to the vector specified in the instruction. It does not affect the interrupt flag register (IFR) or the interrupt enable register (IER), regardless of whether the chosen interrupt has corresponding bits in these registers. The TRAP instruction is not affected by the interrupt global mask bit (INTM) in status register ST1. It also is not affected by the enable bits in the IER or the debug interrupt enable register (DBGIER). Once the TRAP instruction reaches the decode phase of the pipeline, hardware interrupts cannot be serviced until the TRAP instruction is done executing (until the interrupt service routine begins). The following table indicates which interrupt vector is associated with a chosen value for the VectorNumber operand:
Vector Number
Interrupt Vector
Vector Number
Interrupt Vector
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RESET INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 DLOGINT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RTOSINT Reserved NMI ILLEGAL USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 USER10 USER11 USER12
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TRAP #VectorNumber
Part of the operation involves saving pairs of 16-bit core registers onto the stack pointed to by the SP register. Each pair of registers is saved in a single 32-bit operation. The register forming the low word of the pair is saved first (to an even address); the register forming the high word of the pair is saved next (to the following odd address). For example, the first value saved is the concatenation of the T register and the status register ST0 (T:ST0). ST0 is saved first, then T. This instruction should not be used with vectors 112 when the peripheral interrupt expansion (PIE) is enabled.
Note: The TRAP #0 instruction does not initiate a full reset. It only forces execution of the interrupt service routine that corresponds to the RESET interrupt vector. Flush the pipeline; temp = PC + 1; Fetch specified vector; SP = SP + 1; [SP] = T:ST0; SP = SP + 2; [SP] = AH:AL; SP = SP + 2; [SP] = PH:PL; SP = SP + 2; [SP] = AR1:AR0; SP = SP + 2; [SP] = DP:ST1; SP = SP + 2; [SP] = DBGSTAT:IER; SP = SP + 2; [SP] = temp; SP = SP = 2; INTM = 0; // disable INT1INT14, DLOGINT, RTOSINT DBGM = 1; // disable debug events EALLOW = 0; // disable access to emulation registers LOOP = 0; // clear loop flag IDLESTAT = 0; // clear idle flag PC = fetched vector;
Flags and Modes
DBGM INTM EALLOW LOOP IDLESTAT
Debug events are disabled by setting the DBGM bit. Setting the INTM bit disables maskable interrupts. EALLOW is cleared to disable access to protected registers. The loop flag is cleared. The idle flag is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
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TSET loc16,#16bit
TSET loc16,#16bit SYNTAX OPTIONS TSET loc16,#16bit OPCODE

0101 0110 0000 1101 0000 BBBB LLLL LLLL
Test and Set Specified Bit OBJMODE RPT 1 CYC 1
Operands
loc16 #bit
Addressing mode (see Chapter 5)
Immediate constant bit index from 0 to 15 Description Test the specified bit of the data value in the location pointed to by the loc16 addressing mode and then set the same bit to 1:
TC = [loc16(bit)]; [loc16(bit)] = 1;
The value specified for the #bit immediate operand directly corresponds to the bit number. For example, if #bit = 0, you will access bit 0 (least significant bit) of the addressed location; if #bit = 15, you will access bit 15 (most significant bit). TSET performs a read-modify-write operation. Flags and Modes
Z TC N
If (loc16 = = @AX) and bit 15 (MSB) of @AX is 1, then N flag is set..
If (loc16 = = @AX) and @AX gets zeroed out, then Z flag is set. If the bit tested is 1, TC is set; if the bit tested is 0, TC is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; ; ; ; ; ; ;
6-365
UOUT *(PA),loc16
UOUT *(PA),loc16 SYNTAX OPTIONS UOUT *(PA),loc16 Operands

*(PA) loc16
Unprotected Output Data to I/O Port OPCODE

OBJMODE RPT 1 Y
CYC N+2
Immediate I/O space memory address Addressing mode (see Chapter 5)
Description
Store the 16-bit value from the location pointed to by the loc16 addressing mode into the I/O space location pointed to by *(PA):
IOspace[0x000:PA] = loc16;
I/O Space is limited to 64K range (0x0000 to 0xFFFF). On the external interface (XINTF), if available on a particular device, the I/O strobe signal (XISn) is toggled during the operation. The I/O address appears on the lower 16 address lines (XA(15:0)) and the upper address lines are zeroed. The data appears on the lower 16 data lines (XD(15:0).
Note: The UOUT operation is not pipeline protected. Therefore, if an IN instruction immediately follows a UOUT instruction, the IN will occur before the UOUT. To be certain of the sequence of operation, use the OUT instruction, which is pipeline protected. I/O space may not be implemented on all C28x devices. See the data sheet for your particular device for details.
None
This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *(PA) I/O space address is post-incremented by 1 during each repetition.
6-366
UOUT *(PA),loc16
Example
; IORegA address = 0x0300; ; IOREgB address = 0x0301; ; IOREgC address = 0x0302; ; IORegA = 0x0000; ; IORegB = 0x0400; ; IORegC = VarA; ; if( IORegC = 0x2000 ) ; IORegC = 0x0000; IORegA .set 0x0300 IORegB .set 0x0301 IORegC .set 0x0302 MOV @AL,#0 UOUT *(IORegA),@AL MOV @AL,#0x0400 UOUT *(IORegB),@AL OUT *(IORegC),@VarA IN @AL,*(IORegC) CMP @AL,#0x2000 SB $10,NEQ MOV @AL,#0 UOUT *(IORegC),@AL $10:
; ; ; ; ; ; ; ; ; ; ; ; ;
Define IORegA address Define IORegB address Define IORegC address AL = 0 IOspace[IORegA] = AL AL = 0x0400 IOspace[IORegB] = AL IOspace[IORegC] = VarA AL = IOspace[IORegC] Set flags on (AL 0x2000) Branch if not equal AL = 0 IOspace[IORegC] = AL
6-367
XB *AL
XB *AL SYNTAX OPTIONS XB *AL Operands

*AL
C2 xLP Source-Compatible Indirect Branch OPCODE

0101 0110 0001 0100
OBJMODE RPT 1
CYC 7
Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Unconditional indirect branch by loading the low 16 bits of PC with the contents of register AL and forcing the upper 6 bits of the PC to 0x3F:
PC = 0x3F:AL; Note: This branch instruction can only branch to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF).
Description
None
; Branch to subroutines in SwitchTable selected by Switch value. ; This example only works for code located in upper 64K of ; program space: SwitchTable: ; Switch address table: .word Switch0 ; Switch0 address .word Switch1 ; Switch1 address . . MOVL XAR2,#SwitchTable ; XAR2 = pointer to SwitchTable MOVZ AR0,@Switch ; AR0 = Switch index MOV AL,*+XAR2[AR0] ; AL = SwitchTable[Switch] XB *AL ; Indirect branch using AL SwitchReturn: . Switch0: . . XB Switch1: . . XB ; Subroutine 0:
Example
SwitchReturn,UNC
; Return: branch ; Subroutine 1:
SwitchReturn,UNC
; Return: branch
6-368
XB pma,*,ARPn
XB pma,*,ARPn SYNTAX OPTIONS XB pma,*,ARPn Operands

pma
C2xLP Source-Compatible Branch with ARP Modification OPCODE

OBJMODE RPT 1
CYC 4
16-bit immediate program -memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) 3-bit auxiliary register pointer (ARP0 to ARP7) Unconditional branch with ARP modification by loading the low 16 bits of PC with the 16-bit immediate value pma and forcing the upper 6 bits of the PC to 0x3F. Also, change the auxiliary register pointer as specified by the ARPn operand:
PC = 0x3F:pma; ARP = n; Note: This branch instruction can only branch to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF).
ARPn
Description
None
; Branch to SubA and set ARP. Load ACC with pointer pointed to ; by ARP and return to. This example only works for code ; located in upper 64K of program space: XB SubA,*,ARP1 ; Branch to SubA with ARP pointing ; to XAR1 SubReturn: . SubA: MOVL XB ; ; ; ; Subroutine A: Load ACC with contents pointed to by XAR(ARP) Return unconditionally
Example
ACC,* SubReturn,UNC
6-369
XB pma,COND
XB pma,COND SYNTAX OPTIONS XB pma,COND Operands

pma COND
C2 xLP Source-Compatible Branch OPCODE

OBJMODE RPT 1
CYC 7/4
16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Conditional codes:
Description
Conditional branch. If the specified condition is true, then branch by loading the low 16 bits of PC with the 16-bit immediate value pma and forcing the upper 6 bits of the PC to 0x3F.; otherwise continue execution without branching:
If (COND = true) PC(15:0) = pma; If (COND = false) PC(15:0) = PC(15:0) + 2; PC(21:16) = 0x3F; Note: If (COND = true) then the instruction takes 7 cycles. If (COND = false) then the instruction takes 4 cycles.
6-370
XB pma,COND
Example
; Branch to subroutines in SwitchTable selected by Switch value. ; This example only works for code located in upper 64K of ; program space: SwitchTable: ; Switch address table: .word Switch0 ; Switch0 address .word Switch1 ; Switch1 address . . MOVL XAR2,#SwitchTable MOVZ AR0,@Switch MOV AL,*+XAR2[AR0] XB *AL SwitchReturn: . Switch0: . . XB turn,UNC Switch1: . . XB turn,UNC ; XAR2 = pointer to SwitchTable ; AR0 = Switch index ; AL = SwitchTable[Switch] ; Indirect branch using AL
; Subroutine 0:
SwitchRe-
; Return: branch
; Subroutine 1:
SwitchRe-
; Return: branch
6-371
XBANZ pma,*ind{,ARPn}
XBANZ pma,*ind{,ARPn} SYNTAX OPTIONS XBANZ pma,* XBANZ pma,*++ XBANZ pma,* XBANZ pma,*0++ XBANZ pma,*0 XBANZ pma,*,ARPn XBANZ pma,*++,ARPn XBANZ pma,*,ARPn XBANZ pma,*0++,ARPn XBANZ pma,*0,ARPn Operands
pma ARPn
C2 x LP Source-Compatible Branch If ARn Is Not Zero OPCODE

0101 0110 0000 1100 CCCC CCCC CCCC CCCC 0101 0110 0000 1010 CCCC CCCC CCCC CCCC 0101 0110 0000 1011 CCCC CCCC CCCC CCCC 0101 0110 0000 1110 CCCC CCCC CCCC CCCC 0101 0110 0000 1111 CCCC CCCC CCCC CCCC 0011 1110 0011 0nnn CCCC CCCC CCCC CCCC 0011 1110 0011 1nnn CCCC CCCC CCCC CCCC 0011 1110 0100 0nnn CCCC CCCC CCCC CCCC 0011 1110 0100 1nnn CCCC CCCC CCCC CCCC 0011 1110 0101 0nnn CCCC CCCC CCCC CCCC
OBJMODE RPT 1 1 1 1 1 1 1 1 1 1
CYC 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2
16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) 3-bit auxiliary register pointer (ARP0 to ARP7) If the lower 16 bits of the auxiliary register pointed to by the current auxiliary register pointer (ARP) is not equal to 0, then a branch is taken by loading the lower 16 bits of the PC with the 16-bit immediate pma value and forcing the upper 6 bits of the PC to 0x3F. Then, the current auxiliary register, pointed to by the ARP, is modified as specified by the indirect mode. Then,, if indicated, the ARP pointer value is changed to point a new auxiliary register:
if( AR[ARP] != 0 ) PC = 0x3F:pma if(*++ indirect mode) XAR[ARP] if(* indirect mode) XAR[ARP] if(*0++ indirect mode) XAR[ARP] if(*0 indirect mode) XAR[ARP] if(ARPn specified) ARPn = n;
Description
= = = =
XAR[ARP] XAR[ARP] XAR[ARP] XAR[ARP]
+ +
1; 1; AR0; AR0;
Note: This instruction can only transfer program control to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). The cycle times for this operation are: If branch is taken, then the instruction takes 4 cycles If branch is not taken, then the instruction takes 2 cycles
6-372
XBANZ pma,*ind{,ARPn}
None
; ; ; ; ; ; ; Copy the contents of Array1 int32 Array1[N]; int32 Array2[N]; for(i=0; i < N; i++) Array2[i] = Array1[i]; This example only works for program space: MOVL XAR2,#Array1 ; MOVL XAR3,#Array2 ; MOV @AR0,#(N1) ; NOP *,ARP2 ; SETC AMODE ; Loop: MOVL ACC,*++,ARP3 ; MOVL *++,ACC,ARP0 ; BANZ Loop,*,ARP2 ; ; to Array2:
Example
code located in upper 64K of XAR2 = pointer to Array1 XAR3 = pointer to Array2 Repeat loop N times Point to XAR2 Full C2XLP address mode compatible ACC = Array1[i], point to XAR3 Array2[i] = ACC, point to XAR0 Loop if AR[ARP] != 0, AR[ARP], point to XAR2
6-373
XCALL *AL
XCALL *AL SYNTAX OPTIONS XCALL *AL Operands Description

*AL
C2 x LP Source-Compatible Function Call OPCODE

0101 0110 0011 0100
OBJMODE RPT 1
CYC 7
Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Indirect call with destination address in AL. The lower 16 bits of the current PC address are saved onto the software stack. Then, the low 16 bits of PC is loaded with the contents of register AL and the upper 6 bits of the PC are loaded with 0x3F:
temp(21:0) = PC + 1; [SP] = temp(15:0); SP = SP + 1; C = 0x3F:AL; Note: This instruction can only transfer program control to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). To return from a call made by XCALL, the XRETC instruction must be used.
None This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
; Call function in FuncTable selected by FuncIndex value. ; This example only works for code located in upper 64K of ; program space: FuncTable: ; Function address table: .word FuncA ; FuncA address .word FuncB ; FuncB address . . MOVL XAR2,#FuncTable ; XAR2 = pointer to FuncTable MOVZ AR0,@FuncIndex ; AR0 = FuncTable index MOV AL,*+XAR2[AR0] ; AL = Table[FuncIndex] XCALL *AL ; Indirect call using AL . . FuncA: ; Function A: . . XRETC UNC ; Return unconditionally FuncB: . . XRETC ; Function B:
UNC
; Return unconditionally
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XCALL pma,*,ARPn
XCALL pma,*,ARPn SYNTAX OPTIONS XCALL pma,*,ARPn Operands

pma
C2 x LP Source-Compatible Function Call OPCODE

OBJMODE RPT 1
CYC 4
16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) 3-bit auxiliary register pointer (ARP0 to ARP7) Unconditional call with ARP modification. The lower 16 bits of the return address are pushed onto the software stack. Then, the lower 16 bits of the PC are loaded with the 16-bit immediate pma value and the upper 6 bits of the PC are forced to 0x3F. Then, the 3-bit ARP pointer will be set to the ARPn field value:
temp(21:0) = PC + 1; [SP] = temp(15:0); SP = SP + 1; PC = 0x3F:pma; ARP = n; Note: This instruction can only transfer program control to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). To return from a call made by XCALL, the XRETC instruction must be used.
ARPn
Description
None
; Call FuncA and set ARP. Load ACC with pointer pointed to by ARP. ; This example only works for code located in upper 64K of program ; space: XCALL FuncA,*,ARP1 ; Call FuncA with ARP pointing to XAR1 . FuncA: MOVL XRETC ; Function A: ; Load ACC with contents pointed to ; by XAR(ARP) ; Return unconditionally
Example
ACC,* UNC
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XCALL pma,COND
XCALL pma,COND SYNTAX OPTIONS XCALL pma,COND Operands

pma COND
C2xLP Source-Compatible Function Call OPCODE

OBJMODE RPT 1
CYC 7/4
16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Conditional codes:
Description
Conditional call. If the specified condition is true, then the low 16 bits of the return address is pushed onto the software stack and the low 16 bits of the PC are loaded with the 16-bit immediate pma value and the upper 6 bits of the PC are forced to 0x3F; otherwise continue execution with instruction following the XCALL operation:
if(COND = true) { temp(21:0) = PC + 2; [SP] = temp(15:0); SP = SP + 1; PC = 0x3F:pma; } else PC = PC + 2; Note: This instruction can only transfer program control to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). To return from a call made by XCALL, the XRETC instruction must be used. The cycle times for this operation are: If (COND = true) then the instruction takes 7 cycles. If (COND = false) then the instruction takes 4 cycles.
6-376
XCALL pma,COND
; Call FuncA if VarA does not equal zero. This example only ; works for code located in upper 64K of program space: MOV AL,@VarA ; Load AL with VarA XCALL FuncA,NEQ ; Call FuncA if not equal to zero . . FuncA: . . XRETC ; Function A:
Example
UNC
; Return unconditionally
6-377
XMAC P,loc16,*(pma)
XMAC P,loc16,*(pma) SYNTAX OPTIONS XMAC P,loc16,*(pma) Operands

P loc16 *(pma)
C2xLP Source-compatible Multiply and Accumulate OPCODE

OBJMODE RPT 1 Y
CYC N+2
Product register Addressing mode (see Chapter 5) Immediate program memory address, access high 64K range of program space only (0x3F0000 to 0x3FFFFF) Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. Next, load the T register with the content of the location pointed to by the loc16 addressing mode. Last, multiply the signed 16-bit content of the T register by the signed 16-bit content of the addressed program memory location and store the 32-bit result in the P register:
ACC = ACC + P << PM; T = [loc16]; P = signed T * signed Prog[0x3F:pma];
Description
The C28x forces the upper 6 bits of the program memory address, specified by the *(pma) addressing mode, to 0x3F when using this form of the MAC instruction. This limits the program memory address to the high 64K of program address space (0x3F0000 to 0x3FFFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *(pma) addressing mode can be used to access data space variables that fall within its address range. Flags and Modes
Z N C V OVC
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected. If overflow mode is disabled; and if the operation generates a positive overflow, then the counter is incremented. If overflow mode is disabled; and if the operation generates a negative overflow, then the counter is decremented. If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed.
OVM
6-378
XMAC P,loc16,*(pma)
PM
The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. When repeated, the program-memory address is incremented by 1 during each repetition.
Repeat
Example
; ; ; ; ; ;
Calculate sum of product using 16-bit multiply: int16 X[N] ; Data information int16 C[N] ; Coefficient information, located in high 64K sum = 0; for(i=0; i < N; i++) sum = sum + (X[i] * C[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #N1 ; Repeat next instruction N times ||XMAC P,*XAR2++,*(C) ; ACC = ACC + P >> 5, ; P = *XAR2++ * *C++ ADDL ACC,P << PM ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-379
XMACD P,loc16,*(pma)
C2xLP Source-Compatible Multiply and Accumulate With Data Move OPCODE

SYNTAX OPTIONS XMACD P,loc16,*(pma)
OBJMODE RPT 1 Y
CYC N+2
Operands
P loc16

Note: For this operation, register-addressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T. An illegal instruction trap will be generated.
*(pma)
Immediate program memory address, access high 64K range of program space only (0x3F0000 to 0x3FFFFF) The XMACD instruction functions in the same manner as the XMAC, with the addition of a data move. Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register. Next, load the T register with the content of the location pointed to by the loc16 addressing mode. Then, multiply the signed 16-bit content of the T register by the signed 16-bit content of the addressed program memory location and store the 32-bit result in the P register. Last, store the content in the T register onto the next highest memory address pointed to by loc16 addressing mode:
ACC = ACC + P << PM; T = [loc16]; P = signed T * signed Prog[0x3F:pma]; [loc16 + 1] = T;
Description
The C28x forces the upper 6 bits of the program memory address, specified by the *(pma) addressing mode, to 0x3F when using this form of the MAC instruction. This limits the program memory address to the high 64K of program address space (0x3F0000 to 0x3FFFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), therefore, the (pma) addressing mode can be used to access data-space variables that fall within its address range. Flags and Modes
Z
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set; otherwise C is cleared. If an overflow occurs, V is set; otherwise V is not affected.
N C V
6-380
OVC
If overflow mode is disabled and if the operation generates a positive overflow, the counter is incremented. If overflow mode is disabled and if the operation generates a negative overflow, the counter is decremented. If overflow mode bit is set, the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. The state of the Z, N, C and OVC flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. When repeated, the program-memory address is incremented by 1 during each repetition.
OVM
PM
Repeat
Example
; ; ; ; ; ; ; ; ; ;
Calculate FIR filter using 16-bit multiply: int16 X[N] ; Data information int16 C[N] ; Coefficient information, located in high 64K sum = X[N1] * C[0]; for(i=1; i < N; i++) { sum = sum + (X[N1i] * C[i]) >> 5; X[Ni] = X[N1i]; } X[1] = X[0]; MOVL XAR2,#X+N ; XAR2 = point to end of X array SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC XMAC P,*XAR2,*(C) ; ACC = 0, P = X[N1] * C[0] RPT #N2 ; Repeat next instruction N1 times ||XMACD P,*XAR2,*(C+1) ; ACC = ACC + P >> 5, ; P = X[N1i] * C[i], ; i++ MOV *+XAR2[2],T ; X[1] = X[0] ADDL ACC,P << PM ; Perform final accumulate MOVL @sum,ACC ; Store final result into sum
6-381
XOR ACC,loc16
XOR ACC,loc16 SYNTAX OPTIONS XOR ACC,loc16 Operands

ACC loc16
Bitwise Exclusive OR OPCODE

1011 0111 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+1
Accumulator register Addressing mode (see Chapter 5) Perform a bitwise XOR operation on the ACC register with the zero-extended content of the location pointed to by the loc16 address mode. The result is stored in the ACC register:
ACC = ACC XOR 0:[loc16];
Description
Flags and Modes
The load to ACC is tested for a negative condition. If bit 31 of ACC is 1, then the negative flag bit is set; otherwise it is cleared. The load to ACC is tested for a zero condition. The zero flag bit is set if the operation generates ACC = 0; otherwise it is cleared This operation is repeatable. If the operation follows a RPT instruction, then the XOR instruction will be executed N+1 times. The state of the Z and N flags will reflect the final result.
Repeat
Example
; Calculate the 32-bit value: VarA = VarA XOR 0:VarB MOVL ACC,@VarA ; Load ACC with contents of VarA XOR ACC,@VarB ; XOR ACC with contents of 0:VarB MOVL @VarA,ACC ; Store result in VarA
6-382
XOR ACC,#16bit << #0..16
XOR ACC,#16bit << #0..16 SYNTAX OPTIONS XOR ACC,#16bit << #0..15 XOR ACC,#16bit << #16 Operands
ACC #16bit #0..16

OBJMODE RPT 1 1
CYC 1 1
Accumulator register 16-bit immediate constant value Shift value (default is << #0 if no value specified) Perform a bitwise XOR operation on the ACC register with the given 16-bit unsigned constant value left shifted as specified. The value is zero extended and lower order bits are zero filled before the XOR operation. The result is stored in the ACC register:
ACC = ACC XOR (0:16bit << shift value);
Description
Flags and Modes
Repeat
Example
; Calculate the 32-bit value: MOVL ACC,@VarA ; XOR ACC,#0x8000 << 12 ; MOVL @VarA,ACC ;
VarA = VarA XOR 0x08000000 Load ACC with contents of VarA XOR ACC with 0x08000000 Store result in VarA
6-383
XOR AX,loc16
XOR AX,loc16 SYNTAX OPTIONS XOR AX, loc16 Operands

AX loc16

0111 000A LLLL LLLL
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register Addressing mode (see Chapter 5) Perform a bitwise exclusive OR operation on the specified AX register (AH or AL) and the contents of the location pointed to by the loc16 addressing mode. The result is stored in the specified AX register:
AX = AX XOR [loc16];
Description
Flags and Modes
Repeat
Example
; XOR the contents of VarA and VarB and store in VarC: MOV AL,@VarA ; Load AL with contents of VarA XOR AL,@VarB ; XOR AL with contents of VarB MOV @VarC,AL ; Store result in VarC
6-384
XOR loc16, AX
XOR loc16, AX SYNTAX OPTIONS XOR loc16, AX Operands

loc16 AX

1111 001A LLLL LLLL
OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Perform a bitwise exclusive OR operation on the 16-bit contents of location pointed to by the loc16 addressing mode and the specified AX register (AH or AL). The result is stored in the location pointed to by loc16:
[loc16] = [loc16] XOR AX;
Description

N
The load to [loc16] is tested for a negative condition. If bit 15 of [loc16] is 1, then the negative flag bit is set; otherwise it is cleared. The load to [loc16] is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; XOR the contents of VarA with VarB and store in VarB: MOV AL,@VarA ; Load AL with contents of VarA XOR @VarB,AL ; VarB = VarB XOR AL
6-385
XOR loc16,#16bit
XOR loc16,#16bit SYNTAX OPTIONS XOR loc16,#16bit Operands

loc16 #16bit

OBJMODE RPT X
CYC 1
Addressing mode (see Chapter 5) 16-bit immediate constant value Perform a bitwise XOR operation on the content of the location pointed to by the loc16 addressing mode and the 16-bit immediate constant value. The result is stored in the location pointed to by loc16:
[loc16] = [loc16] XOR 16bit;
Description
Smart Encoding: If loc16 = AH or AL and #16bit is an 8-bit number, then the assembler will encode this instruction as XORB AX,#8bt. To override this encoding, use the XORW AX,#16bit instruction alias. Flags and Modes
N
Repeat
Example
; Toggle Bits 2 and 14 of VarA: ; VarA = VarA XOR #(1 << 2 | 1 << 14) XOR @VarA,#(1 << 2 | 1 << 14) ; Toggle bits 2 and 11 of VarA
6-386
XORB AX, #8bit
XORB AX, #8bit SYNTAX OPTIONS XORB AX, #8bit Operands

AX #8bit
Bitwise Exclusive OR 8-bit Value OPCODE

1111 000A CCCC CCCC
OBJMODE RPT X
CYC 1
Accumulator high (AH) or accumulator low (AL) register 8-bit immediate constant value Perform a bitwise exclusive OR operation on the specified AX register and the 8-bit unsigned immediate constant zero extended. The result is stored in the AX register:
AX = AX XOR 0x00:8bit;
Description
Flags and Modes
The load to AX is tested for a negative condition. If bit 15 of AX is 1, then the negative flag bit is set; otherwise it is cleared. The load to AX is tested for a zero condition. The zero flag bit is set if the operation generates [loc16] = 0, otherwise it is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; Toggle bit 7 of VarA and store result in MOV AL,@VarA ; Load AL with XORB AL,#0x80 ; XOR contents MOV @VarB,AL ; Store result
VarB: contents of VarA of AL with 0x0080 in VarB
6-387
XPREAD loc16, *(pma)
XPREAD loc16, *(pma) SYNTAX OPTIONS XPREAD loc16,*(pma)
C2xLP Source-Compatible Program Read OPCODE

1010 1100 MMMM MMMM LLLL LLLL LLLL LLLL
OBJMODE RPT 1 Y
CYC N+2
Operands
loc16 *(pma)
Addressing mode (see Chapter 5) Immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Load the 16-bit data-memory location pointed to by the loc16 addressing mode with the 16-bit content of the program-memory location pointed to by *(pma) addressing mode:
[loc16] = Prog[0x3F:pma];
Description
The C28x forces the upper 6 bits of the program memory address, specified by the *(pma) addressing mode, to 0x3F when using this form of the XPREAD instruction. This limits the program memory address to the high 64K of program address space (0x3F0000 to 0x3FFFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *(pma) addressing mode can be used to access data space variables that fall within its address range. Flags and Modes
N
If (loc16 = @AX) and bit 15 of AX is 1, then N is set; otherwise N is cleared. If (loc16 = @AX) and the value of AX is zero, then Z is set; otherwise Z is cleared. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *(pma) program-memory address is copied to an internal shadow register and the address is post-incremented by 1 during each repetition.
Repeat
Example
; ; ; ; ;
Copy the contents of Array1 to Array2: int16 Array1[N]; // Located in high 64K of program space int16 Array2[N]; // Located in data space for(i=0; i < N; i++) Array2[i] = Array1[i]; MOVL XAR2,#Array2 ; XAR2 = pointer to Array2 RPT #(N1) ; Repeat next instruction N times ||XPREAD *XAR2++,*(Array1) ; Array2[i] = Array1[i], ; i++
6-388
XPREAD loc16, *AL
XPREAD loc16, *AL SYNTAX OPTIONS XPREAD loc16,*AL Operands

loc16 *AL
C2xLP Source-Compatible Program Read OPCODE

0101 0110 0011 1100 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+4
Addressing mode (see Chapter 5) Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF)
Description
Load the 16-bit data-memory location pointed to by the loc16 addressing mode with the 16-bit content of the program-memory location pointed to by *AL addressing mode:
[loc16] = Prog[0x3F:AL];
The C28x forces the upper 6 bits of the program memory address, specified by the *AL addressing mode, to 0x3F when using this form of the XPREAD instruction. This limits the program memory address to the high 64K of program address space (0x3F0000 to 0x3FFFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *AL addressing mode can be used to access data space variables that fall within its address range. Flags and Modes
N
If (loc16 = @AX) and bit 15 of AX is 1, then N is set; otherwise N is cleared. If (loc16 = @AX) and the value of AX is zero, then Z is set; otherwise Z is cleared. This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *AL program-memory address is copied to an internal shadow register and the address is post-incremented by 1 during each repetition.
Repeat
Example
; ; ; ; ;
Copy the contents of Array1 to Array2: int16 Array1[N]; // Located in high 64K of program space int16 Array2[N]; // Located in data space for(i=0; i < N; i++) Array2[i] = Array1[i]; MOV @AL,#Array1 ; AL = pointer to Array1 MOVL XAR2,#Array2 ; XAR2 = pointer to Array2 RPT #(N1) ; Repeat next instruction N times ||XPREAD *XAR2++,*AL ; Array2[i] = Array1[i], ; i++
6-389
XPWRITE *A,loc16
XPWRITE *A,loc16 SYNTAX OPTIONS XPWRITE *AL,loc16 Operands

*AL
C2xLP Source-Compatible Program Write OPCODE

0101 0110 0011 1101 0000 0000 LLLL LLLL
OBJMODE RPT 1 Y
CYC N+4
Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Addressing mode (see Chapter 5) Load the 16-bit program-memory location pointed to by *AL addressing mode with the 16-bit content of the location pointed to by the loc16 addressing mode:
Prog[0x3F:AL] = [loc16];
loc16
Description
The C28x forces the upper 6 bits of the program memory address, specified by the *AL addressing mode, to 0x3F when using this form of the XPWRITE instruction. This limits the program memory address to the high 64K of program address space (0x3F0000 to 0x3FFFFF). On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the *AL addressing mode can be used to access data space variables that fall within its address range. Flags and Modes Repeat None
This instruction is repeatable. If the operation follows a RPT instruction, then it will be executed N+1 times. When repeated, the *AL program-memory address is copied to an internal shadow register and the address is post-incremented by 1 during each repetition.
; ; ; ; ; Copy the contents of Array1 to Array2: int16 Array1[N]; // Located in data space int16 Array2[N]; // Located in high 64K of program space for(i=0; i < N; i++) Array2[i] = Array1[i]; MOVL XAR2,#Array1 ; XAR2 = pointer to Array1 MOV @AL,#Array2 ; AL = pointer to Array2 RPT #(N1) ; Repeat next instruction N times ||XPWRITE *AL,*XAR2++ ; Array2[i] = Array1[i], ; i++
Example
6-390
XRET
XRET SYNTAX OPTIONS XRET

Note: XRET is an alias for RETC unconditional.
C2xLP Source-Compatible Return OPCODE

0101 0110 1111 1111
OBJMODE RPT 1
CYC 7
None Return conditionally. If the specified condition is true, a 16-bit value is popped from the stack and stored into the low 16 bits of the PC while the upper 6 bits of the PC are forced to 0x3F; Otherwise, execution continues with the instruction following the XRETC operation:
if(COND = true) SP = SP 1; PC = 0x3F:[SP]; Note: This instruction can transfer program control only to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). To return from a call made by XCALL, the XRET instruction must be used.
; Return from FuncA if VarA does not equal zero, else set VarB ; to zero and return. This example only works for code located ; in upper 64K of program space: XCALL FuncA ; Call FuncA . FuncA: . . . . MOV AL,@VarA XRET NEQ MOV @VarA,#0 XRETC UNC ; Function A:
Example
; ; ; ;
Load AL with contents of VarA Return if VarA does not equal 0 Store 0 into VarB Return unconditionally
6-391
XRETC COND
XRETC COND SYNTAX OPTIONS XRETC COND Operands

COND
C2xLP Source-Compatible Conditional Return OPCODE

0101 0110 1111 COND
OBJMODE RPT 1
CYC 4/7
Conditional codes:
Description
Return conditionally. If the specified condition is true, a 16-bit value is popped from the stack and stored into the low 16 bits of the PC while the upper 6 bits of the PC are forced to 0x3F; Otherwise, execution continues with the instruction following the XRETC operation:
if(COND { SP = PC = } else PC = = true) SP 1; 0x3F:[SP];
PC + 1;
Note: This instruction can only transfer program control to a location located in the upper 64K range of program space (0x3F0000 to 0x3FFFFF). To return from a call made by XCALL, the XRETC instruction must be used. The cycle times for this operation are: If (COND = true) then the instruction takes 7 cycles. If (COND = false) then the instruction takes 4 cycles.
Flags and Modes
6-392
XRETC COND
Repeat
; Return from FuncA if VarA does not equal zero, else set VarB ; to zero and return. This example only works for code located ; in upper 64K of program space: XCALL FuncA ; Call FuncA . FuncA: . . . . MOV XRETC MOV XRETC ; Function A:
Example
AL,@VarA NEQ @VarA,#0 UNC
; ; ; ;
Load AL with contents of VarA Return if VarA does not equal 0 Store 0 into VarB Return unconditionally
6-393
ZALR ACC,loc16
ZALR ACC,loc16 SYNTAX OPTIONS ZALR ACC,loc16 Operands

ACC loc16
Zero AL and Load AH With Rounding OPCODE

0101 0110 0001 0011 0000 0000 LLLL LLLL
OBJMODE RPT 1
CYC 1
Accumulator register Addressing mode (see Chapter 5) Load low accumulator (AL) with the value 0x8000 and load high accumulator (AH) with the 16-bit contents pointed to by the loc16 addressing mode.
AH = [loc16]; AL = 0x8000;
Description
Flags and Modes
Repeat
Example
; Calculate: Y = round(M*X << 1 + B << 16) ; Y, M, X, B are all Q15 numbers SPM +1 ; Set product shift mode to << 1 MOV T,@M ; T = M (Q15) MPY P,T,@X ; P = M * X (Q30) ZALR ACC,@B ; ACC = B << 16 + 0x8000 (Q31) ADDL ACC,P << PM ; Add P to ACC with shift (Q31) MOV @Y,AH ; Store AH into Y (Q15)
6-394
ZAP OVC
ZAP OVC SYNTAX OPTIONS ZAP OVC Operands Description Flags and Modes Repeat
OVC OVC
Clear Overflow Counter OPCODE

0101 0110 0101 1100
OBJMODE RPT 1
CYC 1
overflow counter bits in Status Register 0 (ST0) Clear the overflow counter (OVC) bits in Status Register 0 (ST0). The 6-bit overflow counter bits (OVC) are cleared.
; Calculate: VarD = sat(VarA + VarB + VarC) ZAP OVC ; Zero overflow counter MOVL ACC,@VarA ; ACC = VarA ADDL ACC,@VarB ; ACC = ACC + VarB ADDL ACC,@VarC ; ACC = ACC + VarC SAT ACC ; Saturate if OVC != 0 MOVL @VarD,ACC ; Store saturated result into VarD
Example
6-395
ZAPA
ZAPA SYNTAX OPTIONS ZAPA Operands Description None OPCODE
Zero Accumulator and P Register OBJMODE RPT 1 CYC 1
0101 0110 0011 0011
Zero the ACC and P registers as well as the overflow counter (OVC):
ACC = 0; P = 0; OVC = 0;
Flags and Modes
The N bit is set. The Z bit is cleared. This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once.
Repeat
Example
; ; ; ; ; ; ;
Calculate sum of product using 32-bit multiply and retain high result: int32 X[N]; // Data information int32 C[N]; // Coefficient information (located in low 4M) int32 sum = 0; for(i=0; i < N; i++) sum = sum + ((X[i] * C[i]) >> 32) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X MOVL XAR7,#C ; XAR7 = pointer to C SPM 5 ; Set product shift to >> 5 ZAPA ; Zero ACC, P, OVC RPT #(N1) ; Repeat next instruction N times ||QMACL P,*XAR2++,*XAR7++ ; ACC = ACC + P >> 5, ; P = (X[i] * C[i]) >> 32 ADDL MOVL ACC,P << PM @sum,ACC ; i++ ; Perform final accumulate ; Store final result into sum
6-396
Chapter 7
Emulation Features
The CPU in the C28x contains hardware extensions for advanced emulation features that can assist you in the development of your application system (software and hardware). This chapter describes the emulation features that are available on all C28x devices using only the JTAG port (with TI extensions). For more information about instructions shown in examples in this chapter, see Chapter 6, Assembly Language Instructions.
Topic
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9
Page
Overview of Emulation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Debug Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Execution Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Aborting Interrupts With the ABORTI Instruction . . . . . . . . . . . . . . . . 7-15 DT-DMA Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Analysis Breakpoints, Watchpoints, and Counter(s) . . . . . . . . . . . . . 7-19 Data Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 Sharing Analysis Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
7.10 Diagnostics and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Emulation Features
7-1
Overview of Emulation Features
7.1 Overview of Emulation Features

The CPUs hardware extensions for advanced emulation features provide simple, inexpensive, and speed-independent access to the CPU for sophisticated debugging and economical system development, without requiring the costly cabling and access to processor pins required by traditional emulator systems. It provides this access without intruding on system resources. The on-chip development interface provides:
- Minimally intrusive access to internal and external memory - Minimally intrusive access to CPU and peripheral registers - Control of the execution of background code while continuing to service
time-critical interrupts
J J J J J
Break on a software breakpoint instruction (instruction replacement) Break on a specified program or data access without requiring instruction replacement (accomplished using bus comparators) Break on external attention request from debug host or additional hardware Break after the execution of a single instruction (single-stepping) Control over the execution of code from device power up
- Nonintrusive determination of device status J J J J
Detection of a system reset, emulation/test-logic reset, or powerdown occurrence Detection of the absence of a system clock or memory-ready signal Determination of whether global interrupts are enabled Determination of why debug accesses might be blocked
- Rapid transfer of memory contents between the device and a host (data
logging)
- A cycle counter for performance benchmarking. With a 100-MHz cycle
clock, the counter can benchmark actions up to 3 hours in duration.
7-2
Debug Interface
7.2 Debug Interface

The target-level TI debug interface uses the five standard IEEE 1149.1 (JTAG) signals (TRST, TCK, TMS, TDI, and TDO) and the two TI extensions (EMU0 and EMU1). Figure 71 shows the 14-pin JTAG header that is used to interface the target to a scan controller, and Table 71 (page 7-4) defines the pins. As shown in the figure, the header requires more than the five JTAG signals and the TI extensions. It also requires a test clock return signal (TCK_RET), the target supply (VCC ) and ground (GND). TCK_RET is a test clock out of the scan controller and into the target system. The target system uses TCK_RET if it does not supply its own test clock (in which case TCK would simply not be used). In many target systems, TCK_RET is simply connected to TCK and used as the test clock.
Figure 71. JTAG Header to Interface a Target to the Scan Controller

TMS TDI PD (VCC) TDO TCK_RET TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TRST GND No pin (key) GND GND GND EMU1 Header dimensions: Pin-to-pin spacing: 0.100 in. (X,Y) Pin width: 0.025-in. square post Pin length: 0.235-in. nominal
Emulation Features
7-3
Debug Interface
Table 71. 14-Pin Header Signal Descriptions

Signal EMU0 EMU1 GND PD (VCC) Description Emulation pin 0 Emulation pin 1 Ground Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VCC in the target system. Test clock. TCK is a clock source from the emulation cable pod. This signal can be used to drive the system test clock. Test clock return. Test clock input to the emulator. Can be a buffered or unbuffered version of TCK. Test data input Test data output Test mode select Test reset I O Emulator State I I Target State I/O I/O
TCK
TCK_RET
TDI TDO TMS TRST

O I O O
I O I I
I = input; O = output Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on electrical current considerations.)
The state of the TRST, EMU0, and EMU1 signals at device power up determine the operating mode of the device. The operating mode takes effect as soon as the device has sufficient power to operate. Should the TRST signal rise, the EMU0 and EMU1 signals are sampled on its rising edge and the\at operating mode is latched. Some of these modes are reserved for test purposes, but those that can be of use in a target system are detailed in Table 72. A target system is not required to support any mode other than normal mode.
7-4
Debug Interface
Table 72. Selecting Device Operating Modes By Using TRST, EMU0, and EMU1
TRST Low EMU1 Low EMU0 Low Device Operating Mode JTAG Cable Active?
Slave mode. Disables the CPU and No memory portions of the C28x. Another processor treats the C28x as a peripheral. Reserved for testing No
Low Low
Low High
High Low
Wait-in-reset mode. Prolongs the Yes devices reset until released by external means. This allows a C28x to power up in reset, provided external hardware holds EMU0 low only while power-up reset is active. Normal mode with emulation dis- No abled. This is the setting that should be used on target systems when a scan controller (such as the XDS510) is not attached. TRST will be pulled down and EMU1 and EMU0 pulled up within the C28x; this is the default mode. Normal mode with emulation en- Yes abled. This is the setting to use on target systems when a scan controller is attached (the scan controller will control TRST). TRST should not be high during device power-up.
Low
High
High
High
Low or High
Low or High
Emulation Features
7-5
Debug Terminology
7.3 Debug Terminology

The following definitions will help you to understand the information in the rest of this chapter:
- Background code. The body of code that can be halted during debug-
ging because it is not time-critical.

- Foreground code. The code of time-critical interrupt service routines,
which are executed even when background code is halted.

- Debug-halt state. The state in which the device does not execute back-
ground code.
- Time-critical interrupt. An interrupt that must be serviced even when
background code is halted. For example, a time-critical interrupt might service a motor controller or a high-speed timer.
- Debug event. An action, such as the decoding of a software breakpoint
instruction, the occurrence of an analysis breakpoint/watchpoint, or a request from a host processor that can result in special debug behavior, such as halting the device or pulsing one of the signals EMU0 or EMU1.
- Break event. A debug event that causes the device to enter the debug-
halt state.
7-6
Execution Control Modes
7.4 Execution Control Modes

The C28x supports two debug execution control modes:
- Stop mode - Real-time mode
Stop mode provides complete control of program execution, allowing for the disabling of all interrupts. Real-time mode allows time-critical interrupt service routines to be performed while execution of other code is halted. Both execution modes can suspend program execution at break events, such as occurrences of software breakpoint instructions or specified program-space or data-space accesses.
7.4.1
Stop Mode
Stop mode causes break events, such as software breakpoints and analysis watchpoints, to suspend program execution at the next interrupt boundary (which is usually identical to the next instruction boundary). When execution is suspended, all interrupts (including NMI and RS) are ignored until the CPU receives a directive to run code again. In stop mode, the CPU can operate in the following execution states:
- Debug-halt state. This state is entered through a break event, such as
the decoding of a software breakpoint instruction or the occurrence of an analysis breakpoint/watchpoint. This state can also be entered by a request from the host processor. In the stop mode debug-halt state, the CPU is halted. You can place the device into one of the other two states by giving the appropriate command to the debugger. The CPU cannot service any interrupts, including NMI and RS (reset). When multiple instances of the same interrupt occurs without the first instance being serviced, the later instances are lost.
- Single-instruction state. This state is entered when you tell the debug-
ger to execute a single instruction by using a RUN 1 command or a STEP 1 command. The CPU executes the single instruction pointed to by the PC and then returns to the debug-halt state (it executes from one interrupt boundary to the next). The CPU is only in the single-instruction state until that single instruction is done. If an interrupt occurs in this state, the command used to enter this state determines whether that interrupt can be serviced. If a RUN 1 command was used, the CPU can service the interrupt. If a STEP 1 command was used, the CPU cannot, even if the interrupt is NMI or RS.
- Run state. This state is entered when you use a run command from the
debugger interface. The CPU executes instructions until a debugger command or a debug event returns the CPU to the debug-halt state.
Emulation Features 7-7
The CPU can service all interrupts in this state. When an interrupt occurs simultaneously with a debug event, the debug event has priority; however, if interrupt processing began before the debug event occurred, the debug event cannot be processed until the interrupt service routine begins. Figure 72 illustrates the relationship among the three states. Notice that the C28x cannot pass directly between the single-instruction and run states. Notice also that the CPU can be observed only in the debug-halt state. In practical terms, this means the contents of CPU registers and memory are not updated in the debugger display in the single-instruction state or the run state. Maskable interrupts occurring in any state are latched in the interrupt flag register (IFR).
Figure 72. Stop Mode Execution States

Single-instruction state Cannot observe CPU Can service an interrupt if RUN 1 used Debugger command After executing one instruction Debugger command Run state Cannot observe CPU Can service interrupts
Debugger command, breakpoint, or analysis stop
Debug-halt state Can observe CPU Cannot service interrupts
If you use a RUN 1 command to execute a single instruction, an interrupt can be serviced in the single-instruction state. If you use a STEP 1 command for the same purpose, an interrupt cannot be serviced.
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7.4.2
Real-Time Mode
Real-time mode provides for the debugging of code that interacts with interrupts that must not be disabled. Real-time mode allows you to suspend background code at break events while continuing to execute time-critical interrupt service routines (also referred to as foreground code). In real-time mode, the CPU can operate in the following execution states:
- Debug-halt state. This state is entered through a break event such as the
decoding of a software breakpoint instruction or the occurrence of an analysis breakpoint/watchpoint. This state can also be enter by a request from the host processor. You can place the device into one of the other two states by giving the appropriate command to the debugger. In this state, only time-critical interrupts can be serviced. No other code can be executed. Maskable interrupts are considered time-critical if they are enabled in the debug interrupt enable register (DBGIER). If they are also enabled in the interrupt enable register (IER), they are serviced. The interrupt global mask bit (INTM) is ignored. NMI and RS are also considered time-critical, and are always serviced once requested. It is possible for multiple interrupts to occur and be serviced while the device is in the debug-halt state. Suspending execution adds only one cycle to interrupt latency. When the C28x returns from a time-critical ISR, it reenters the debug-halt state. If a CPU reset occurs (initiated by RS), the device runs the corresponding interrupt service routine until that routine clears the debug enable mask bit (DBGM) in status register ST1. When a reset occurs, DBGM is set, disabling debug events. To reenable debug events, the interrupt service routine must clear DBGM. Only then will the outstanding emulation-suspend condition be recognized. Note: Should a time-critical interrupt occur in real-time mode at the precise moment that the debugger receives a RUN command, the time-critical interrupt will be taken and serviced in its entirety before the CPU changes states.
- Single-instruction state. This state is entered when you you tell the de-
bugger to execute a single instruction by using a RUN 1 command or a STEP 1 command. The CPU executes the single instruction pointed to by the PC and then returns to the debug-halt state (it executes from one interrupt boundary to the next). If an interrupt occurs in this state, the command used to enter this state determines whether that interrupt can be serviced. If a RUN 1 command was
used, the CPU can service the interrupt. If a STEP 1 command was used, the CPU cannot, even if the interrupt is NMI or RS. In real-time mode, if the DBGM bit is 1 (debug events are disabled), a RUN 1 or STEP 1 command forces continuous execution of instructions until DBGM is cleared. Note: If you single-step an instruction in realtime emulation mode and that instruction sets DBGM, the CPU continues to execute instructions until DBGM is cleared. If you want to single-step through a non-time-critical interrupt service routine (ISR), you must initiate a CLRC DBGM instruction at the beginning of the ISR. Once you clear DBGM, you can single-step or place breakpoints.
- Run state. This state is entered when you use a run command from the
debugger interface. The CPU executes instructions until a debugger command or a debug event returns the CPU to the debug-halt state. The CPU can service all interrupts in this state. When an interrupt occurs simultaneously with a debug event, the debug event has priority; however, if interrupt processing began before the debug event occurred, the debug event cannot be processed until the interrupt service routine begins. Figure 73 illustrates the relationship among the three states. Notice that the C28x cannot pass directly between the single-instruction and run states. Notice also that the CPU can be observed in the debug-halt state and in the run state. In the single-instruction state, the contents of CPU registers and memory are not updated in the debugger display. In the debug-halt and run states, register and memory values are updated unless DBGM = 1. Maskable interrupts occurring in any state are latched in the interrupt flag register (IFR).
Figure 73. Real-time Mode Execution States

Single-instruction state Cannot observe CPU Can service an interrupt if RUN 1 used Run state Can observe CPU Can service interrupts
Debugger command After executing one instruction Debugger command Debugger command, breakpoint, or analysis stop
Debug-halt state Can observe CPU Can service time-critical interrupts (including NMI and RS)
If you use a RUN 1 command to execute a single instruction, an interrupt can be serviced in the single-instruction state. If you use a STEP 1 command for the same purpose, an interrupt cannot be serviced.
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Caution about breakpoints within time-critical interrupt service routines

Do not use breakpoints within time-critical interrupt service routines. They will cause the device to enter the debug-halt state, just as if the breakpoint were located in normal code. Once in the debug-halt state, the CPU services requests for RS, NMI, and those interrupts enabled in the DBGIER and the IER. After approving a maskable interrupt, the CPU disables the interrupt in the IER. This prevents subsequent occurrences of the interrupt from being serviced until the IER is restored by a return from interrupt (IRET) instruction or until the interrupt is deliberately re-enabled in the interrupt service routine (ISR). Do not reenable that interrupts IER bit while using breakpoints within the ISR. If you do so and the interrupt is triggered again, the CPU performs a new context save and restarts the interrupt service routine.
7.4.3
Summary of Stop Mode and Real-Time Mode

Figure 74 (page 7-12) is a graphical summary of the differences between the execution states of stop mode and real-time mode. Table 73 (page 7-13) is a summary of how interrupts are handled in each of the states of stop mode and real-time mode.
Emulation Features
7-11
Figure 74. Stop Mode Versus Real-Time Mode

Single-instruction state Cannot observe CPU Can service an interrupt if RUN 1 used Debugger command After executing one instruction Debugger command Run state Cannot observe CPU Can service interrupts
Debugger command, breakpoint, or analysis stop
Debug-halt state Can observe CPU Cannot service interrupts
Stop mode Real-time mode
Debugger command Debugger command Debug-halt state Can observe CPU Can service time-critical interrupts (including NMI and RS) Debugger command, breakpoint, or analysis stop
Debugger command Debugger command After executing one instruction Single-instruction state Cannot observe CPU Can service an interrupt if RUN 1 used
Run state Can observe CPU Can service interrupts
If you use a RUN 1 debugger command to execute a single instruction, an interrupt can be serviced in the single-instruction state. If you use a STEP 1 debugger command for the same purpose, an interrupt cannot be serviced.
7-12
Table 73. Interrupt Handling Information By Mode and State

Mode State If This Interrupt Occurs ... The Interrupt Is ...
Stop
Debug-halt
RS NMI Maskable interrupt
Not serviced Not serviced Latched in IFR but not serviced If running: Serviced If stepping: Not serviced If running: Serviced If stepping: Not serviced If running: Serviced If stepping: Latched in IFR but not serviced Serviced Serviced Serviced Serviced Serviced If time-critical: Serviced. If not time-critical: Latched in IFR but not serviced If running: Serviced If stepping: Not serviced If running: Serviced If stepping: Not serviced If running: Serviced If stepping: Latched in IFR but not serviced Serviced Serviced Serviced
Single-instruction
Run
Real-time
Debug-halt
Single-instruction
Run
Emulation Features
7-13
Note: Unless you are using a real-time operating system, do not enable the realtime operating system interrupt (RTOSINT). RTOSINT is completely disabled when bit 15 in the IER is 0 and bit 15 in the DBGIER is 0.
7-14
Aborting Interrupts With the ABORTI Instruction
7.5 Aborting Interrupts With the ABORTI Instruction

Generally, a program uses the IRET instruction to return from an interrupt. The IRET instruction restores all the values that were saved to the stack during the automatic context save. In restoring status register ST1 and the debug status register (DBGSTAT), IRET restores the debug context that was present before the interrupt. In some target applications, you might have interrupts that must not be returned from by the IRET instruction. Not using IRET can cause a problem for the emulation logic, because the emulation logic assumes the original debug context will be restored. The abort interrupt (ABORTI) instruction is provided as a means to indicate that the debug context will not be restored and the debug logic needs to be reset to its default state. As part of its operation, the ABORTI instruction:
- Sets the DBGM bit in ST1. This disables debug events. - Modifies select bits in DBGSTAT. The effect is a resetting of the debug
context. If the CPU was in the debug-halt state before the interrupt occurred, the CPU does not halt when the interrupt is aborted. Teh CPU automatically switches to the run state. If you want to abort an interrupt, but keep the CPU halted, insert a breakpoint after the ABORTI instruction. The ABORTI instruction does not modify the DBGIER, the IER, the INTM bit, or any analysis registers (for example, registers used for breakpoints, watchpoints, and data logging).
Emulation Features
7-15
DT-DMA Mechanism
7.6 DT-DMA Mechanism

The debug-and-test direct memory access (DT-DMA) mechanism provides access to memory, CPU registers, and memory-mapped registers (such as emulation registers and peripheral registers) without direct CPU intervention. DT-DMAs intrude on CPU time; however, you can block them by setting the debug enable mask bit (DBGM) in ST1. Because the DT-DMA mechanism uses the same memory-access mechanism as the CPU, any read or write access that the CPU can perform in a single operation can be done by a DT-DMA. The DT-DMA mechanism presents an address (and data, in the case of a write) to the CPU, which performs the operation during an unused bus cycle (referred to as a hole). Once the CPU has obtained the desired data, it is presented back to the DT-DMA mechanism. The DT-DMA mechanism can operate in the following modes:
- Nonpreemptive mode.The DT-DMA mechanism waits for a hole on the
desired memory buses. During the hole, the DT-DMA mechanism uses them to perform its read or write operation. These holes occur naturally while the CPU is waiting for newly fetched instructions, such as during a branch.
- Preemptive mode. In preemptive mode, the DT-DMA mechanism forces
the creation of a hole and performs the access. Nonpreemptive accesses to zero-wait-state memory take no cycles away from the CPU. If wait-stated memory is accessed, the pipeline stalls during each wait state, just as a normal memory access would cause a stall. In realtime mode, DT-DMAs to program memory cannot occur when application code is being run from memory with more than one wait state. DT-DMAs can be polite or rude.
- Polite accesses. Polite DT-DMAs require that DBGM = 0. - Rude accesses. Rude DT-DMAs ignore DBGM.
Figure 75 summarizes the process for handling a request from the DT-DMA mechanism.
7-16
DT-DMA Mechanism
Figure 75. Process for Handling a DT-DMA Request

DT-DMA mechanism requests access
Request polite or rude? Polite No DBGM = 0? Access denied Yes Mode nonpreemptive or preemptive? Nonpreemptive Wait for hole
Rude
Preemptive
Force a hole
Access performed
Some key concepts of the DT-DMA mechanism are:

- Even if DBGM = 0, when the mechanism is in nonpreemptive mode, it
must wait for a hole. This minimizes the intrusiveness of the debug access on a system.
- Real-time-mode accesses are typically polite (although there may be rea-
sons, such as error recovery, to perform rude accesses in real-time mode). If the DBGM bit is permanently set to 1 due to a coding bug but you need to regain debug control, use rude accesses, which ignore the state of DBGM.
- In stop mode, DBGM is ignored, and the DT-DMA mode is set to preemp-
tive. This ensures that you can gain visibility to and control of your system if an otherwise unrecoverable error occurs (for example, if ST1 is changed to an undesired value due to stack corruption).
DT-DMA Mechanism
- The DT-DMA mechanism does not cause a program-flow discontinuity. No
interrupt-like save/restore is performed. When a preemptive DT-DMA forces a hole, no program address counters increment during that cycle.
- A DT-DMA request awakens the device from the idle state (initiated by the
IDLE instruction). However, unlike returning from an interrupt, the CPU returns to the idle state upon completion of the DT-DMA. Note: The information shown on the debugger screen is gathered at different times from the target; therefore, it does not represent a snapshot of the target state, but rather a composite. It also takes the host time to process and display the data. The data does not correspond to the current target state, but rather, the target state as of a few milliseconds ago.
7-18
Analysis Breakpoints, Watchpoints, and Counter(s)
7.7 Analysis Breakpoints, Watchpoints, and Counter(s)

All C28x devices include two analysis units AU1 and AU2. Analysis Unit 1 (AU1) counts events or monitors address buses. Analysis Unit 2 (AU2) monitors address and data buses. You can configure these two analysis units as analysis breakpoints or watchpoints. In addition, AU1 can be configured as a benchmark counter or event counter. This section describes thee types of analysis features: analysis breakpoints, watchpoints, and counters. Typical analysis unit configurations are presented in section 7.7.4. Data logging is described in section 7.8.
7.7.1
Analysis Breakpoints
An analysis breakpoint is sometimes called a hardware breakpoint, because it acts like a software breakpoint instruction (in this case, the ESTOP0 instruction) but does not require a modification to the application software. An analysis breakpoint triggers a debug event when an instruction at a breakpoint address would have entered the decode 2 phase of the pipeline; this halts the CPU before the instruction is executed. A bus comparator watches the program address bus, comparing its contents against a reference address and a bit mask value. Consider the following example. If a hardware breakpoint is set at T0, the CPU stops after returning from the T1 subroutine, with the instruction counter (IC) pointing to T0.
NOP CALL T0: MOVB SB T1: NOP RET T2: NOP T1 AL, #0x00 TIMINGS, UNC
Hardware breakpoints allow masking of address bits. For example, a hardware breakpoint could be placed on the address range 00 02001600 02FF16 by specifying the following mask address, where the eight LSBs are dont cares: 00 0000 0000 0010 XXXX XXXX2
7.7.2
Watchpoints
A hardware watchpoint triggers a debug event when either an address or an address and data match a compare value. The address portion is compared against a reference address and bit mask, and the data portion is compared against a reference data value and a bit mask.
When comparing two addresses, you can set two watchpoints. When comparing an address and a data value, you can set only one watchpoint. When performing a read watchpoint, the address is available a few cycles earlier than the data; the watchpoint logic accounts for this. The point where execution stops depends on whether the watchpoint was a read or write watchpoint, and whether it was an address or an address/data read watchpoint. In the following example, a read address watchpoint occurs when the address X is accessed, and the CPU stops with the instruction counter (IC) pointing three instructions after that point:
MOV MOV nop nop nop AR4,#X AL,*+AR4[0] ; Data read
; The IC will point here
For a read watchpoint that requires both an address and data match, the CPU stops with the IC pointing six instructions after that point:
MOV MOV nop nop nop nop nop nop AR4,#X AL,*+AR4[0] ; Data read
In the following example, a write address watchpoint occurs when the address Y is accessed, and the CPU stops with the IC pointing six instructions after that point:
MOV MOV nop nop nop nop nop nop AR4,#Y *+AR4[0],AL ; Data write
7.7.3
Benchmark Counter/Event Counter(s)

The 40-bit performance counter on the C28x can be used as a benchmark counter to increment every CPU clock cycle (it can be configured not to count when the CPU is in the debug-halt state). Wait states affect the counter. Wait states in the read 1 and write pipeline phases of an executing instruction affect the counter, regardless of whether an instruction is being single-stepped or run. However, wait states in the fetch 1 pipeline phase do not affect the counter during single-stepping, because the cycle counting does not begin until the de-
7-20
code 2 pipeline phase. The counter counts wait states caused by instructions that are fetched but not executed. In most cases, these effects cancel each other out. Benchmarking is best used for larger portions of code. Do not rely heavily on the precision of the benchmarking. (For more information about the pipeline, see Chapter 4.) Alternatively, you can configure the 40-bit performance counter as two 16-bit or one 32-bit event counter if you want to generate a debug event when the counter equals a match value. The comparison between the counter value and the match value is done before the count value is incremented. For example, suppose you initialize a counter to 0. A match value of 0 causes an immediate debug event (when the action to be counted occurs), and the counter holds 1 afterward. You can also clear the counter when a hardware breakpoint or address watchpoint occurs. With this feature, you can implement a mechanism similar to a watchdog timer: if a certain address is not seen on the address bus within a certain number of CPU clock cycles, a debug event occurs.
7.7.4
Typical Analysis Unit Configurations

Each analysis unit can be configured to perform one analysis job at a time. Typical configurations for these two analysis units can be any one of the following:
- Two analysis breakpoints (i.e., hardware breakpoints)
Detect when an instruction is executed from a specified address or range of addresses. Each hardware breakpoint only requires one analysis unit.
- Two hardware address watch points
Detect when any value is either read from or written to a specified address or a range of addresses. In this case, the data written or read is not specified. Only the address of the location is specified and whether to watch for reads or writes to that address. Each watchpoint only requires one analysis unit.
- One address with data watchpoint
Detect when a specified data value is either read from or written to a specified address. In this configuration you can either watch for a read or a write but not both reads and writes. This type of watchpoint requires both analysis units.
- A set of two chained breakpoints
Detect when a given instruction is executed after another specified instruction.

- A benchmark counter/event counter
The benchmark counter is only available with analysis unit 1. This counter can be used as a benchmark counter to count cycles or instructions. It can also be used to count AU2 events. Configuration of the analysis resources is supported in Code Composer Studio. For more information on configuring these, use the Code Composer online help.
7-22
Data Logging
7.8 Data Logging

Data logging enables the C28x to send selected memory values to a host processor using the standard JTAG port and an XDS510 or other compatible scan controller. You control data logging activity with your application code. To perform data logging, you must create a linear buffer of 32-bit words to hold a packet of information. Your application code controls the size, format, and location of this buffer and also determines when to send a buffers contents to the host. You can control the size of a data logging buffer in two ways:
- Specify a count value in the upper eight bits of ADDRH (when the number
of 32-bit words you want to log is between 1 and 256)

- Specify an end address
Note: When the debugger is not active, the data logging transfers are considered complete as soon as they are enabled to prevent the application software from getting stuck when there is nothing to receive the data.
7.8.1
Creating a Data Logging Transfer Buffer

To create a data logging transfer buffer, follow these steps in your application code: 1) Execute the EALLOW instruction to enable access to emulation registers. 2) Specify the start address of the buffer in ADDRL and the six LSBs of ADDRH (see Figure 76 and Figure 77). The address in ADDRL and ADDRH is called the transfer address. 3) Use either of the following methods to specify when data logging is to end: a) If the number of words you want to log is between 1 and 256, specify a count value in the upper eight bits of ADDRH (see Figure 77). The form of the count value is 256n, where n is the number of 32-bit words you want to log. As each word is transferred, both the transfer address and the count value are decremented. b) If the number of words you want to log is greater than 256, specify a data logging end address in REFL and the six LSBs of REFH (see Figure 78 and Figure 79). Load the ten MSBs of REFH with 0s. When using this method, be sure to set the data logging end address control register (EVT_CNTRL) first, and then the DMA control register
Data Logging
(DMA_CNTRL). EVT_CNTRL is described in Table 75 (page 7-26), and DMA_CNTRL is described in Table 74 (page 7-25). Note: The application must not read from the end address of the buffer during the data logging operation. When the end address appears on the address bus, the C28x ends the transfer. 4) Execute the EDIS instruction to disable access to emulation registers. See Table 74 and Table 75 on the following pages for descriptions of the registers associated with data logging.
Figure 76. ADDRL (at Data-Space Address 00 083816 )

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 LSBs of transfer address
Figure 77. ADDRH (at Data-Space Address 00 083916 )

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word counter
Reserved
6 MSBs of transfer address
Figure 78. REFL (at Data-Space Address 00 084A16 )

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 LSBs of end address
Figure 79. REFH (at Data-Space Address 00 084B16 )

15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0
6 MSBs of end address
7-24
Data Logging
Table 74. Start Address and DMA Registers

Address 00 083816 00 083916 Name ADDRL Access R/W Description Start address register (lower 16 bits) 15:0 Lower 16 bits of start address Word counter/start address register (upper 6 bits) 15:8 Word counter. When using this to stop the data logging transfer, set the counter to 256 n, where n is the number of 32-bit words to transfer. Otherwise set the counter to 0. 7:6 Reserved. Set to 0. 5:0 Upper 6 bits of start address DMA control register 15:14 Set to 0 13 Set to 1 12 Set to 1 11 Give higher priority to: 0: CPU (nonpreemptive mode) 1: Data logging (preemptive mode) 10 Allow data logging during time-critical ISR? 0: No 1: Yes 9 Allow data logging while DBGM = 1? 0: No (polite accesses) 1: Yes (rude accesses) 8:6 Set to 1 5:4 0: EMU0/EMU1 using TCK 1: EMU0/EMU1 using FCK/2 2: JTAG signals 3: Reserved 3:2 Method for ending data logging session: 0: Use the count register to stop data logging 1: Use an end address to stop data logging 1:0 Data logging control/status: 0: Release resource from data logging operation 1: Claim resource for data logging operation 2: Enable resource for data logging operation 3: Data logging operation is complete. Bits 14:10 are corrupted when this occurs. DMA ID register 15:14 Resource control: 0: Resource is free 1: Application owns resource 2: Debugger owns resource 13:12 Set to 3. 11:0 Set to 1.
ADDRH
R/W
00 083E16
DMA_CNTRL
R/W
00 083F16
DMA_ID
Emulation Features
7-25
Data Logging
Table 75. End-Address Registers

Address 00 084816 00 084916 00 084A16 00 084B16 Name MASKL MASKH REFL Access R/W R/W R/W Description Set to 0 Set to 0 Data logging end reference address (lower 16 bits) 15:0 Lower 16 bits of start address Data logging end reference address (upper 6 bits) 15:6 Set to 0 5:0 Upper 6 bits of start address Data logging end address control register 15:14 Set to 0 13 Set to 1 12 Set to 1 11:5 Set to 0 4:2 Set to 1 1:0 End-address resource control/status: 0: Release end-address resource. 1: Claim end-address resource. 2: Enable end-address resource. 3: Data logging operation has ended. Bits 14:10 are corrupted when this occurs. Data logging end address ID register 15:14 Resource control: 0: Resource is free 1: Application owns resource 2: Debugger owns resource 13:12 Set to 1 11:0 Set to 2
REFH
R/W
00 084E16
EVT_CNTRL
R/W
00 084F16
EVT_ID
7.8.2
Accessing the Emulation Registers Properly

Make sure your application code follows the following protocol when accessing the emulation registers that have been provided for data logging. Each resource has a control register and an ID register. 1) Enable writes to memory-mapped registers by using the EALLOW instruction. 2) Write to the appropriate control register to claim the resource you want to use. The resource for data logging transfers uses DMA_CNTRL (see Table 74 on page 7-25). The resource for detecting the data logging end address uses EVT_CNTRL (see Table 75).
7-26
Data Logging
3) Wait at least three cycles so that the write to the control register (done in the write phase of the pipeline) occurs before the read from the ID register in step 4. You can fill in the extra cycles with NOP (no operation) instructions or with other instructions that do not involve accessing the emulation registers. 4) Read the appropriate ID register and verify that the application is the owner. The resource for data logging transfers uses DMA_ID (see Table 74 on page 7-25). The resource for detecting the data logging end address uses EVT_ID (see Table 75 on page 7-26). If the application is not the owner, then go back to step 2 until this succeeds (you may want a time-out function to prevent an endless loop). This step is optional. The application would fail to become the owner only if the debugger already owns the resource. 5) If the application is the owner, the remaining registers for that function can be programmed, and the control register written to again, to enable the function. However, if the application is not the owner, then all of its writes are ignored. 6) Disable writes to memory-mapped emulation registers by executing the EDIS instruction. If an interrupt occurs between the EALLOW instruction in step 1 and the EDIS instruction in step 6, access to emulation registers are automatically disabled by the CPU before the interrupt service routine begins and automatically reenabled when the CPU returns from the interrupt. This means that there is no need to disable interrupts between the EALLOW instruction and the EDIS instruction. The debugger can, at your request, seize ownership of a register from the application; however, that is not the normal mode of operation.
7.8.3
Data Log Interrupt (DLOGINT)

The completion of a data logging transfer (determined either by the word counter or by the end address) triggers a DLOGINT request. DLOGINT is serviced only if it is properly enabled. If the CPU is halted in real-time mode, DLOGINT must be enabled in both the DBGIER and the IER. Otherwise, DLOGINT must be enabled in the IER and by the INTM bit in status register ST1. This interrupt capability is most useful when there are multiple buffers of data to be transferred through data logging and the completion of one transfer should begin the next.
Data Logging
7.8.4
Examples of Data Logging

Example 71 shows how to log 20 32-bit words, starting at address 00 010016 in data memory. The accesses are preemptive (they have higher priority than the CPU) and rude (they ignore the state of the DBGM bit). In addition, data logging can occur during time-critical interrupt service routines. The application can determine whether the data logging operation is complete by polling the LSB of the DMA control register (DMA_CNTRL) at 00 083E16. When the operation is complete, that bit is set to 1.
Example 71. Initialization Code for Data Logging With Word Counter
; Base addresses ADMA .set 0838h ; Offsets DMA_ADDRL DMA_ADDRH DMA_CNTRL DMA_ID EALLOW MOV MOV NOP NOP NOP CMP B
.set .set .set .set
0 1 6 7
AR4, #ADMA *+AR4[#DMA_CNTRL],#1
; AR4 pointing to register base addr ; Attempt to claim resource
*+AR4[#DMA_ID],#7001h FAIL, NEQ
; Value expected in ID register ; If we dont see the correct ID, then we ; failed (the resource is already in use)
MOV MOV MOV EDIS
; Set starting address of buffer, ; and then the count *+AR4[DMA_ADDRH],#((256 20) << 8) *+AR4[DMA_CNTRL],#3E62h
*+AR4[#DMA_ADDRL],#0100h
Example 72 shows how to log from address 00 010016 to address 00 02FF16 in data memory. The accesses are nonpreemptive (they have lower priority than the CPU), and are polite (they are not performed when the DBGM bit is 0). The data logging cannot occur when a time-critical interrupt is being serviced. An end address of 00 02FF16 is used to end the transfer. The application must not read from 00 02FF16 during the data logging; a read from that address stops the data logging. As in Example 71, the application can poll the LSB of DMA_CNTRL for a 1 to determine whether the data logging operation is complete.
7-28
Data Logging
Example 72. Initialization Code for Data Logging With End Address
; Base addresses ADMA .set 0838h DEVT .set 0848h ; Offsets DMA_ADDRL DMA_ADDRH DMA_CNTRL DMA_ID MASKL MASKH REFL REFH EVT_CNTRL EVT_ID EALLOW MOV MOV MOV MOV NOP NOP NOP CMP B CMP B MOV MOV MOV MOV MOV MOV MOV MOV EDIS
.set .set .set .set .set .set .set .set .set .set
0 1 6 7 0 1 2 3 6 7
AR5, #DEVT AR4, #ADMA *+AR5[#EVT_CNTRL],#1 *+AR4[#DMA_CNTRL],#1
; ; ; ;
AR5 pointing to End Address registers AR4 pointing to Start/Control base Attempt to claim End Address Attempt to claim Start/Control
*+AR5[#EVT_ID],#5002h FAIL, NEQ *+AR4[#DMA_ID],#7001h FAIL, NEQ *+AR5[#MASKL],#0 *+AR5[#MASKH],#0 *+AR5[#REFL],#02FFh *+AR5[#REFH],#0 *+AR5[#EVT_CNTRL],# ( 2 | *+AR4[#DMA_ADDRL],#0100h *+AR4[DMA_ADDRH],#0 *+AR4[DMA_CNTRL],#3066h
; Value expected in ID register ; If we dont see the correct ID, FAIL ; Value expected in ID register ; If we dont see the correct ID, FAIL ; Attempt to claim End ; Attempt to claim End ; Stop data logging at ; Attempt to claim End (1<<2) | (1<<12) | Address Address address 0x02FF Addr (1<<13) )
; Set buffer start address and then the count
Emulation Features
7-29
Sharing Analysis Resources
7.9 Sharing Analysis Resources

You can use analysis breakpoints, watchpoints, and a benchmark/event counter through the debugger, and you can use data logging through application code. Table 76 lists the analysis resources, and Figure 710 shows which resources are available to be used at the same time. When the application owns analysis resources, they will be cleared (made unowned and set to the completed state) by a reset. When the debugger owns the resources, they are not cleared by reset but by the JTAG test-logic reset. This ensures that when you are using the debugger, the resources can be used even while the target system undergoes a reset.
Table 76. Analysis Resources

Resource BA0 BA1 BD Purpose Break on contents of program address or memory address bus Break on contents of program address or memory address bus Break on contents of program data, memory read data, or memory write data in addition to an address bus Perform data logging using counter Count CPU cycles
Data log Benchmark
Figure 710. Valid Combinations of Analysis Resources

BA0 BA0 BA1 BD Data log Benchmark
BA1 Yes Yes No No No
BD No No Yes No No
Data log Yes No No Yes No
Benchmark Yes No No No Yes
Yes Yes No Yes Yes
The data logging mode that uses the word counter allows this combination, but not the data logging mode that uses the end address (see section 7.8, Data Logging).
7-30
Diagnostics and Recovery
7.10 Diagnostics and Recovery

Debug registers within the CPU keep track of the state of several key signals. This allows diagnosis of such problems as a floating READY signal, NMI signal, or RS (reset) signal. Should the debug software attempt an operation that does not complete after a certain time-out period (as determined by the debug software), it attempts to determine the probable cause and display the situation to you. You can then abort, correct the situation or allow it to correct itself, or chose to override it. Such situations include:
- RS being asserted - A ready signal not being asserted for a memory access - NMI being asserted - The absence of a functional clock - The occurrence of a JTAG test-logic-reset
Emulation Features
7-31
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7-32
Appendix AppendixA A
Register Quick Reference

For the status and control registers of the 28x, this appendix summarizes:
- Their reset values - The instructions available for accessing them - The functions of their bits
Topic
A.1 A.2
Page
Reset Values of and Instructions for Accessing the Registers . . . . A-2 Register Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A-1
Reset Values of and Instructions for Accessing the Registers
A.1 Reset Values of and Instructions for Accessing the Registers

Table A1 lists the CPU status and control registers, their reset values, and the instructions that are available for accessing the registers.
Table A1. Reset Values of the Status and Control Registers

Register ST0 ST1 IFR IER DBGIER
Note:
Description Status register 0 Status register 1 Interrupt flag register Interrupt enable register Debug interrupt enable register
Reset Value 0000 0000 0000 00002 0000 M000 0000 V0112 0000 0000 0000 00002 0000 0000 0000 00002 0000 0000 0000 00002
Instructions PUSH, POP, SETC, CLRC PUSH, POP, SETC, CLRC PUSH, POP, AND, OR MOV, AND, OR PUSH, POP
V: Bit 3 of ST1 (the VMAP bit) depends on the level of the VMAP input signal at reset. If the VMAP signal is low, the VMAP bit is 0 after reset; if the VMAP signal is high, the VMAP bit is 1 after reset. For C28x devices that do not pin out VMAP, the signal is tied high internal to the device. M: Bit 11 of ST1 (the M0M1MAP bit) depends on the level of the M0M1MAP input signal at reset. If the M0M1MAP signal is low, the bit is 0, high bit is 1. For C28x devices that do not pinout MOM1MAP, the signal is tied high internal to the device.
Register Figures
A.2 Register Figures

The following figures summarize the content of the 28x status and control registers. Each figure in this section provides information in this way:
- The value shown in the register is the value after reset. - Each unreserved bit field or set of bits has a callout that very briefly de-
scribes its effect on the processor.

- Each nonreserved bit field or set of bits is labeled with one of the following
symbols:
J J
R indicates that your software can read the bit field but cannot write to it. R/W indicates that your software can read the bit field and write to it.
- Where needed, footnotes provide additional information for a particular
figure.
A-3
Register Figures
Figure A1. Status register ST0

15 14 13 12 11 10
OVC/OVCU

0 0
0 PM
0 V
0 N
0 Z
0 C
0 TC
0 OVM
0 SXM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Negative flag 0 Negative condition false 1 Negative condition true
Sign-extension mode 0 Sign extension suppressed 1 Sign extension mode selected
Overflow flag 0 Flag is reset 1 Overflow detected Product shift mode 0 0 0 Left shift by 1 0 0 1 No shift 0 1 0 Right shift by 1, sign extended 0 1 1 Right shift by 2, sign extended 1 0 0 Right shift by 3, sign extended 1 0 1 Right shift by 4, sign extended 1 1 0 Right shift by 5, sign extended 1 1 1 Right shift by 6, sign extended Overflow counter Behaves differently for signed and unsigned operations: Signed operations (OVC) Increments by 1 for each positive overflow; Decrements by 1 for each negative overflow. Unsigned operations (OVCU) Increments by 1 for ADD operations that generate a Carry Decrements by 1 for SUB operations that generate a Borrow
ACC overflow mode 0 Results overflow normally 1 Overflow mode selected Test/control flag Holds result of test performed by TBIT or NORM instruction
Carry bit 0 Carry not detected/borrow detected 1 Carry detected/borrow not detected Zero flag 0 Zero condition false 1 Zero condition true
Note:
For more details about ST0, see section 2.3 on page 2-16.
Register Figures
Figure A2. Status register ST1, Bits158

15 14 13 12 11 10 9
0 ARP
R/W
0 XF
R/W
0 MOM1MAP
R
0 CNF
R/W
0
R/W
OBJMODE
AMODE
R/W
XF status bit 0 XFS output signal low 1 XFS output signal is high Address mode bit 0 C28x/C27x processing mode 1 C2xLP addressing modes Object compatibility mode bit 0 C27x compatible map 1 C28x/C2xLP compatible map
Auxiliary register pointer 0 0 0 XAR0 selected 0 0 1 XAR1 selected 0 1 0 XAR2 selected 0 1 1 XAR3 selected 1 0 0 XAR4 selected 1 0 1 XAR5 selected 1 1 0 XAR6 selected 1 1 1 XAR7 selected
C2xLP-mapping mode bit 0 PAGE0 stack addressing mode 1 PAGE0 direct addressing mode M0 and M1 mapping mode bit 0 M0 is 03FF data, 4007FF pro1 gram M0 is 03FF data and program SP starts at 0x400.
A-5
Register Figures
Figure A3. Status Register ST1, Bits 70

7 6 5 4
0 IDLESTAT
R
0 EALLOW
R/W
0 LOOP
R
0 SPA
R/W

3 2
1 DBGM
R/W
1 INTM
R/W
VMAP
R/W
PAGE0
R/W
Stack pointer alignment bit 0 Stack pointer has not been 1 aligned to even address Stack pointer has been aligned to even address Loop instruction status bit 0 LOOPNZ/LOOPZ instruction done 1 LOOPNZ/LOOPZ instruction in progress Emulation access enable bit 0 Access to emulation registers disabled 1 Access to emulation registers enabled IDLE status flag bit 0 IDLE instruction done 1 IDLE instruction in progress
Interrupt enable mask bit 0 Maskable interrupts globally enabled 1 Maskable interrupts globally disabled Debug enable mask bit 0 Debug events enabled 1 Debug events disabled
PAGE0 addressing configuration bit 0 PAGE0 stack addressing mode 1 PAGE0 direct addressing mode
Vector map bit 0 Interrupt vectors mapped to programmemory addresses 00 00001600 003F16 1 Interrupt vectors mapped to programmemory addresses 3F FFC0163F FFFF16

These reserved bits are always 0s and are not affected by writes. The VMAP bit depends on the level of the VMAP input signal at reset. If the VMAP signal is low, the VMAP bit is 0 after reset; if the VMAP signal is high, the VMAP bit is 1 after reset. For C28x devices that do not pin out the VMAP signal, the signal is tied high internal to the device. For more details about ST1, see section 2.4 on page 2-34.
Note:
Register Figures

Figure A4. Interrupt flag register (IFR)
15 14 13 12
11 0
10 0
9 0
8 0
RTOSINT
DLOGINT
INT14
INT13
INT12
INT11
INT10
INT9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INT13 flag bit 0 INT13 not pending 1 INT13 pending INT14 flag bit 0 INT14 not pending 1 INT14 pending DLOGINT flag bit 0 DLOGINT not pending 1 DLOGINT pending RTOSINT flag bit 0 RTOSINT not pending 1 RTOSINT pending
INT9 flag bit 0 INT9 not pending 1 INT9 pending INT10 flag bit 0 INT10 not pending 1 INT10 pending INT11 flag bit 0 INT11 not pending 1 INT11 pending INT12 flag bit 0 INT12 not pending 1 INT12 pending

7 6 5 4
3 0
2 0
1 0
0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
For more details about the IFR, see section 3.3.1 on page 3-7.
A-7
Register Figures

Figure A5. Interrupt enable register (IER)
15 14 13 12
11 0
10 0
9 0
8 0
RTOSINT
DLOGINT
INT14
INT13
INT12
INT11
INT10
INT9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INT13 enable bit 0 INT13 disabled 1 INT13 enabled INT14 enable bit 0 INT14 disabled 1 INT14 enabled DLOGINT enable bit 0 DLOGINT disabled 1 DLOGINT enabled RTOSINT enable bit 0 RTOSINT disabled 1 RTOSINT enabled
INT9 enable bit 0 INT9 disabled 1 INT9 enabled INT10 enable bit 0 INT10 disabled 1 INT10 enabled INT11 enable bit 0 INT11 disabled 1 INT11 enabled INT12 enable bit 0 INT12 disabled 1 INT12 enabled

7 6 5 4
3 0
2 0
1 0
0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
For more details about the IER, see section 3.3.2 on page 3-8.
Register Figures

Figure A6. Debug interrupt enable register (DBGIER)
15 14 13 12
11 0
10 0
9 0
8 0
RTOSINT
DLOGINT
R/W
INT14
INT13
INT12
INT11
INT10
INT9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INT13 debug enable bit 0 INT13 disabled 1 INT13 enabled INT14 debug enable bit 0 INT14 disabled 1 INT14 enabled DLOGINT debug enable bit 0 DLOGINT disabled 1 DLOGINT enabled RTOSINT debug enable bit 0 RTOSINT disabled 1 RTOSINT enabled
INT9 debug enable bit 0 INT9 disabled 1 INT9 enabled INT10 debug enable bit 0 INT10 disabled 1 INT10 enabled INT11 debug enable bit 0 INT11 disabled 1 INT11 enabled INT12 debug enable bit 0 INT12 disabled 1 INT12 enabled

7 6 5 4
3 0
2 0
1 0
0 0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
For more details about the DBGIER, see section 3.3.2 on page 3-8.
A-9
Appendix AppendixB A
C2xLP and C28x Architectural Differences

This appendix highlights some of the architecture differences between the C2xLP and the C28x. Not all of the changes are listed here. An emphasis is placed on those changes of which you need to be aware while migrating from a C2xLP-based design to a C28x design. In particular changes in CPU registers and memory map are addressed.
Topic
B.1 B.2 B.3
Page
Summary of Architecture Differences Between C2xLP and C28x . . B-2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
B-1
Summary of Architecture Differences Between C2xLP and C28x
B.1 Summary of Architecture Differences Between C2xLP and C28x

The C28x CPU features many improvements over the C2xLP CPU. A summary of the enhancements is given here.
Table B1. General Features

Feature Program memory space Data memory space Number of internal buses Addressable word size Multiplier Maskable CPU interrupts C2xLP 64K (16 address signals) 64K (16 address signals) 3 (prog, data-read, data-write) 16 16 bits 6 C28x 4M (22 address signals) 4G (32 address signals) 3 (prog, data-read, data-write) 16/32 16/32 bits 14
B.1.1
Enhancements of the C28x over the C2xLP:

-
Much higher MHz operation 32 x 32 MAC 16 x16 Dual MAC 32-bit register file 32-bit single-cycle operations 4M linear program-address reach 4G linear data-address reach Dedicated software stack pointer Monitorless real-time emulation 4050% better C code efficiency than C2xLP 2030% better assembly code efficiency than C2xLP Atomic operation eliminates need to disable/re-enable interrupts Extended debugging features (Analysis block, data logging, etc.) Faster interrupt context save/restore More efficient addressing modes Unified memory map Byte packing and unpacking operations
When you first recompile your C2xLP code set for C28x, you will not be able to take advantage of every enhancement since you are limited by the original source code. Once you begin migrating your code, however, you will quickly begin to take advantage of the full capabilities the C28x offers. See Appendix D for help with migration to C28x.
Registers
B.2 Registers
The register modifications to the C2xLP are shown in Figure B1. Registers that are shaded show the changes or enhancements on the C28x. The italicized names on the left are the original C2xLP names for the registers. The names on the right are the C28x names for the registers.
Figure B1. Register Changes From C2xLP to C28x
32 bits C2xLP Names TREG PREG ACC 16 bits T or TH PH AH 16 bits TL PL AL C28x Names XT P ACC SP DP AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 PC AR0H AR1H AR2H AR3H AR4H AR5H AR6H AR7H 9 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 DP XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 PC RPC 22 bits IMR IFR ST0 ST1
On
IER DBGIER IFR ST0 ST1
the C2xLP, IMR and IFR were memory mapped. On the C28x, they are registers.
B-3
Registers
B.2.1 CPU Register Changes

A brief description of the register modifications is given below. For a complete description of each register, see descriptions in the C2xLP and C28x Reference Guides.
XT Multiplicand register. The 32-bit multiplicand register is called XT on the C28x. The C2xLP TREG is represented by the upper 16 bits (T). The lower 16 bit area is known as TL. The assembler will also accept TH in place of T for the upper 16 bits of the XT register. Product register. This register is the same as the C2xLP PREG. You can separately access the high half (PH) or the low half (PL) on the C28x Accumulator. The size of ACC is the same on the C28x. Access to the register has been enhanced. On C28x, you can access it as two 16-bit registers (AL and AH). Stack Pointer. The SP is new on the C28x. It points directly to the C28x software stack Auxiliary registers. All of the auxiliary registers (XARn) are increased to 32 bits on the C28x. This enables a full 32-bit address reach in data space. Some instructions separately access the low half of the registers (ARn). Program counter. The PC is 22 bits on C28x. On the C2xLP, the PC is 16 bits Return program counter. The RPC register is new on the C28x. When a call operation is performed, the return address is saved in the RPC register and the old value in the RPC is saved on the stack. When a return operation is performed, the return address is read from the RPC register and the value on the stack is written into the RPC register. The net result is that return operations are faster (4 instead of 8 cycles). This register is only used when certain call and return instructions are used. Normal call and return instructions bypass this register. Interrupt enable register. The IER is analogous to the Interrupt Mask Register (IMR) on the C2xLP. It performs the same function, however, the name has changed to more appropriately describe the function of the register. Each bit in the register enables one of the maskable interrupts. On the C2xLP, there are six maskable CPU interrupts. On the C28x CPU, there are 16 CPU interrupts. On the C2xLP, the IMR was memory mapped. Debug interrupt-enable register. The DBGIER is new on the C28x. It enables interrupts during debug events and allows the processor and debugger to perform real-time emulation. Interrupt flag register. The IFR functions the same as on the C2xLP. There are more valid bits in this register to accommodate the additional interrupts on the C28x. On the C2xLP, the IFR was memory mapped.
ACC
SP XAR0 XAR7
PC RPC
IER
DBGIER
IFR
Registers
ST0/ST1 DP
Status Registers. The C28x status register bit positions are different compared to the C2xLP. Figure B3 shows the differences. Data Page Pointer. On the C2xLP the DP is part of status register ST0. The DP on the C28x is a separate register and is increased from 9 to 16 bits.
B.2.2 Data Page (DP) Pointer Changes

B.2.2.1 C2xLP DP The direct addressing mode on the C2xLP can access any data memory location in the 64K address range of the device using a 9-bit data page pointer and a 7-bit offset, supplied by the instruction, which is concatenated with the data page pointer value to form the 16-bit data address location. An example C2xLP operation is as follows:
LDP #VarA LACL VarA ; Load DP with page location for VarA ; Load ACC low with contents of VarA
The first instruction initializes the DP register value with the page location for the specified variable. Each page is 128 words in size. The assembler/linker automatically resolve the page value by dividing the absolute address of the specified location by 128. For example:
If VarA address = 0x3456, then the DP value is: DP(8:0) = 0x3456/128 = 0x69
The next instruction will then calculate the 7-bit offset of the specified variable within the 128-word page. This offset value is then embedded in the address field for that instruction. The assembler/linker automatically resolves the offset value by taking the first 7 bits of the absolute address of the specified location. For example:
If VarA address = 0x3456, then the 7bit offset value is: 7-bit offset = 0x3456 & 0x007F = 0x56
B.2.2.2 C28x DP The C28x also supports the direct addressing mode using the DP register; however, the following changes and enhancements have been made: - Supports 22-bit address reach - DP increased from 9 to 16 bits - DP is a separate 16-bit register - When AMODE == 0, page size is 64 words and DP(15:0) is used - When AMODE == 1, page size is 128 words and DP(15:1) is used, bit 0 of DP is ignored When AMODE == 1, the DP and the direct addressing mode behaves identically to the C2xLP but are enhanced to 22-bit address reach from 16. When
C2xLP and C28x Architectural Differences B-5
Registers
AMODE == 0, the page size is reduced by half. This was done to accommodate other useful addressing modes. The mapping of the direct addressing modes between the C2xLP and the C28x is as shown in Figure B2.
Figure B2. Direct Addressing Mode Mapping

16 bit address 15 C2xLP 15 DP (8:0) 22 bit address 7 6 7-bit offset 0 0
21 C28x 21 AMODE = 1: AMODE = 0: 15 DP (15:1) DP (15:0)
7 6 5 7-bit offset 6-bit offset
Using the previous example, the assembler/linker will initialize the DP and offset values as follows on the C28x: C2xLP Original Source Mode (v28 m20 mode, AMODE == 1)
LDP #VarA LACL VarA ; DP(15:0) = 0x3456/128 << 1 = 0x00D1 ; 7-bit offset = 0x3456 & 0x007F = 0x56
Equivalent C28x Mnemonics (after C2xLP source is reassembled with the C28x assembler)
MOVZ MOVU DP,#VarA ; DP(15:0) = 0x3456/128 << 1 = 0x00D1 ACC,@@VarA ; 7-bit offset = 0x3456 & 0x007F = 0x56
C28x Addressing Mode

MOVZ MOVU
Note:
(v28 mode, AMODE == 0)
DP,#VarA ; DP(15:0) = 0x3456/64 = 0x00D1 ACC,@VarA ; 6-bit offset = 0x3456 & 0x003F = 0x16
When using C28x syntax, the 128 word data page is indicated by using the double @@ symbol. The 64 word data page is indicated by the single @ symbol. This helps the user and assembler to track which mode is being used.
Registers
B.2.3 Status Register Changes Figure B3. Status Register Comparison Between C2xLP and C28x

15 14 13 12 11 10 1 9 8 7 6 5 4 3 2 1 0 ARP OV OVM INTM DP R/WX R/W0 R/WX R/W1 R/WX Note: R = Read access; W = Write access; value following dash () is value after reset.
C2xLP Status Register ST0
C28x Status Register ST0

8 7 6 5
15
14
13
12
11
10
OVC/OVCU
PM
TC
OVM
SXM
R/W000000
R/W000
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
Note:
C2xLP Status Register ST1

9 8 1 7 1
15
14
13
12
11
10
6 1
5 1
3 1
2 1
ARB
CNF
TC
SXM
XF
PM
R/WX
R/W0
R/WX
R/W1
R/W1
R/W1
R/W00
Note:
C28x Status Register ST1

4 3
IDLESTAT R0
EALLOW R/W0
LOOP R0
SPA
VMAP
PAGE0 R/W0
DBGM
INTM
R/W0
R/W1
R/W1
R/W1
1513 ARP
12
11
10
XF
M0M1MAP
Reserved
OBJMODE
AMODE
R/W000 R/W0 R1 R/W0 R/W0 R/W0 Notes: 1) R = Read access; W = Write access; value following dash () is value after reset; reserved bits are always 0s and are not affected by writes.
B-7
Registers
Zero flag. Z is new on the C28x. It is involved in determining if the results of certain operations are 0. It is also used for conditional operations. Negative flag. N is new on the C28x. It is involved in determining if the results of certain operations are negative. It is also used for conditional operations. Overflow flag. V has changed names from OV on the C2xLP. It flags overflow conditions in the accumulator. Product shift mode. The PM has increased to a 3-bit register with additional capabilities. Below is a comparison of the PM register in the C2xLP and the C28x. Note that the register behaves differently depending on the operational mode of the C28x device. The XSPM instructions correspond to equivalent C2xLP instructions conversion. On the C2xLP, the PM bits corresponded to no shift at reset. On C28x, however, the PM corresponds to a left shift of 1 at reset.
V PM
Table B2. C2xLP Product Mode Shifter

Bits 00 01 10 11 Shift Value no shift shift left 1 shift left 4 shift right 6 Instruction SPM 0 SPM 1 SPM 2 SPM 3
Table B3. C28x Product Mode Shifter

C2xLP Source-Compatible Mode AMODE == 1 OBJMODE = 1 PAGE0 == 0 Bits 000 001 010 011 100 101 110 111 Shift Value shift left 1 no shift shift right 1 shift right 2 shift right 3 shift left 4 shift right 5 shift right 6 Instruction SPM +1 (or SPM 1) SPM 0 (or SPM 0) SPM 1 SPM 2 SPM 3 SPM +4 (or SPM 2) SPM 5 SPM 6 (or SPM 3) Shift Value shift left 1 no shift shift right 1 shift right 2 shift right 3 shift right 4 shift right 5 shift right 6 C28x Mode AMODE == 0 OBJMODE = 1 PAGE0 == 0 Instruction SPM +1 SPM 0 SPM 1 SPM 2 SPM 3 SPM 4 SPM 5 SPM 6
Registers
OVC:
Overflow counter. OVC is new on the C28x. It can be viewed as an extension of the accumulator. For signed operations, the OVC counter is an extension of the overflow mode. For unsigned operations, the OVC counter (OVCU) is an extension of the carry mode. Debug enable mask bit. DBGM is new on the C28x. It is analogous to the INTM bit and works in cooperation with the DBGIER register to globally enable interrupts in real-time emulation. PAGE0 addressing mode configuration bit. The PAGE0 bit is new on the C28x. It is used for compatibility to the C27x and should be left as 0 for users moving from the C2xLP to C28x. Vector map bit. The VMAP bit is new on the C28x. It determines from where in memory interrupt vectors will be fetched. Stack pointer alignment bit. The SPA bit is new on the C28x. It is a flag used to determine if aligning the stack pointer caused an adjustment in the stack pointer address. Loop instruction status bit. The LOOP bit is new on the C28x. It is used in conjunction with the LOOPZ/LOOPNZ instructions. Emulation access enable bit. The EALLOW bit is new on the C28x. It allows access to the emulation register on the C28x. IDLE status bit. The IDLESTAT bit is new on the C28x. It flags an IDLE condition on the C28x, and is mainly used when returning from an interrupt. Address mode bit. The AMODE bit is new on the C28x. This mode bit is used to select between C28x addressing mode (AMODE == 0) and C2xLP addressing mode (AMODE == 1). Object mode bit. The OBJMODE bit is new on the C28x. It is used to select between C27x object mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1). For users moving from C2xLP to C28x, this bit should always be set to 1.
Note: Upon reset of the C28x, this bit is set to 0 and needs to be changed in firmware.
DBGM:
PAGE0
VMAP SPA
LOOP EALLOW IDLESTAT
AMODE
OBJMODE
M0M1MAP
M0 M1 map bit. The M0M1MAP bit is new on the C28x. It is only used for C27x compatibility. For users transitioning from the C2xLP to C28x this bit should always be set to 1. XF pin status bit. The XF pin has the same function as on the C2xLP. Please note that the reset state has changed on the C28x. Auxiliary register pointer. The ARP has the same functionality as on the C2xLP. It should, however, only be used when transitioning code to the C28x. The C28x has enhanced addressing modes which eliminate the need to keep track of the ARP.
XF ARP
B-9
Register Reset Conditions
The functionality of the remaining bits is the same on C28x as they are on C2xLP. It should be noted that although the functionality did not change, the bit position in the registers did. These bits are: - Sign extension mode (SXM) - Overflow mode (OVM) - Test/control flag (TC) - Carry bit (C) - Interrupt global mask bit (INTM)
B.2.4 Register Reset Conditions

The reset conditions of internal registers have changed between the C2xLP and C28x as shown in Table B4. Most C28x registers are cleared on a reset. Differences in Table B5 are highlighted in bold.
Table B4. Reset Conditions of Internal Registers

C2xLP Register T P ACC AR0AR7 PC ST0 ST1 DP IMR IFR GREG X = Uninitiated C2xLP Reset X X X X 0x0000 See Table B5 See Table B5 X 0x00 0x0000 0x0000 C28x Register XT P ACC XAR0XAR7 PC ST0 ST1 DP SP IER DBGIER IFR RPC C28x Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x3FFFC0 0x0000 0x080B 0x0000 0x0400 0x0000 0x0000 0x0000 0x000000
Register Reset Conditions
Table B5. Status Register Bits

Reg ST0 C2xLP Bit Name DP INTM OVM OV ARP C2xLP Reset Value XXXXXXXXX 1 X 0 XXX C28x Bit Name SXM OVM TC C Z N V PM ST1 PM XF C SXM TC CNF ARB 00 (no shift) 1 1 1 X 0 XXX INTM DBGM PAGE0 VMAP SPA LOOP EALLOW IDLESTAT AMODE OBJMODE CNF not implemented M0M1MAP XF ARP C28x Reset Value 0 0 0 0 0 0 0 000 (left shift 1) 1 1 0 1 0 0 0 0 0 0 0
1
0 000
B-11
Memory Map
B.3 Memory Map

The major changes between the C2xLP and C28x memory maps are outlined in this section. There are several differences between the C2xLP and C28x memory maps. These improvements are due to the expanded architecture of the C28x. The C28x CPU memory map ranges from 4G to 4M in data and program memory, respectively. However, C28x CPU-based devices may not use the entire memory range. See the device data sheet for the specific memory range applicable to that device. Vectors. On the C2xLP, only one vector table is present at address 0x0000. These vectors were generally branch instructions to different interrupt service routines. On the C28x, the vector table can be placed in two different locations depending on the state of the VMAP input pin. On devices that do not pin out the VMAP signal, it is tied internal to the device. Generally, vectors will be located in non-volatile memory at 0x3FFFC00x3FFFFF. To take advantage of relocatable vectors or fetching vectors from fast internal memory space, place the vectors at address 0x0000000x00003F. Often the C28x CPU interrupt vectors are expanded using external hardware logic. In such cases, see the related documents for the expanded vector map. Memory space. On the C2xLP, the memory space for program, data, and I/O space is each 64K words. On the C28x, the program memory space is 4M words (22 address signals). The data memory space is 4G words (32 address signals). The global space (32K) and I/O space (64K) is generally used for C2xLP compatibility. Program space. On the C2xLP CPU, program space could be mapped anywhere from (0x00xFFFF). With the extended address reach of the C28x (22 bits), the compatible region in program space for the C2xLP is 0x3F00000x3FFFF. Thus, any program memory on the C2xLP must be remapped to this upper region on the C28x. When the processor accesses program memory, the upper bits (bits 1622) will be forced to all 1s when C2xLPcompatible instructions are used (See Appendix E).
Memory Map
Figure B4. Memory Map Comparison (See Note A)
Block Start Address 0x0000-0000 0x0000-0040 0x0000-0060 0x0000-0200 Low 6K (C2xLP Data, I/O Space) 0x0000-0300 0x0000-0400
C28x memory map for C2xLP Data Space Program Space
C2xLP memory map Data Space - 64K Memory Registers I/O space 64K
VECTORS (32 x 32) (enabled if VMAP = 0)
M0 SARAM (1K x 16)
B2 Block B1 Block B0 Block
M1 SARAM (1K x 16) Emulation registers (2K x 16) Reserved 0x0000-2000
Reserved
0x0000-0800
On-chip 4K SARAM Don = 1
0x0000-8000 Global Space 032K 0x0000-FFFF 0x0010000 Reserved for only C28x addressing 0x03EFFFF High 64K (C2xLP Program Space) 0x03F0000 Vectors 32 x 16
Program Space - 64K
4K SARAM Pon = 1
0x03FFFC0 0x03FFFFF
Vectors (32 x 32) (enabled if VMAP = 1)
B0 Block CNF = 1
Note A: Memory map is not to scale.
B-13
Memory Map
Data memory. The C2xLP has three internal memory regions (B0, B1, B2) totaling 544 words. The C28x has two internal memory regions (M0,M1) totaling 1K words each. Note that for strict C2xLP compatibility, the memory regions are placed at the same addresses as noted in Table B6.
Table B6. B0 Memory Map

C28x in C2xLP-Compatible Mode CNF Not Available B0 range mapped in M0 block 200 2FFh. (No mirroring of the block) CNF = 0 B0 in Data space 100 1FFh (mirrored locations) 200 2FFh CNF Not Available B0 range cannot be enabled in C2xLP-equivalent program memory CNF = 1 B0 in program space FE00 FEFFh (mirrored locations) FF00 FFFFh C2xLP
I/O space. I/O space has remained on the C28x for compatibility reasons, and can only be accessed using IN and OUT/UOUT instructions. Not all C28x devices will support I/O space. See the data sheet of your particular device for details. Global space. Global space is not supported on all C28x devices. See the data sheet specific to your device for details. Reserved memory. Reserved memory regions have changed on the C28x. No user-defined memory or peripherals are allowed at addresses 0x8000x9FF on the C28x. While using C2xLP-compatible mode, these addresses are reserved. It is recommended that C2xLP memory or peripherals be relocated to avoid memory conflicts. Stack space. The C28x has a dedicated software stack pointer. This pointer is initialized to address 0x0400 (the beginning of block M1) at reset, and it grows upward in address. It is up to the user to move this stack pointer if needed in firmware.
Appendix AppendixC A
C2xLP Migration Guidelines

The C28x DSP is source-code compatible with C2xLP DSP based devices. The C28x DSP assembler accepts all C2xLP mnemonics with the exception of a few instructions. This chapter provides guidelines for C2xLP code migration to a C28x device. C2xLP refers to the CPU used in all TMS320C24x, TMS320C24xx, and TMS320C20x DSP devices.
Topic
C.1 C.2 C.3 C.4 C.5
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Recommended Migration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 Mixing C2xLP and C28x Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 Reference Tables for Code Migration Topics . . . . . . . . . . . . . . . . . . . C-10
C-1
Introduction
C.1 Introduction
This chapter provides guidelines that are intended for conversion from C2xLP assembly source to C28x object code. The conversion steps highlight the architectural changes between C2xLP and C28x operating modes. Future releases of documents will contain code conversion examples and software library modules facilitating the conversion from C2xLP mixed C and assembly source to C28x object code. This chapter will be best understood if the reader has prior knowledge of Appendix C and Appendix E, as they explain the architectural and instructional enhancements between the C2xLP and C28x DSPs.
Recommended Migration Flow
C.2 Recommended Migration Flow

Use the following steps (shown in Figure C1) to migrate code: 1) Install the latest development tools for the C28x DSP (e.g. Code Composer Studiot version 2.x or higher) 2) Build the project with following C28x assembler options:
m20 g mw ; ; ; ; enable C2xLP instructions enable source level debug to view the C2xLP instructions enable additional assembly checks
Code Composer Studio 2.x will assemble all C2xLP instructions and map all the compatible instructions to their equivalent C28x instructions and mnemonics. Code Composer Studio 2.x disassembly will display the instructions in the memory as C28x mnemonics only. If the source is built with g option, the relevant C2xLP source file will be also displayed and will facilitate C2xLP instruction readability during debug. 3) Memory map: Define your C28x device memory map with C2xLP compatible memory sections. Build a linker command file (*.cmd). See Table C8. Select a C2xLP assembly source code *.asm for migration to C28x architecture. 4) Boot Code: Add the C2xLP mode conversion code segment shown in section C.4.1 as the first set of instructions after reset. After reset, the C28x powers up in C27x objectcompatible mode. Adding these few lines of initialization code will place the device in the proper operating mode for executing reassembled C2xLP code.
Note: The C27x object-compatible mode is for use only for migration from the C27x CPU. It is a reserved operating mode for all C28x and C2xLP applications.
5) This step will facilitate faster code conversion. In the C2xLP source file modify the interrupt section with suggestions from the reference table in section D.5. In particular, modify the following types of code: a) IMR and IFR See the example code in section C.4.2. b) Context Save/Restore See the example code in section C.4.3 c) Comment all the known incompatible instructions or map with equivalent instructions. See Table D2 in Appendix D.
C2xLP Migration Guidelines C-3
Figure C1. Flow Chart of Recommended Migration Steps

Start Step 1 Migrate to Code Composer Studio for the C28x DSP Step 2 Configure your project with m20, mw, and g assembler options to enable acceptance of C2xLP mnemonics. Also build a linker command file *.cmd for your C28x device. Step 3 Select the C2xLP assembler source code for C28x migration *.asm Step 4 Add the initialization code segment to enable C2xLP compatible mode in the beginning of the code. Step 5 Comment or fix incompatible instructions in C2xLP source, if any Step 6 Invoke the C28x Assembler and assemble the modified C2xLP source code to get a C28x *.obj file See the tables in Section C.5 for corrections to source code
Assembly errors ? No
Yes
Step 7 Invoke the C28x Linker with assembled .obj files
Fix Linker errors. See the tables in Section C.5 if required.
Linker errors ?
Yes
No Step 8 Linker outputs C28x COFF file *.out Migrated code ready for Debug End Legend: * represents user filename
6) Link the assembled code with the linker command file generated in Step 2. Relink if necessary to avoid any linker related errors. 7) Assemble or reassemble using the C28x assembler until the assembly is successful with no errors. The tables in section C.5 will help to resolve most of the errors during the assembly process. This will prepare a *.obj file, ready for C28x Linker processing. 8) The Linker output COFF file, *.out, will be the migrated code and should be ready for Debug and integration.
C-5
Mixing C2xLP and C28x Assembly
C.3 Mixing C2xLP and C28x Assembly

At this point your original C2xLP code will be running on the C28x device. To facilitate further migration to C28x code, there are special assembler directives that will facilitate mixing of C2xLP code and C28x code segments. The .c28_amode and .lp_amode directives tell the assembler to override the assembler mode.
.c28_amode
The .c28_amode directive tells the assembler to operate in the C28x object mode (v28). The .lp_amode directive tells the assembler to operate in C28x object accept C2xLP syntax mode (m20). These directives can be repeated throughout a source file. For example, if a file is assembled with the m20 option, the assembler begins the assembly in the C28x object accept C2xLP syntax mode. When it encounters the .c28_amode directive, it changes the mode to C28x object mode and remains in that mode until it encounters an .lp_amode directive or the end of file.
.lp_amode
Example
In this example, C28x code is inserted in the existing C2xLP code.
; C2xLP source code .lp_amode #VarA LDP LACL VarA LAR AR0 *+, AR2 SACL *+ . . CALL FuncA . . ; The C2xLP code in function FuncA is replaced with C28x Code ; using C28x addressing (AMODE = 0) .c28_amode ; Override the FuncA: C28ADDR ; MOV DP, #VarB MOV AL, @VarB MOVL XAR0, *XAR0++ MOV *XAR2++, AL .lp_amode ; LPADDR ; LRET assembler mode to C28x syntax Set AMODE to 0 C28x addressing
Change back the assembler mode to C2xLP. Set AMODE to 1 to resume C2xLP addressing.
Code Examples
C.4 Code Examples

C.4.1 Boot Code for C28x operating mode initalization
Note: The following code fragment must be placed in your code just after reset. This code will place the device in the proper operating mode to execute C2xLP converted code:
Code SETC OBJMODE CLRC PAGE0 SETC AMODE SETC SXM SETC C SPM 0 Explanation ;C28OBJ = 1 enable 28x object mode ;PAGE0 = 0 not relevant for 28x mode, ;cleared to zero ;AMODE = 1 enable C2xLP compatible ;addressing mode ;SXM = 1 for C2xLP at reset, SXM = 0 ;for 28x at reset ;Carry bit =1 for C2xLP at reset, ;Carry bit = 0 for 28x at reset ;Set product shift mode zero, that is PM bits = 001 compatible to ;C2xLP PM reset;mode
C.4.2 IER/IFR Code Table C1. Code to Save Contents Of IMR (IER) And Disabling Lower Priority Interrupts At Beginning Of ISR
C2xLP INTx: . MAR LDP LACL SACL AND SACL . . C28x INTx: *,AR1 #0 IMR *+ #~INT_MASK IMR
. AND .
IER,#~INT_MASK
Note: C28x saves IER as part of automatic context save operation and disables the current interrupt automatically to prevent recursive interrupts.
Table C2. Code to Disable an Interrupt

C2xLP SETC INTM LDP LACL AND SACL CLRC C28x AND #0 IMR #~INTx IMR INTM
IER,#~INTx
;operation is atomic and ;will not be interrupted.
C-7
Code Examples
Table C3. Code to Enable an Interrupt

C2xLP SETC INTM LDP LACL OR SACL CLRC INTM C28x #0 IMR #INTx IMR OR IER,#INTx
;operation is atomic and ;will not be interrupted.
Table C4. Code to Clear the IFR Register

C2xLP ;write 1 to clear SETC INTM LDP #0 SPLK #0FFFFh,IFR CLRC INTM C28x ;write 0 to clear AND IFR,#~INTx ;operation is atomic and ;will not be interrupted
C.4.3 Context Save/Restore

The C28x automatically saves a number of registers on each interrupt. To perform a full context save, some additional code must be added. Table C5 shows a typical full context save and restore for both processors.
Code Examples
Table C5. Full Context Save/Restore Comparison

C2xLP Full Context Save/Restore C28x Full Context Save/Restore ;C28x automatically saves the ;following registers: ;T,ST0,AH,AL,PH,PL,AR1,AR0,DP,ST1, ;DBGSTAT,IER,PC INTx_ISR: ;interrupt context save PUSH AR1H:AR0H ; 32bit PUSH XAR2 ; 32bit PUSH XAR3 ; 32bit PUSH XAR4 ; 32bit PUSH XAR5 ; 32bit PUSH XAR6 ; 32bit PUSH XAR7 ; 32bit PUSH XT ; 32bit . . ;interrupt code goes here . . ;interrupt context restore POP XT POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H IRET
INTx_ISR: ; context save MAR *, AR1 MAR *+ SST #1,*+ SST #0,*+ SACH *+ SACL *+ SPH *+ SPL *+ MPY #1 SPL *+ SAR AR0, *+ SAR AR2, *+ SAR AR3, *+ SAR AR4, *+ SAR AR5, *+ SAR AR6, *+ SAR AR7, *+ . ;interrupt code goes here . . ; context restore MAR *, AR1 MAR * LAR AR7, * LAR AR6, * LAR AR5, * LAR AR4, * LAR AR3, * LAR AR2, * LAR AR0, * SETC INTM MAR * SPM 0 LT *+ MPY #1 LT * MAR * LPH * LACL * ADD *, 16 LST #0, * LST #1, * CLRC INTM RET
C-9
Reference Tables for C2xLP Code Migration Topics
C.5 Reference Tables for C2xLP Code Migration Topics

Table C6 through Table C10 explain the major differences between the C2xLP and C28x architectures and in their respective code generation process. These tables are organized to highlight the differences in interrupts, CPU registers, memory maps, instructions, registers, and syntax. While migrating the C2xLP code, check the tables for these key differences to make the necessary changes to the source to avoid assembler or linker errors.
Table C6. C2xLP and C28x Differences in Interrupts

Migration topic 1 Interrupt flag register C2xLP IFR Memory mapped register Write 1 to clear bits set in IFR 2 3 Interrupt enable register TRAP instruction IMR Memory mapped register Only one TRAP vector TRAP Affects: INTM bit is not affected 4 INTR instruction syntax INTR0 .. INTR31 Affects: IFR not cleared IMR not affected INTM bit =1 5 6 NMI Instruction CLRC INTM instruction NMI CLRC INTM instruction blocks all interrupts until the next instruction is executed. CLRC INTM next_instn ;interrupts ;blocked ;until this ;executed 7 Interrupt enable and return from interrupt service CLRC INTM RET IRET C28x IFR is a CPU register Write 0 to clear bits set in IFR Renamed as IER and is a CPU register multiple,32 TRAP vectors TRAP 0, .. TRAP31 Affects: INTM bit is set to 1 INTR INT0 . INTR INT31 Affects: IFR cleared IER affected INTM bit =1 TRAP NMI Interrupts enabled after the instruction CLRC INTM
Table C6. C2xLP and C28x Differences in Interrupts (Continued)

Migration topic 8 Interrupt enable and return from function call Interrupts Vector CLRC INTM next_instn Uses Branch statements at the vector address. Ex: B Start ;assembly ;code ; opcode in memory 0x7980 ;branch ;instruction 0x0040 ;branch ;address No automatic context save See section D.3 for a full context save/restore example C2xLP next_instn CLRC INTM 32bit absolute addresses. ; code in vector location 0x0040 (low address) 0x003F (high address) C28x
10
Context save
Automatic context save of CPU registers T, ST0, AH, AL, PH, PL, AR1, AR0, DP, ST1, DBGSTAT, IER, PC See Table C5 for a full context save/ restore example
Table C7. C2xLP and C28x Differences in Status Registers

Migration topic 1 Saving ST0/ST1 registers C2xLP Save: SST #0,mem ;store ST0 SST #1,mem ;store ST1 Restore: LST #0,mem ;load ST0 LST #1,mem ;load ST1 C28x Save: PUSH ST ;store ST0 to stack PUSH ST ;store ST1 to stack Restore: POP ST1 ;load ST1 ;from stack POP ST0 ;load ST0 ;from stack ST0/ST1 bits are rearranged compared to C2xLP registers.
ST0/ST1 bit differences
ST0/ST1 bits have CPU registers and status bits
C-11
Table C7. C2xLP and C28x Differences in Status Registers (Continued)

3 INTM bit in ST0 Cannot be saved if ST0 register is saved DP save/restored along with ST0. SST #0,mem ;store ST0 LST #0,mem ;load ST0 Saved along with ST0 register
Data page pointer DP save
DP is a register, hence explicit store/ restore is required. PUSH DP ;store DP ;to stack PUSH DP:ST1 ; 32bit ; save POP DP ;load DP from ;stack POP DP:ST1 ; 32bit ; restore
Table C8. C2xLp and C28x Differences in Memory Maps

Migration topic 1 Program memory C2xLP 16bit address Size : 64kx16 Range :0x00000xFFFFh 22 bit address Size : 64kx16 mapped to Range : 0x3F 0000h 0x3F FFFFh 2 Data memory Size : 64kx16 Range :0x00000xFFFFh Size : 64kx16 mapped to Range : 0x00 0000h 0x00 FFFFh C28x
B2 Block
Size: 32 words Range: 0x00600x007F
Located in M0 Block 1Kx16 Size: 1K words Range: 0x00 0060 0x00 07Fh
B1 Block
Size: 256 words Range: 0x01000x01FF (mirrored) : 0x02000x02FF
Located in M0 Block 1Kx16 Not Mirrored Range: 0x00 0200 0x00 02FFh Located in M0 Block 1Kx16 Not Mirrored Range: 0x00 0300 0x00 03FFh
B0 Block
Mirrored locations Size: 256 words Range: 0x03000x03FF : 0x04000x04FF
Table C8. C2xLp and C28x Differences in Memory Maps (Continued)

Migration topic C2xLP CNF bit maps B0 in data and program memory CNF =0 B0 in data memory Range: 0x03000x03FF : 0x04000x04FF CNF =1 B0 in program memory Range: 0xFE000xFEFF : 0xFF000xFFFF Not applicable C28x
CNF bit mapping of B0 Block
10
Vector table range
Size: 32x16 words Range: 0x00000x003F
Size 32x32 words 0x3F FFC0 0x3F FFFF at reset In C28x based DSP devices may use additional expanded vector table (e.g., PIE)
11
Internal SARAM mapping in data memory
Mapped as internal memory map
Reserved for emulation registers Range : 0x0800 0x1000h
I/O space
Range : 0x0000 0xFFFFh
Range : 0x0x00 000 0x00 FFFFh I/O Space may or may not be implemented on a particular device. See the device datasheet for details.
Global space
Range : 0x8000 0xFFFFh
Implemented via the XINTF Global Space may or may not be implemented on a specific C28x device. See the device datasheet for details.
Table C9. C2xLP and C28x Differences in Instructions and Registers

Migration topic C2xLP Can take more than one condition in these instructions Conditional flags update on Accumulator operation only Many instructions are repeatable C28x The C28x assembler will automatically break the instructions into multiple instructions. Conditional flags update on Accumulator, register and memory operations Same instructions are repeatable. For additional repeatable instructions see Table D3.
Conditional Instructions Branches, Calls, Returns
2 3
When are CPU Flags updated? Repeat instructions
C-13
Table C9. C2xLP and C28x Differences in Instructions and Registers (Continued)
Migration topic C2xLP Memory mapped register C28x Memory mapped register in XINTF Global Space may or may not be implemented on a particular device. See the device data sheet for details. 5 ARx registers ARx registers are 16bit only LAR AR1, #0FFFFh ADRK #1 Result: AR1 = 0x0000h 6 2s complement subtraction to ARx LAR AR1, #0FFFFh ADRK #0FE Result: AR1 = 0xFFFDh 7 I/O instructions Supports IN, OUT instructions XARn registers are 32 bits. Some instructions access only the lower 16 bits known as ARn MOV XAR1, #0FFFFh ADD XAR1,#1 Result: XAR1 = 0x10000h MOV XAR1, #0FFFFh ADD XAR1,#0FE Result: XAR1 = 0x1FFFDh Supports IN, OUT,UOUT I/O Space may or may not be implemented on a particular device. See the device datasheet for details. 8 Stack Uses 8deep Hardware stack C2xLP Compiler uses AR1 as Stack Pointer 9 Program counter 16 bits in size Uses software stack pointer register (SP) Compiler will use SP register, as stack pointer 22 bits in size The C28x assembler will use special C2xLP compatible instructions that force the upper program address lines to 0x3F thus creating a 16bit C2xLP compatible PC. B or XB 5000h 0x3F5000 ;
GREG register
B 5000h ; Branch to 5000 ; address
Table C10. Code Generation Tools and Syntax Differences

Migration topic 1 Mnemonic C2xLP Source or destination not always specified. LACL, source SACL, destination 2 Direct addressing syntax @ symbol LACL dma MOV ACC, @@dma ; C2xLP mode MOV ACC, @dma ; 28x mode @@ means 128 word data page @ means 3 Indirect address pointer buffer, ARB In indirect addressing, Auxiliary register will be pointed by ARP register in ST0. ARB is ARP pointer buffer in ST1. MAR *,AR2 ; ARP =AR2 LACL * 4 New Address pointers syntax *(0 5 Repeat instructions syntax change || No additional syntax RPT #5 NOP ST0, ST1, IFR, IMR, GREG Uses || syntax with repeat instructions RPT #5 || NOP ST0, ST1, AH, AL, PH, PL,T, TL, XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, XAR7, DP, ST1, DBGSTAT, IER, PC, RPC 7 Increment/Decrement syntax change MAR *,AR2 LACL *+ . LACL * 8 Shift syntax change LACL dma, 4 MOV ACC,dma <<4 MOV ACC, *AR2++ .. MOV ACC, *AR2 BLDD #4545h,RegA MOV @REGA, *(0:0x4545) 64 word data page C28x Instructions are always of the form mnemonic destination, source MOV destination,source
No ARB equivalent in 28x. Selected ARx is referenced in the instruction itself. MOV ACC,*AR2
Reserved register names Application code should not use these reserved words
C-15
Table C10. Code Generation Tools and Syntax Differences (Continued)

Migration topic 9 Number radix usage x .set 09 C2xLP ;Assembler ;accepts ;this as ;decimal 9 x .set 9 Avoid leading zeros, else the assembler will be use this as octal number. C28x
10
Order of precedence in expressions Syntax change Tools Directives
Expressions in assembly statements do not require parenthesis. x .set A<<B = C>>D .mmregs ; reserved register use .port .globl
Expressions in assembly statements do require parenthesis. x .set (A<<B = C>>D) not applicable not applicable .global Useful in coding style All C2xLP Macros are not directly used Convert them individually to 28x mode.
11
12
Macros
Useful in coding style
13
Assembler options
v2xx
m20, v28
Appendix AppendixD A
C2xLP Instruction Set Compatibility

This appendix highlights the differences in syntax between the C2xLP and the C28x instructions, and details which C2xLP compatible instructions are repeatable on the C28x. The C28x assembler accepts both C28x and C2xLP assembly source syntax. This enables you to quickly port C2xLP code with minimal effort. Additionally, all compatible C2xLP instructions have an equivalent C28x style syntax. The C28x disassembler will show the C28x equivalent syntax.
Topic
D.1 D.2 D.3
Page
Condition Tests on Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 C2xLP vs. C28x Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Repeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
D-1
Condition Tests on Flags
D.1 Condition Tests on Flags

On the C28x, all EQ/NEQ/GT/LT/LEQ conditional tests are performed on the state of the Z and N flags. On the C2xLP, the same condition tests are performed on the contents of the ACC register.
Table D1. C28x and C2xLP Flags

Designation NEQ EQ GT GEQ LT LEQ HI HIS, C LO, NC LOS NOV OV NTC TC NBIO UNC C28x Modes != 0 == 0 > 0 >= 0 < 0 <= 0 higher higher or same, carry set lower, carry clear lower or same no overflow overflow TC == 0 TC == 1 test BIO input == 0 unconditional C2xLP Equivalent ACC != 0 ACC == 0 ACC > 0 ACC >= 0 ACC < 0 ACC <= 0 C == 1 C == 0 OV == 0 OV == 1 TC == 0 TC == 1 BIO == 0 UNC
On the C28x, the Z and N flags are set on all ACC operations. That includes ACC loads. Therefore, the Z and N flags reflect the current state of the ACC immediately after an operation on the ACC.
D.2 C2xLP vs. C28x Mnemonics

Table D2 lists the C2xLP instructions with the C28x equivalent syntax. The C28x assembler will accept either the C2xLP syntax or the equivalent C28x syntax. The disassembler will decode and display the C28x syntax. The C2xLP cycle count numbers shown are for zero wait-state internal memory, where n equals the number of repetitions (i.e., if an instruction is repeated, using the RPT instruction for repeatable instructions, n times it is executed n+1 times).
Table D2. C2xLP Instructions and C28x Equivalent Instructions

C2xLP Instruc- Mnemonic tion
ABS ADD ADD ADD ADD ADD ADDC ADDS ADDT ADRK AND AND AND APAC B B B pma pma,*,ARn pma,*ind loc16[,0] loc16,1..15 loc16,16 #8bit #16bit[,0..15] loc16 loc16 loc16 #8bit loc16 #16bit,16 #16bit[,0..15]
C28x Cycles Size

n+1 n+1 n+1 n+1 1 2 n+1 n+1 n+1 1 n+1 2 2 n+1 4 4 4 16 16 16 16 16 32 16 16 16 16 16 32 32 16 32 32 32
Instruction
ABS ADD ADD ADD ADDB ADD ADDCU ADDU ADD ADRK AND AND AND ADDL XB XB NOP XB NOP XB
Mnemonic
ACC ACC,loc16 {<<0} ACC,loc16 << 1..15 ACC,loc16 << 16 ACC,#8bit ACC,#16bit {<<0..15} ACC,loc16 ACC,loc16 ACC,loc16 << T #8bit ACC,loc16 ACC,#16bit<<16 ACC,loc16 {<< 0..15} ACC,P<<PM pma,UNC pma,*,ARPn *ind pma, UNC *ind pma,*,ARPn
Cycles Size
1 n+1 n+1 n+1 1 1 1 n+1 n+1 1 n+1 1 1 n+1 7 4 8 16 16 32 16 16 32 16 16 32 16 16 32 32 16 32 32 32
pma,*ind,ARn
32
48
True/False
D-3
Table D2. C2xLP Instructions and C28x Equivalent Instructions (Continued)

C2xLP Instruction
BACC BANZ BANZ BCND pma,*ind[,ARn] pma,*BR0+/*BR0[,ARn] pma[,COND]
C28x Cycles Size

4 4/2 4/2 4/2 16 32 32 32 XB or SB SB SB . XB skip: TBIT TBIT MOV MOV XPREAD XCALL XCALL XCALL NOP XCALL NOP XCALL XCALL SB SB pma,CONDn . XCALL skip:
Mnemonic
Instruction
XB XBANZ
Mnemonic
*AL pma,*ind[,ARAPn] Not applicable pma,COND #8bitOff,COND skip,opposite of COND1 skip,opposite of COND2 . pma,CONDn
Cycles Size
7 4/2 16 32
7/4
32 16
BCND
pma,COND1,COND2,.., CONDn
4/2
32
7+
48+
BIT BITT BLDD BLDD BLPD CALA CALL CALL CALL
loc16,15bit loc16 #src_addr,loc16 loc16,#dest_addr #pma,loc16
n+1 n+1 n+3 n+3 n+3 4
16 16 32 32 32 16 32 32 32
loc16,#bit loc16,T loc16,*(0:src_addr) *(0:dest_addr),loc16 loc16,*(pma) *AL pma,UNC pma,*,ARPn *ind pma,UNC *ind pma,*,ARPn pma,COND skip,opposite of COND1 skip,opposite of COND2
1 1 n+2 n+2 n+2 7 7 4 8
16 32 32 32 32 16 32 32 48
pma pma,*,ARn pma,*ind
4 4 4
CALL
pma,*ind,ARn
32
48
CC CC
pma,COND pma,COND1,..,CONDn
4/2 4/2
32 32
7/4 7+
32 48+
CLRC
INTM
n+1
16
See Table C6.
True/False

C2xLP Instruction
CLRC CLRC CMPL CMPR DMOV IDLE IN INTR LACC loc16,PA K loc16[,0] 0/1/2/3 loc16
C28x Cycles Size

n+1 n+1 n+1 n+1 n+1 1 2(n+1) 4 n+1 16 16 16 16 16 16 32 16 16 MOV NOT CMPR DMOV IDLE IN loc16,*(PA) Not applicable ACC,loc16 [<< 0] 1 16
Mnemonic
XF/OVM/SXM/TC/C CNF
Instruction
CLRC
Mnemonic
XF/OVM/SXM/TC/C Not applicable ACC 0/1/2/3 loc16
Cycles Size
2,1 16
1 1 n+1 5 n+2
16 16 16 16 32
LACC LACC LACC
loc16,1..15 loc16,16 #16bit,0..15
n+1 n+1 2
16 16 32
MOV MOV MOV
ACC,loc16 << 1..15 ACC,loc16 << 16 ACC,#16bit << 0..15
1 1 1
32 16 32
LACL LACL LACT LAR LAR LAR LDP LDP LPH LST LT LTA
loc16 #8bit loc16 ARn,loc16 ARn,#8bit ARn,#16bit loc16 #9bit loc16 #0/1,loc16 loc16 loc16
n+1 1 n+1 2(n+1) 2 2 2(n+1) 2 n+l 2(n+1) n+l n+l
16 16 16 16 16 32 16 16 16 16 16 16
MOVU MOVB MOV MOVZ MOVB MOVL
ACC,loc16 ACC,#8bit ACC,loc16 << T ARn,loc16 XARn,#8bit XARn,#22bit Not applicable
1 1 1 1 1 1
16 16 32 16 16 32
MOVZ MOV
DP,#10bit >> 1 PH,loc16 See Table C7
1 1
16 16
MOV MOVA
T,loc16 T,loc16
1 n+1
16 16
True/False
D-5

C2xLP Instruction
LTD LTP LTS MAC MACD MAR MPY MPY MPYA MPYS MPYU NEG NMI NOP NORM NORM OR OR OR OUT PAC POP POPD PSHD PUSH
C28x Cycles Size

n+l n+l n+l n+3 n+3 n+l n+l 1 n+l n+l n+l n+l 4 n+l 16 16 16 32 32 16 16 16 16 16 16 16 16 16 16 16 16 32 32 32 16 16 16 16 16 OR OR OR OUT MOV MOVU POP PUSH MOV NOP NORM ACC,*/*++/*/*0++/*0 Not applicable ACC,loc16 ACC,#16bit<<16 ACC,#16bit {<< 0..15} *(PA),loc16 ACC,P<<PM ACC,*SP loc16 loc16 *SP++,AL n+1 1 1 4 1 1 2 2 n+1 16 32 32 32 16 16 16 16 16
Mnemonic
loc16 loc16 loc16 pma,loc16 pma,loc16 *ind[,ARn] loc16 #13bit loc16 loc16 loc16
Instruction
MOVAD MOVP MOVS XMAC XMACD NOP MPY MPY MPYA MPYS MPYU NEG
Mnemonic
T,loc16 T,loc16 T,loc16 P,loc16,*(pma) P,loc16,*(pma) *ind[,ARPn] P,T,loc16 P,@T,#16bit P,T,loc16 P,T,loc16 P,T,loc16 ACC Not applicable
Cycles Size
1 1 n+1 n+2 n+2 n+1 1 1 n+1 n+1 1 1 16 16 16 32 32 16 16 32 16 16 16 16
n+1 n+4
16 16
*/*+/*/*0+/*0 *BR0+/*BR0 loc16 #16bit,16 #16bit[,0..15] loc16,PA
n+l n+l n+l 2 2 3(n+1) n+l n+l
loc16 loc16
n+l n+l n+l
True/False

C2xLP Instruction
RET RETC RETC COND COND1,COND2,..,CONDn
C28x Cycles Size

4 4/2 4/2 16 16
Mnemonic
Instruction
XRETC XRETC SB SB . XRETC $10: ROL ROR RPT RPT MOV MOVH MOVH MOV MOV MOV MOV SBRK SETC SETC
Mnemonic
UNC COND $10,opposite of COND1 $10,opposite of COND2 . CONDn
Cycles Size
7 7/4 7+ 16 16 48+
ROL ROR RPT RPT SACH SACH SACH SACL SACL SACL SAR SBRK SETC SETC SETC SFL SFR SPAC SPH SPL
n+l n+l loc16 #8bit loc16[,0] loc16,1 loc16,2..7 loc16[,0] loc16,1 loc16,2..7 ARn,loc16 #8bit INTM XF/OVM/SXM/TC/C CNF 1 1 n+l n+l n+l n+l n+l n+l n+l 1 n+l n+l n+l n+l n+l n+l loc16 loc16 n+l n+l
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
ACC ACC loc16 #8bit loc16,AH loc16,ACC << 1 loc16,ACC << 2..7 loc16,AL loc16,ACC << 1 loc16,ACC << 2..7 loc16,ARn #8bit INTM XF/OVM/SXM/TC/C Not applicable
n+1 n+1 1 1 n+1 n+1 n+1 n+1 n+1 n+1 1 1 2 2,1
16 16 16 16 16 16 32 16 16 32 16 16 16 16
LSL SFR SUB MOVH MOV
ACC,1 ACC,1 ACC,P<<PM loc16,P loc16,P
n+1 n+1 n+1 n+1 n+1
16 16 16 16 16
True/False
D-7

C2xLP Instruction
SPLK SPLK SPM SPM SPM SPM SQRA SQRS SST SUB SUB SUB SUB SUB SUBB SUBC SUBS SUBT TBLR TBLW TRAP XOR XOR XOR ZALR
C28x Cycles Size

2 2 1 1 1 1 n+l n+l n+l n+l n+l n+l 1 2 n+l n+l n+l n+l n+3 n+3 4 32 32 16 16 16 16 16 16 16 16 16 16 16 32 16 16 16 16 16 16 16 16 32 32 16 XOR XOR XOR ZALR SUB SUB SUB SUBB SUB SUBU SUBCU SUBU SUB XPREAD XPWRITE
Mnemonic
#0x0000,loc16 #16bit,loc16 0 1 2 3 loc16 loc16 #0/1,loc16 loc16[,0] loc16,1..15 loc16,16 #8bit #16bit[,0..15] loc16 loc16 loc16 loc16 loc16 loc16
Instruction
MOV MOV SPM SPM SPM SPM SQRA SQRS
Mnemonic
loc16,#0 loc16,#16bit 0 1 (or 2 (or +1) +4)
Cycles Size
n+1 n+1 1 1 1 1 n+1 n+1 16 32 16 16 16 16 32 32
3 (or 6) loc16 loc16 Not applicable ACC,loc16 {<< 0} ACC,loc16 << 1..15 ACC,loc16 << 16 ACC,#8bit ACC,#16bit {<< 0..15} ACC,loc16 ACC,loc16 ACC,loc16 ACC,loc16 << T loc16,*AL *AL,loc16 Not applicable ACC,loc16 ACC,#16bit<<16 ACC,#16bit [<< 0..15] ACC,loc16
n+1 n+1 n+1 1 1 1 n+1 n+1 n+1 n+4 n+4
16 32 16 16 32 16 16 16 32 32 32
loc16 #16bit,16 #16bit[,0..15] loc16
n+l 2 2 n+l
n+1 1 1 1
16 32 32 32
True/False
Repeatable Instructions
D.3 Repeatable Instructions

Not all of the repeatable instructions on the C2xLP are repeatable on the C28x. The ones that were not made repeatable do not make sense to repeat from a functionality standpoint. Also, some instructions that were not repeatable on the C2xLP are repeatable on the C28x. Table D3 shows which C2xLP operations are repeatable, and which ones are repeatable on the C28x.
Table D3. Repeatable Instructions for the C2xLP and C28x

C2xLP Instruction ABS ADD mem,shift1 ADDC mem ADDS mem ADDT mem C2xLP Repeatable X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X C28x Repeatable
AND
APAC
mem
BIT mem,bit_code BITT mem BLDD #addr,mem BLDD mem,#addr BLPD #pma,mem CLRC CNF/XF/INTM/OVM/SXM/TC/C CMPL CMPR constant DMOV mem IN mem,PA INTR K LACC mem[,shift1] LACL mem
D-9
Table D3. Repeatable Instructions for the C2xLP and C28x (Continued)
C2xLP Instruction LACT mem LAR AR,mem LDP mem LPH mem LST #n,mem LT mem LTA mem LTD mem LTP mem LTS mem MAC pma,mem MACD pma,mem MAR {ind}[,nextARP] MPY mem MPY #k MPYA mem MPYS mem MPYU mem NEG NOP NORM {ind} OR mem OUT mem,PA PAC POP POPD mem C2xLP Repeatable X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X C28x Repeatable
Table D3. Repeatable Instructions for the C2xLP and C28x (Continued)
C2xLP Repeatable X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X C28x Repeatable
C2xLP Instruction PSHD mem PUSH ROL ROR SACH mem[,shift] SACL mem[,shift] SAR AR,mem SETC CNF/XF/INTM/OVM/SXM/TC/C SFL SFR SPAC SPH mem SPL mem SPLK #lk,mem SQRA mem SQRS mem SST #n,mem SUB mem[,shift1] SUBB mem SUBC mem SUBS mem SUBT mem TBLR mem TBLW mem
XOR
mem
ZALR mem
D-11
Appendix AppendixE A
Migration From C27x to C28x

This appendix highlights the architecture differences between the C27x and the C28x and describes how to migrate your code from a C27x-based design to a C28x-based design.
Topic
E.1 E.2 E.3 E.4
Page
Architecture Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 Moving to C28x Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 Migrating to C28x Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 Compiling C28x Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16
E-1
Architecture Changes
E.1 Architecture Changes

Certain changes to the architecture that are important when migrating from the C27x to the C28x include: - Changes to registers - Full context save and restore - B0/B1 memory map consideration
E.1.1 Changes to Registers

The register modifications from the C27x are shown in Figure E1. Shaded registers highlight the changes or enhancements for the C28x.
Figure E1. C28x Registers

T(16) PH(16) AH(16) TL(16) PL(16) AL(16) XT(32) P(32) ACC(32) ST0(16) ST1(16) IER(16) DBGIER(16) IFR(16)
SP(16) 6/7bit DP(16) offset AR0H(16) AR1H(16) AR2H(16) AR3H(16) AR4H(16) AR5H(16) AR6H(16) AR7H(16) AR0(16) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) PC(22) RPC(22) XAR0(32) XAR1(32) XAR2(32) XAR3(32) XAR4(32) XAR5(32) XAR6(32) XAR7(32)
A brief description of the register modifications is given below:

XT(32), TL(16): The T register is increased to 32-bits and called the XT register. The existing C27x T register portion represents the upper 16-bits of the new 32-bit register. The additional 16-bits, called the TL portion, represents the lower 16-bits.
XAR0,..,XAR7(32): All of the AR registers are stretched to 32-bits. This enables a full 22-bit address. For addressing operations, only the lower 22-bits of the registers are used, the upper 10-bits are ignored. For operations between the ACC, all 32-bits are valid (register addressing mode @XARx). For 16-bit operations to the low 16-bit of the registers (register addressing mode @ARx), the upper 16-bits are ignored. RPC(22): This is the return PC register. When a call operation is performed, the return address is saved in the RPC register and the old value in the RPC is saved on the stack (in two 16-bit operations). When a return operation is performed, the return address is read from the RPC register and the value on the stack is written into the RPC register (in two 16-bit operations). The net result is that return operations are faster (4 instead of 8 cycles) By default the C28x SP register is initialized to 0x400 after a reset. Shaded items indicate a change or addition from the C27x
SP(16): ST0 (16):
Table E1. ST0 Register Bits

Bit(s) 0 1 2 3 4 5 6 9:7 15:10 PM: Mnemonic SXM OVM TC C Z N V PM OVC/OVCU Description Sign Extension Mode Bit Overflow Mode Bit Test Control Bit Carry Bit Zero Condition Bit Negative Condition Bit Overflow Condition Bit Product Shift Mode ACC Overflow Counter Reset Value 0 0 0 0 0 0 0 0 (+1 shift) 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Functionality of the Product Shift Mode changes if the AMODE bit in ST1 is set to 1. C27x users will not modify the AMODE bit and PM will function as they did on the C27x. The overflow counter is modified so that it behaves differently for signed or unsigned operations. For signed operations (OVC), it behaves as it does on the C27x (increment for positive overflow, decrement for negative underflow of a signed number). For unsigned operations (OVCU), the overflow counter increments for an ADD operation when there is a carry generated and decrements for a SUB operation when a borrow is generated. Basically, in unsigned mode, the OVCU behaves like a carry (C) counter and in signed mode the OVC behaves like an overflow (V) counter.
OVC/OVCU:
E-3
Table E2. ST1 Register Bits

Bit(s) 0 1 2 3 4 5 6 7 8 9 10 11 12 15:13 Syntax INTM DBGM PAGE0 VMAP SPA LOOP EALLOW IDLESTAT AMODE OBJMODE RESERVED M0M1MAP XF ARP Description Interrupt Enable Mask Bit DeBug Enable Mask Bit PAGE0 Direct/Stack Address Mode Vector Map Bit Stack Pointer Align Bit Loop Instruction Status Bit Emulation Access Enable Bit IDLE Status Flag Bit Address Mode Bit Object Compatibility Mode Bit Reserved for future use M0 and M1 Mapping Mode Bit XF Status Bit Auxiliary Register Pointer Reset Value 1 (disabled) 1 (disabled) 0 VMAP input 0 0 0 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R R R/W R/W
AMODE:
This mode selects the appropriate addressing mode decodes for compatibility with the C2xLP device. For all C27x/C28x based projects leave this bit as 0. This mode is used to select between C27x object mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1) compatibility. This bit is set by the C28OBJ (or SETC OBJMODE) instructions. This bit is cleared by the C27OBJ (or CLRC OBJMODE) instructions. The pipeline is flushed when setting or clearing this bit using the given instructions. This bit can be saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset. This mode is used to remap block M0 and M1 in program memory space as discussed in detail in section E.1.2. This bit is set by the C28MAP (or SETC M0M1MAP) instructions. This bit is cleared by the C27MAP (or CLRC M0M1MAP) instructions. The pipeline is flushed when setting or clearing this bit using the given instructions. This bit cannot be restored by interrupts and when restoring the ST1 register (read only). This bit reflects the current state of the XFS output signal. This signal is for C2xLP compatibility and is not used by C27x users.
OBJMODE:
M0M1MAP:
XF:
E.1.2 Full Context Save and Restore

On both C27x and C28x, the registers in Figure E2 are automatically saved on the stack on an interrupt or trap operation and automatically restored on an IRET instruction.
Figure E2. Full Context Save/Restore

31 T AH PH AR1 DP DBGSTAT PCH 16 1 ST0 AL PL AR0 ST1 IER PCL 0
Due to the register changes described in section E.1.1. C28x additional registers must be saved for a full-context store. Figure E3 shows the difference between a C27x and C28x full-context save/restore for an interrupt or trap.
E-5
Figure E3. Code for a Full Context Save/Restore for C28x vs C27x
C27X Full Context Save/Rest IntX: ; 8 cycles push AR3:AR2 push AR5:AR4 push XAR6 push XAR7 ; + 4 = 12 cycles . . . pop XAR7 pop XAR6 pop AR5:AR4 pop AR3:AR2 iret ; 12 cycles
C28x Full Context Save/Restore IntX: ; 8 cycles PUSH AR1H:AR0H ; 32bit PUSH XAR2 ; 32bit PUSH XAR3 ; 32bit PUSH XAR4 ; 32bit PUSH XAR5 ; 32bit PUSH XAR6 ; 32bit PUSH XAR7 ; 32bit PUSH XT ; 32bit ; + 8 = 16 cycles . . . POP XT POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H IRET ; 16 cycles
If you perform a task-switch operation (stack changes), the RPC register must be manually saved. You are not to save the RPC register if the stack is not changed.
E.1.3 B0/B1 Memory Map Consideration

Another architecture change to consider is the C27x mapping of blocks B0 and B1. To avoid confusion, on the C28x these blocks are known as M1 and M0 respectively. On the C27x, block B1 was mapped to only data space and block B0 was mapped both in program and data space. In addition, block B0 was mapped to different address ranges in program and in data space. The C27x mapping of these blocks is shown in Figure E4.
Figure E4. Mapping of Memory Blocks B0 and B1 on C27x

C27x Program Space B0 Data Space 00 0000 B1 00 0400 B0 00 07FF
On a C28x device at reset, these blocks are mapped uniformly in both program and data space as shown in Figure E5. This can cause issues when running C27x object code that relies on the C27x mapping. If your code relies on this mapping, you can flip-block M0 and M1 in program space only by clearing the M0M1MAP bit in status register 1 (ST1) to a 0. Executing the C27MAP (or CLRC M0M1MAP) instruction is the only way to clear this bit. With M0M1MAP == 0, the mapping is compatible with the C27x B0 and B1 blocks as shown in Figure D-4. Remember that after a reset M0 and M1 revert to the C28x mapping. It is strongly recommended that you migrate your code to use the default C28x mapping of these blocks and not rely on the compatible mapping.
Figure E5. C27x Compatible Mapping of Blocks M0 and M1
C28 at Reset (M0M1MAP = 1) Program Space M0 Data Space M0 00 0400 M1 M1 00 07FF 00 0000
C27x Compatible Mapping (M0M1MAP = 0) Program Space Data Space 00 0000 M1 M0 00 0400 M0 M1 00 07FF
E-7
E.1.4 C27x Object Compatibility

At reset, the C28x operates in C27x object mode (OBJMODE == 0). In this mode, the C28x CPU is 100% object-code compatible and cycle-count compatible with the C27x. In this case, you will compile your code just as you would for a C27x design as shown in Figure E6.
Figure E6. Building a C27x Object File From C27x Source

C27x Source Code (.asm .c .cpp) CL2000-V27 C27x Object (.out)
v27
Accepts C27x syntax only. Generates C27x object only (assumes OBJMODE = 0) Once you have taken the mapping of blocks M0 and M1 into account as previously described, you can simply load the C27x object (.out) code into the C28x and run it. When using the C27x compatible mode, you are limited to the C27x instruction set. To take advantage of advanced C28x operations, you should migrate to C28x object code. When the device is operating in C27x object mode (OBJMODE == 0), the upper bits of the stretched registers (XAR0(31:16) to XAR5(31:16), XAR6(31:22), XAR7(31:22)) are protected from writes. Hence, if the registers are set to zero by a reset then the XARn pointers behave like they do on the C27x and overflow problems are not of concern.
Moving to a C28x Object
E.2 Moving to a C28x Object

The C28x instruction set is a superset of the C27x instruction set. The syntax of a number of instructions however has changed slightly due to the modifications in registers as previously described. (For a summary of syntax changes, see Section E.3.1 Instruction Syntax Changes). To quickly move to C28x object code, the codegen tools allow you to build a C28x object file with a switch allowing for C27x source syntax:
Figure E7. Building a C28x Object File From Mixed C27x/C28x Source
C27x/C28x Source Code (.asm .c .cpp) CL2000 V28 m27 C28x Object (.out)
v28m27
Accepts C28x & C27x syntax. Generates C28x object only (assumes OBJMODE == 1) Prior to running C28x object you must set the mode of the device appropriately (OBJMODE == 1). To do this, you set the OBJMODE bit in ST1 to 1 after reset. This can be done with a C28OBJ (or SETC OBJMODE) instruction. Note that before the C28OBJ instruction is executed, the disassembly window in the debugger may display incorrect information. This is because the debugger will decode memory as C27x opcodes until after you execute the C28OBJ instruction. When running in this mode, the disassembly window in your debugger will show the C28x instruction syntax for all instructions. For example, the C27x MOV AR0,@SP instruction will look like MOVZ AR0,@SP, which is the C28x-equivalent instruction. Now that you are using a C28x object file, you can add C28x operations to your source code.
E.2.1 Caution When Changing OJBMODE

On reset, the XARn registers are forced to 0x0000 0000 and OBJMODE == 0. When operating in C27x compatible mode (OBJMODE == 0), the upper bits of the XARn registers are protected from writes. Some things to be aware of when changing OBJMODE:
- When operating in C28x object mode (OBJMODE == 1) overflow can oc-
cur to the extended portion of XARn registers and program execution is not specified. This would be an issue for assembly code that is reassembled in C28x mode when you relied on the fact that C27x registers were a certain size.
- If the user switches to C28x object mode (OBJMODE == 1), then the upper
bits of XARn registers may be modified. If you then switch back to C27x
Migration From C27x to C28x E-9
Moving to a C28x Object
mode (OBJMODE == 0), the upper bits of XARn registers may contain nonzero values. You MUST zero out the upper bits of the XARn registers when switching from OBJMODE == 1 to OBJMODE == 0.
- It is recommended that you not switch modes frequently in your code.
Typically, you will select the appropriate operating mode at boot time and stick to one mode for the whole program.
Migrating to C28x Object Code
E.3 Migrating to C28x Object Code

This section describes additional changes to C27x necessary for migrating your C27x code to pure C28x code.
E.3.1 Instruction Syntax Changes

Syntax changes were necessary for clarity and because of changes in the auxiliary registers stretched pointers. Table E3 shows the C27x instructions that changed syntax on the C28x. For all other C27x instructions, the syntax remains the same. For new C28x instructions, the syntax is documented in Chapter 6.
E-11
Table E3. Instruction Syntax Change

C27x Syntax ADDB ADDB SUBB SUBB MOV MOVB MOV MOVL MOV MOVL MOV MOVL CALL LC CALL LC RET LRET RETE LRETE ARn,#7bit XAR6/7,#7bit ARn,#7bit XAR6/7,#7bit AR0/../5,loc16 AR0/../5,#8bit XAR6/7,loc32 XAR6/7,loc32 XAR6/7,#22bit XAR6/7,#22bit loc32,XAR6/7 loc32,XAR6/7 22bit 22bit *XAR7 *XAR7 ADDB C28x Syntax XARn,#7bit
SUBB
XARn,#7bit
MOVZ MOVB MOVL
AR0/../5,loc16 XAR0/../5,#8bit XAR6/7,loc32
MOVL
XAR6/7,#22bit
MOVL
loc32,XAR6/7
LC
22bit
LC
*XAR7
LRET
LRETE
MOV
ADD SUB CMP MOV NORM NORM NORM NORM B SB
ACC,P
ACC,P ACC,P ACC,P P,ACC
{MOVP
{MOVA {MOVS
T,@T decode}
T,@T decode} T,@T decode}
MOVL ADDL SUBL CMPL MOVL NORM
ACC,P << PM {MOVP ACC,P << PM {MOVA ACC,P << PM {MOVS ACC,P << PM P,ACC ACC,XARn++
T,@T decode} T,@T decode} T,@T decode}
ACC,ARn++ ACC,XAR6/7++ ACC,ARn ACC,XAR6/7 16bitOff 8bitOff {unconditional} {unconditional}
NORM
ACC,XARn
B SB
16bitOff,UNC 8bitOff,UNC
[2] [2]
For conditional branches on the C28x, the UNC code must always be specified for unconditional tests. This will help to distinguish between unconditional C2xLP branches (which have the same mnemonic B).
E.3.2 Repeatable Instructions

On the C28x, additional instructions have been made repeatable. The following two tables list those instructions that are repeatable on the C28x device. These instructions are repeatable in both C27x compatible mode (OBJMODE = 0) and C28x native mode (OBJMODE = 1). Any instruction that is not listed, which follows a repeat instruction, will execute only once. C27x operations that were already repeatable include the following:
ROR ROL NORM NORM SUBCU MAC MOV MOV MOV MOV PREAD PWRITE NOP ACC ACC ACC,XARn++ ACC,XARn ACC,loc16 P,loc16,0:pma *(0:addr),loc16 loc16,*(0:addr) loc16,#16bit loc16,#0 loc16,*XAR7 *XAR7,loc16 loc16
E-13
C27x Operations That Are Made Repeatable On C28x include the following:
MOV ADD ADDU SUB SUBU ADDL SFR LSL MOVH MOV MOVA MOVS MPYA MPYS loc16,AX ACC,loc16 << 16 ACC,loc16 ACC,loc16 << 16 ACC,loc16 ACC,loc32 ACC,1..16 ACC,1..16 loc16,P loc16,P T,loc16 T,loc16 P,T,loc16 P,T,loc16
E.3.3 Changes to the SUBCU Instruction

The SUBCU instruction changed slightly from the C27x to the C28x. Under the prescribed usage of the SUBCU operation, the change will yield the same result as the C27x. The SUBCU instruction operates as follows on the C27x device:
temp(31:0) if( temp32 ACC else ACC = ACC [loc16] << 15 >= 0 ) = temp(31:0) >> 1 + 1; = ACC << 1;
To simplify the implementation, the SUBCU operation changed as follows on the C28x:
temp(32:0) = ACC << 1 [loc16] << 16 if( temp(32:0) >= 0 ) ACC = temp(31:0) + 1; else ACC = ACC << 1; - The temp(32:0) value is the result of an unsigned 33-bit compare. The
carry bit is used to select between y or < condition.
- The C flag is affected by the unsigned 33-bit compare operation. The Z,
N flags reflect the value in the ACC after the operation is complete. The operation of the C, N, Z flags should be identical to the C27x implementation.
- The V flag and overflow counter (OVC) are not affected by the operation.
On the C27x the V and OVC flags are affected. The V and OVC flags may be affected on the C27x and not on the C28x implementation. The values of these flags are not usable under prescribed usage of such an operation.
E-15
Compiling C28x Source Code
E.4 Compiling C28x Source Code

Once you move your code to C28x native instructions, you will no longer use the m27 switch to allow for C27x source as shown in Figure E8.
Figure E8. Compiling C28x Source

C28x Source Code (.asm .c .cpp) CL2000 V28 C28x Object (.out)
v28:
Accepts C28x syntax only. Generates C28x object only (assumes OBJMODE = 1)
Appendix AppendixF A
Revision History
F.1 Changes
This revision history lists the technical changes made in the most recent revision.
Table F1. Revision History

Location Preface page iii Preface page vii Chapter 1 Table 26 Page 2-32 Example 31 Section 3.6 Section 4.1.2 Section 6.1, 6.2 Page 6-78 Page 6-46 Page 6-145 Page 6-149 Page 6-150 Additions, Deletions, Modifications Changed About This Manual introduction and Chapter 1 description. Updated Related Documents From Texas Instruments. Changed introduction. Changed descriptions for MAX, MAXL, MIN, and MINL. Changed description of SXM bit values and added example code. Removed period in first line and changed semicolon to colon in 21st line. Added fourth bullet and fifth bullets. Changed DZ to D2. Added note on cycle counts. Changed example for CMP64 ACC:P instruction. Changed 0xFFBE to 0xFFDE in example for AND IER, #16bit instruction. Changed RPT and CYC values for MAC P, loc16, 0:pma instruction. Changed then to than for MAX AX, loc16 instruction. Added closing square bracket in Description note and changed 2 to 0 in 7th line of example for MAXCUL P, loc32 instruction.
Page 6-152, 6-153, 6-154 Changed then to than for multiple instructions.
F-1
Table F1. Revision History

Location Page 6-168 Page 6-201 Additions, Deletions, Modifications Changed Repeat description for MOV loc16, ARn instruction. Changed operand from loc16 to loc32, modified Repeat description, and moved notes in example for MOVDL instruction. Changed T to XT in Description of MOVL loc32, XT instruction. Changed operand listed for Description from loc32 for MOVX TL, loc16 instruction. Changed PSA to SPA in Flags and Modes for NASP instruction. Changed OPCODE value for POP ACC instruction. Modified alignment of code in Description for SAT ACC instruction. Changed RPT and CYC values for SFR ACC, T instruction. Changed Repeat description for SPM shift instruction. Added else to N flag description for SUB ACC, #16bit << 0..15 instruction. Changed to in Description to from for SUBB SP, #7bit instruction. Changed ADD to XOR in 6th line of example for TBIT loc16, T instruction. Corrected grammar in Description and added SP = SP + 2; line in example for TRAP #VectorNumber instruction. Added POP to Instructions for IFR register. Removed original Appendix B, Submitting Rom Codes to TI, and renumbered remaining appendices.
Page 6-211 Page 6-224
Page 6-243 Page 6-267 Page 6-313 Page 6-326 Page 6-327 Page 6-337 Page 6-341 Page 6-360 Page 6-363
Table A1 Appendix BE
Revision History
F-3
Appendix AppendixG A
Glossary
16-bit operation: An operation that reads or writes 16 bits. 32-bit operation: An operation that reads or writes 32 bits.
A
absolute branch: A branch to an address that is permanently assigned to a memory location. See also offset branch. ACC: See accumulator (ACC). access: A term used in this document to mean read from or write to. For example, to access a register is to read from or write to that register. accumulator (ACC): A 32-bit register involved in a majority of the arithmetic and logical calculations done by the C28x. Some instructions that affect ACC use all 32 bits of the register. Others use one of the following portions of ACC: AH (bits 31 through 16), AL (bits 15 through 0), AH.MSB (bits 31 through 24), AH.LSB (bits 23 through 16), AL.MSB (bits 15 through 8), and AL.LSB (bits 7 through 0). address-generation logic: Hardware in the CPU that generates the addresses used to fetch instructions or data from memory. address reach: The range of addresses beginning with 00 000016 that can be used by a particular addressing mode. address register arithmetic unit (ARAU): Hardware in the CPU that generates addresses for values that must be fetched from data memory. The ARAU is also the hardware used to increment or decrement the stack pointer (SP) and the auxiliary registers (AR0, AR1, AR2, AR3, AR4, AR5, XAR6, and XAR7). addressing mode: The method by which an instruction interprets its operands to acquire the data and/or addresses it needs. AH: High word of the accumulator. The name given to bits 31 through 16 of the accumulator.
G-1
Glossary
AH.LSB: Least significant byte of AH. The name given to bits 23 through 16 of the accumulator. AH.MSB: Most significant byte of AH. The name given to bits 31 through 24 of the accumulator. AL: Low word of the accumulator. The name given to bits 15 through 0 of the accumulator. AL.LSB: Least significant byte of AL. The name given to bits 7 through 0 of the accumulator. AL.MSB: Most significant byte of AL. The name given to bits 15 through 8 of the accumulator. ALU: See arithmetic logic unit (ALU). analysis logic: A portion of the emulation logic in the core. The analysis logic is responsible for managing the following debug activities: hardware breakpoints, hardware watchpoints, data logging, and benchmark/event counting. approve an interrupt request: Allow an interrupt to be serviced. If the interrupt is maskable, the CPU approves the request only if it is properly enabled. If the interrupt is nonmaskable, the CPU approves the request immediately. See also interrupt request and service an interrupt. ARAU: See address register arithmetic unit (ARAU). arithmetic logic unit (ALU): A 32-bit hardware unit in the CPU that performs 2s-complement arithmetic and Boolean logic operations. The ALU accepts inputs from data from registers, from data memory, or from the program control logic. The ALU sends results to a register or to data memory. arithmetic shift: A shift that treats the shifted value as signed. See also logical shift. ARP: See auxiliary register pointer (ARP). ARP indirect addressing mode: The indirect addressing mode that uses the current auxiliary register to point to a location in data space. The current auxiliary register is the auxiliary register pointed to by the ARP. See also auxiliary register pointer (ARP). automatic context save: A save of system context (modes and key register values) performed by the CPU just prior to executing an interrupt service routine. See also context save.
Glossary
auxiliary register: One of eight registers used as a pointer to a memory location. The register is operated on by the auxiliary register arithmetic unit (ARAU) and is selected by the auxiliary register pointer (ARP). See also AR0AR5, AR6/AR7, and XAR6/XAR7. auxiliary-register indirect addressing mode: The indirect addressing mode that allows you to use the name of an auxiliary register in an operand that uses that register as a pointer. See also ARP indirect addressing mode. auxiliary register pointer (ARP): A 3-bit field in status register ST1 that selects the current auxiliary register. When an instruction uses ARP indirect addressing mode, that instruction uses the current auxiliary register to point to data space. When an instruction specifies auxiliary register n by using auxiliary-register indirect addressing mode, the ARP is updated, so that it points to auxiliary register n. See also current auxiliary register.
B
background code: The body of code that can be halted during debugging because it is not time-critical. barrel shifter: Hardware in the CPU that performs all left and right shifts of register or data-space values. bit field: One or more register bits that are differentiated from other bits in the same register by a specific name and function. bit manipulation: The testing or modifying of individual bits in a register or data-space location. boundary scan: The use of scan registers on the border of a chip or section of logic to capture the pin states. By scanning these registers, all pin states can be transmitted through the JTAG port for analysis. branch: 1) A forcing of program control to a new address. 2) An instruction that forces program control to a new address but neither saves a return address (like a call) nor restores a return address (like a return). break event: A debug event that causes the CPU to enter the debug-halt state. breakpoint: A place in a routine specified by a breakpoint instruction or hardware breakpoint, where the execution of the routine is to be halted and the debug-halt state entered.
Glossary G-3
Glossary
C
C bit: See carry (C) bit. call: 1) The operation of saving a return address and then forcing program control to a new address. 2) An instruction that performs such an operation. See also return. carry (C) bit: A bit in status register ST0 that reflects whether an addition has generated a carry or a subtraction has generated a borrow. circular addressing mode: The indirect addressing mode that can be used to implement a circular buffer. circular buffer: A block of addresses referenced by a pointer using circular addressing mode, so that each time the pointer reaches the bottom of the block, the pointer is modified to point back to the top of the block. clear : To clear a bit is to write a 0 to it. To clear a register or memory location is to load all its bits with 0s. See also set. COFF: Common object file format. A binary object file format that promotes modular programming by supporting the concept of sections, where a section is a relocatable block of code or data that ultimately occupies a space adjacent to other blocks of code in the memory map. conditional branch instruction: A branch instruction that may or may not cause a branch, depending on a specified or predefined condition (for example, the state of a bit). context restore: A restoring of the previous state of a system (for example, modes and key register values) prior to returning from a subroutine. See also context save. context save: A save of the current state of a system (for example, modes and key register values) prior to executing the main body of a subroutine that requires a different context. See also context restore. core: The portion of the C28x that consists of a CPU, a block of emulation circuitry, and a set of signals for interfacing with memory and peripheral devices. current auxiliary register: The register selected by the auxiliary register pointer (ARP) in status register. For example, if ARP = 3, the current auxiliary register is AR3. See also auxiliary registers. current data page: The data page selected by the data page pointer. For example, if DP = 0, the current data page is 0. See also data page.
Glossary
D
D1 phase: See decode 1 (D1) phase. D2 phase: See decode 2 (D2) phase. data logging: Transferring one or more packets of data from CPU registers or memory to an external host processor. data log interrupt (DLOGINT): A maskable interrupt triggered by the onchip emulation logic when a data logging transfer has been completed. data page: A 64-word portion of the total 4M words of data space. Each data page has a specific start address and end address. See also data page pointer (DP) and current data page. data page pointer (DP): A 16-bit pointer that identifies which 64-word data page is accessed in DP direct addressing mode. For example, for as long as DP = 500, instructions that use DP direct addressing mode will access data page 500. data-/program-write data bus (DWDB): The bus that carries data during writes to data space or program space. data-read address bus (DRAB): The bus that carries addresses for reads from data space. data-read data bus (DRDB): The bus that carries data during reads from data space. data-write address bus (DWAB): The bus that carries addresses for writes to data space. DBGIER: See debug interrupt enable register (DBGIER). DBGM bit: See debug enable mask (DBGM) bit. DBGSTAT: See debug status register (DBGSTAT). debug-and-test direct memory access (DTDMA): An access of a register or memory location to provide visibility to this location during debugging. The access is performed with variable levels of intrusiveness by a hardware DT-DMA mechanism inside the core. debug enable mask (DBGM) bit: A bit in status register ST1 used to enable (DBGM = 0) or disable (DBGM = 1) debug events such as analysis breakpoints or debug-and-test direct memory accesses (DT-DMAs).
Glossary G-5
Glossary
debug event: An action such as the decoding of a software breakpoint instruction, the occurrence of an analysis breakpoint/watchpoint, or a request from a host processor that may result in special debug behavior, such as halting the device or pulsing one of the debug interface signals EMU0 or EMU1. See also break event and debug enable mask (DBGM) bit. debug-halt state: A debug execution state that is entered through a break event. In this state the CPU is halted. See also single-instruction state and run state. debug host: See host processor. debug interrupt enable register (DBGIER): The register that determines which of the maskable interrupts are time-critical when the CPU is halted in real-time mode. If a bit in the DBGIER is 1, the corresponding interrupt is time-critical/enabled; otherwise, it is disabled. Time-critical interrupts also must be enabled in the interrupt enable register (IER) to be serviced. debug status register (DBGSTAT): A register that holds special debug status information. This register, which need not be read from or written to, is saved and restored during interrupt servicing, to preserve the debug context during debugging. decode an instruction: To identify an instruction and prepare the CPU to perform the operation the instruction requires. decode 1 (D1) phase: The third of eight pipeline phases an instruction passes through. In this phase, the CPU identifies instruction boundaries in the instruction-fetch queue and determines whether the next instruction to be executed is an illegal instruction. See also pipeline phases. decode 2 (D2) phase: The fourth of eight pipeline phases an instruction passes through. In this phase, the CPU accepts an instruction from the instruction-fetch queue and completes the decoding of that instruction, performing such activities as address generation and pointer modification. See also pipeline phases. decrement: To subtract 1 or 2 from a register or memory value. The value subtracted depends on the circumstance. For example, if you use the operand *AR4, the auxiliary register AR4 is decremented by 1 for a 16-bit operation and by 2 for a 32-bit operation. device reset: See reset.
Glossary
direct addressing modes: The addressing modes that access data space as if it were 65 536 separate blocks of 64 words each. DP direct addressing mode uses the data page pointer (DP) to select a data page from 0 to 65 535. PAGE0 direct addressing mode uses data page 0, regardless of the value in the DP. discontinuity: DLOGINT: See program-flow discontinuity.
See data log interrupt (DLOGINT).
DP: See data page pointer (DP). DP direct addressing mode: A direct addressing mode that uses the data page pointer (DP) to select a data page from 0 to 65 535. See also PAGE0 direct addressing mode. DRAB: See data-read address bus (DRAB). DRDB: See data-read data bus (DRDB). DTDMA: See debug-and-test direct memory access (DT-DMA). DWAB: See data-write address bus (DWAB). DWDB: See data-/program-write data bus (DWDB).
E
E phase: See execute (E) phase. EALLOW bit: See emulation access enable (EALLOW) bit. EMU0 and EMU1 pins: Pins known as the TI extensions to the JTAG interface. These pins can be used as either inputs or outputs and are available to help monitor and control an emulation target system that is using a JTAG interface. emulation access enable (EALLOW) bit: A bit in status register ST1 that enables (EALLOW = 1) or disables (EALLOW = 0) access to the emulation registers. The EALLOW instruction sets the EALLOW bit, and the EDIS instruction clears the EALLOW bit. emulation logic: The block of hardware in the core that is responsible controlling emulation activities such as data logging and switching among debug execution states. emulation registers: Memory-mapped registers that are available for controlling and monitoring emulation activities.
Glossary G-7
Glossary
enable bit: See interrupt enable bits. execute an instruction: Take an instruction from the decode 2 phase of the pipeline through the write phase of the pipeline. execute (E) phase: The seventh of eight pipeline phases an instruction passes through. In this phase, the CPU performs all multiplier, shifter, and arithmetic-logic-unit (ALU) operations. See also pipeline phases. extended auxiliary registers: See XAR6/XAR7.
F
F1 phase: See fetch 1 (F1) phase. F2 phase: See fetch 2 (F2) phase. FC : See fetch counter (FC). fetch 1 (F1) phase: The first of eight pipeline phases an instruction passes through. In this phase, the CPU places on the program-read bus the address of the instruction(s) to be fetched. See also pipeline phases. fetch 2 (F2) phase: The second of eight pipeline phases an instruction passes through. In this phase, the CPU fetches an instruction or instructions from program memory. See also pipeline phases. fetch counter (FC) : The register that contains the address of the instruction that is being fetched from program memory. field : See bit field.
H
hardware interrupt: An interrupt initiated by a physical signal (for example, from a pin or from the emulation logic). See also software interrupt. hardware interrupt priority: A priority ranking used by the CPU to determine the order in which simultaneously occurring hardware interrupts are serviced. hardware reset: See reset. high addresses: Addresses closer to 3F FFFF16 than to 00 000016. See also low addresses. high bits: See MSB.
Glossary
high word: The 16 MSBs of a 32-bit value. See also low word. host processor: The processor running the user interface for a debugger.
I
IC: See instruction counter (IC). IDLESTAT (IDLE status) bit: A bit in status register ST1 that indicates when an IDLE instruction has the CPU in the idle state (IDLESTAT = 1). idle state: The low-power state the CPU enters when it executes the IDLE instruction. IEEE 1149.1 standard: IEEE Standard Test Access Port and BoundaryScan Architecture, first released in 1990. See also JTAG. IER: See interrupt enable register (IER). IFR: See interrupt flag register (IFR). illegal instruction: An unacceptable value read from program memory during an instruction fetch. Unacceptable values are 000016, FFFF16, or any value that does not match a defined opcode. illegal-instruction trap: A trap that is serviced when an illegal instruction is decoded. immediate address: An address that is specified directly in an instruction as a constant. immediate addressing modes: Addressing modes that accept a constant as an operand. immediate constant/data: A constant specified directly as an operand of an instruction. immediate-constant addressing mode: An immediate addressing mode that accepts a constant as an operand and interprets that constant as data to be stored or processed. immediate-pointer addressing mode: An immediate addressing mode that accepts a constant as an operand and interprets that constant as the 16 LSBs of a 22-bit address. The six MSBs of the address are filled with 0s. increment: To add 1 or 2 to a register or memory value. The value added depends on the circumstance. For example, if you use the operand *AR4++, the auxiliary register AR4 is incremented by 1 for a 16-bit operation and by 2 for a 32-bit operation.
Glossary G-9
Glossary
indirect addressing modes: Addressing modes that use pointers to access memory. The available pointers are auxiliary registers AR0AR5, extended auxiliary registers XAR6 and XAR7, and the stack pointer (SP). instruction boundary: The point where the CPU has finished one instruction and is considering what it will do next move on to the next instruction. instruction counter (IC): The register that points to the instruction in the decode 1 phase (the instruction that is to enter the decode 2 phase next). Also, on an interrupt or call operation, the IC value represents the return address, which is saved to the stack or to auxiliary register XAR7. instruction-fetch mechanism: The hardware for the fetch 1 and fetch 2 phases of the pipeline. This hardware is responsible for fetching instructions from program memory and filling an instruction-fetch queue. instruction-fetch queue: A queue of four 32-bit registers that receives fetched instructions and holds them for decoding. When a program-flow discontinuity occurs, the instruction-fetch queue is emptied. instruction-not-available condition: The condition that occurs when the decode 2 pipeline hardware requests an instruction but there are no instructions waiting in the instruction-fetch queue. This condition causes the decode 2 through write phases of the pipeline to freeze until one or more new instructions have been fetched. instruction register: The register that contains the instruction that has reached the decode 2 pipeline phase. instruction word: Either an entire 16-bit opcode or one of the halves of a 32-bit opcode. INT1INT14: Fourteen general-purpose interrupts that are triggered by signals at pins of the same names. These interrupts are maskable and have corresponding bits in the interrupt flag register (IFR), the interrupt enable register (IER), and the debug interrupt enable register (DBGIER). Interrupt boundary: An instruction boundary where the CPU can insert an interrupt between two instructions. See also instruction boundary. interrupt enable bits: Bits responsible for enabling or disabling maskable interrupts. The enable bits are all the bits in the interrupt enable register (IER), all the bits in the debug interrupt enable register (DBGIER), and the interrupt global mask bit (INTM in status register ST1). interrupt enable register (IER): Each of the maskable interrupts has an interrupt enable bit in this register. If a bit in the IER is 1, the corresponding interrupt is enabled; otherwise, it is disabled. See also debug interrupt enable register (DBGIER).
Glossary
interrupt flag bit: A bit in the interrupt flag register (IFR). If the interrupt flag bit is 1, the corresponding interrupt has been requested by hardware and is awaiting approval by the CPU. interrupt flag register (IFR): The register that contains the interrupt flag bits for the maskable interrupts. If a bit in the IFR is 1, the corresponding interrupt has been requested by hardware and is awaiting approval by the CPU. interrupt global mask (INTM) bit: A bit in status register ST1 that globally enables or disables the maskable interrupts. If an interrupt is enabled in the interrupt enable register (IER) but not by the INTM bit, it is not serviced. The only time this bit is ignored is when the CPU is in real-time mode and is in the debug-halt state; in this situation, the interrupt must be enabled in the IER and in the DBGIER (debug interrupt enable register). interrupt priority: See hardware interrupt priority. interrupt request: A signal or instruction that requests the CPU to execute a particular interrupt service routine. See also approve an interrupt request and service an interrupt. interrupt service routine (ISR): A subroutine that is linked to a specific interrupt by way of an interrupt vector. interrupt vector: The start address of an interrupt service routine. After approving an interrupt request, the CPU fetches the interrupt vector from your interrupt vector table and uses the vector to branch to the start of the corresponding interrupt service routine. interrupt vector location: The preset location in program memory where an interrupt vector must reside. interrupt vector table: The list of interrupt vectors you assign in program memory. INTM bit: See interrupt global mask (INTM) bit. ISR: See interrupt service routine (ISR).
Glossary
G-11
Glossary
J
JTAG: Joint Test Action Group. The Joint Test Action Group was formed in 1985 to develop economical test methodologies for systems designed around complex integrated circuits and assembled with surface-mount technologies. The group drafted a standard that was subsequently adopted by IEEE as IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture. See also boundary scan; test access port (TAP). JTAG port: See test access port (TAP).
L
latch: Hold a bit at the same value until a given event occurs. For example, when an overflow occurs in the accumulator, the V bit is set and latched at 1 until it is cleared by a conditional branch instruction or by a write to status register ST0. An interrupt is latched when its flag bit has been latched in the interrupt flag register (IFR). least significant bit (LSB): The bit in the lowest position of a binary number. For example, the LSB of a 16-bit register value is bit 0. See also MSB, LSByte, and MSByte. least significant byte (LSByte): The byte in the lowest position of a binary value. The LSByte of a value consists of the eight LSBs. See also MSByte, LSB, and MSB. location: A space where data can reside. A location may be a CPU register or a space in memory. logical shift: A shift that treats the shifted value as unsigned. See also arithmetic shift. LOOP (loop instruction status) bit: A bit in status register ST1 that indicates when a LOOPNZ or LOOPZ instruction is being executed (LOOP = 1). low addresses: Addresses closer to 00 000016 than to 3F FFFF16. See also high addresses. low bits: See LSB. low word: The 16 LSBs of a 32-bit value. See also high word.
Glossary
LSB: When used in a syntax of the MOVB instruction, LSB means least significant byte. Otherwise, LSB means least significant bit. See least significant bit (LSB) and least significant byte (LSByte). LSByte: See least significant byte (LSByte).
M
maskable interrupt: An interrupt that can be disabled by software so that the CPU does not service it until it is enabled by software. See also nonmaskable interrupt. memory interface: The buses and signals responsible for carrying communications between the core and on-chip memory/peripherals. memory-mapped register: A register that can be accessed at addresses in data space. memory wrapper: The hardware around a memory block that identifies access requests and controls accesses for that memory block. mirror: A range of addresses that is the same size and is mapped to the same physical memory block as another range of addresses. most significant bit (MSB): The bit in the highest position of a binary number. For example, the MSB of a 16-bit register value is bit 15. See also LSB, LSByte, and MSByte. most significant byte (MSByte): The byte in the highest position of a binary value. The MSByte of a value consists of the eight MSBs. See also LSByte, LSB, and MSB. MSB: When used in a syntax of the MOVB instruction, MSB means most significant byte. Otherwise MSB means most significant bit. See most significant bit (MSB) and most significant byte (MSByte). MSByte: See most significant byte (MSByte). multiplicand register (T): The primary function of this register, also called the T register, is to hold one of the values to be multiplied during a multiplication. The following shift instructions use the four LSBs to hold the shift count: ASR (arithmetic shift right), LSL (logical shift left), LSR (logical shift right), and SFR (shift accumulator right). The T register can also be used as a general-purpose 16-bit register.
Glossary G-13
Glossary
N
N (negative flag) bit: A bit in status register ST0 that indicates whether the result of a calculation is a negative number (N = 1). N is set to match the MSB of the result. nested interrupt: An interrupt that occurs within an interrupt service routine. NMI: A hardware interrupt that is nonmaskable, like reset (RS), but does not reset the CPU. NMI simply forces the CPU to execute its interrupt service routine. nonmaskable interrupt: An interrupt that cannot be blocked by software and is approved by the CPU immediately. See also maskable interrupt.
O
offset branch: A branch that uses a specified or generated offset value to jump to an address relative to the current position of the program counter (PC). See also absolute branch. opcode: This document uses opcode to mean the complete code for an instruction. Thus, an opcode includes the binary sequence for the instruction type and the binary sequence and/or constant in which the operands are encoded. operand : This document uses operand to mean one of the values entered after the instruction mnemonic and separated by commas (or for a shift operand, separated by the symbol <<). For example, in the CLRC INTM instruction, CLRC is the mnemonic and INTM is the operand. operation: 1) A defined action; namely, the act of obtaining a result from one or more operands in accordance with a rule that completely specifies the result of any permitted combination of operands. 2) The set of such acts specified by a rule, or the rule itself. 3) The act specified by a single computer instruction. 4) A program step undertaken or executed by a computer; for example, addition, multiplication, extraction, comparison, shift, transfer, etc. 5) The specific action performed by a logic element. OVC: See overflow counter (OVC). OVM: See overflow mode (OVM) bit.
Glossary
overflow counter (OVC): A 6-bit counter in status register ST0 that can be used to track overflows in the accumulator (ACC). The OVC is enabled only when the overflow mode (OVM) bit in ST0 is 0. When OVM = 0, the OVC is incremented by 1 for every overflow in the positive direction (too large a positive number) and decremented by 1 for every overflow in the negative direction (too large a negative number). The saturate (SAT) instruction modifies ACC to reflect the net overflow represented in the OVC. overflow flag (V): A bit in status register ST0 that indicates when the result of an operation causes an overflow in the location holding the result (V = 1). If no overflow occurs, V is not modified. overflow mode (OVM) bit: A bit in the status register ST0 that enables or disables overflow mode. When overflow mode is on (OVM = 1) and an overflow occurs, the CPU fills the accumulator (ACC) with a saturation value. When overflow mode is off (OVM = 0), the CPU lets ACC overflow normally but keeps track of each overflow by incrementing or decrementing by 1 the overflow counter (OVC) in ST0.
P
P register: See product register (P). PAB: See program address bus (PAB). PAGE0 bit: PAGE0 addressing mode configuration bit. This bit, in status register ST1, selects between two addressing modes: PAGE0 stack addressing mode (PAGE = 0) and PAGE0 direct addressing mode (PAGE0 = 1). PAGE0 direct addressing mode: The direct addressing mode that uses data page 0 regardless of the value in the data page pointer (DP). This mode is available only when the PAGE0 bit in status register ST1 is 1. See also DP direct addressing mode and PAGE0 stack addressing mode. PAGE0 stack addressing mode: The indirect addressing mode that references a value on the stack by subtracting a 6-bit offset from the current position of the stack pointer (SP). This mode is available only when the PAGE0 bit in status register ST1 is 0. See also stack-pointer indirect addressing mode. PC: See program counter (PC). pending interrupt: An interrupt that has been requested but is waiting for approval from the CPU. See also approve an interrupt request.
Glossary G-15
Glossary
peripheral-interface logic: Hardware that is responsible for handling communications between a processor and a peripheral. PH: The high word (16 MSBs) of the P register. phases: See pipeline phases.
pipeline: The hardware in the CPU that takes each instruction through eight independent phases for fetching, decoding, and executing. During any given CPU cycle, there can be up to eight instructions in the pipeline, each at a different phase of completion. The phases, listed in the order in which instructions pass through them, are fetch 1, fetch 2, decode 1, decode 2, read 1, read 2, execute, and write. pipeline conflict: A situation in which two instructions in the pipeline try to access a register or memory location out of order, causing improper code operation. The C28x pipeline inserts as many inactive cycles as needed between conflicting instructions to prevent pipeline conflicts. pipeline freeze: A halt in pipeline activity in one of the two decoupled portions of the pipeline. Freezes in the fetch 1 through decode 1 portion of the pipeline are caused by a not-ready signal from program memory. Freezes in the decode 2 through write portion are caused by lack of instructions in the instruction-fetch queue or by not-ready signals from memory. pipeline phases: The eight stages an instruction must pass through to be fetched, decoded, and executed. The phases, listed in the order in which instructions pass through them, are fetch 1, fetch 2, decode 1, decode 2, read 1, read 2, execute, and write. pipeline-protection mechanism: The mechanism responsible for identifying potential pipeline conflicts and preventing them by adding inactive cycles between the conflicting instructions. PL: The low word (16 LSBs) of the P register. PM bits: See product shift mode (PM) bits. PRDB: See program-read data bus (PRDB). priority: See interrupt priority. product register (P): This register, also called the P register, is given the results of most multiplications done by the CPU. The only other register that can be given the result of a multiplication is the accumulator (ACC). See also PH and PL.
Glossary
product shift mode (PM) bits: A 3-bit field in status register ST0 that enables you to select one of eight product shift modes. The product shift mode determines whether or how the P register value is shifted before being used by an instruction. You have the choices of a left shift by 1 bit, no shift, or a right shift by N, where N is a number from 1 to 6. program address bus (PAB): The bus that carries addresses for reads and writes from program space. program address generation logic: This logic generates the addresses used to fetch instructions or data from program memory and places each address on the program address bus (PAB). program control logic: This logic stores a queue of instructions that have been fetched from program memory by way of the program-read bus (PRDB). It also decodes these instructions and passes commands and constant data to other parts of the CPU. program counter (PC): When the pipeline is full, the 22-bit PC always points to the instruction that is currently being processedthe instruction that has just reached the decode 2 phase of the pipeline. program-flow discontinuity: A branching to a nonsequential address caused by a branch, a call, an interrupt, a return, or the repetition of an instruction. program-read data bus (PRDB): The bus that carries instructions or data during reads from program space.
R
R1 phase: See read 1 (R1) phase. R2 phase: See read 2 (R2) phase. read 1 (R1) phase: The fifth of eight pipeline phases an instruction passes through. In this phase, if data is to be read from memory, the CPU drives the address(es) on the appropriate address bus(es). See also pipeline phases. read 2 (R2) phase: The sixth of eight pipeline phases an instruction passes through. In this phase, data addressed in the read 1 phase is fetched from memory. See also pipeline phases.
Glossary G-17
Glossary
ready signals: When the core requests a read from or write to a memory device or peripheral device, that device can take more time to finish the data transfer than the core allots by default. Each device must use one of the cores ready signals to insert wait states into the data transfer when it needs more time. Wait-state requests freeze a portion of the pipeline if they are received during the fetch 1, read 1, or write pipeline phase of an instruction. real-time mode: An emulation mode that enables you execute certain interrupts (time-critical interrupts), even when the CPU is halted. See also stop mode. real-time operating system interrupt (RTOSINT): A maskable hardware interrupt generated by the emulation hardware in response to certain debug events. This interrupt should be disabled in the interrupt enable register (IER) and the debug interrupt enable register (DBGIER) unless there is a real-time operating system present in your debug system. reduced instruction set computer (RISC): A computer whose instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. register addressing mode: An addressing mode that enables you to reference registers by name. register conflict: A pipeline conflict that would occur if an instruction read a register value before that value were changed by a prior instruction. The C28x pipeline inserts as many inactive cycles as needed between conflicting instructions to prevent register conflicts. register pair: One of the pairs of CPU register stored to the stack during an automatic context save. repeat counter (RPTC): The counter that is loaded by the RPT (repeat) instruction. The number in the counter is the number of times the instruction qualified by RPT is to be repeated after its initial execution. reserved: A term used to describe memory locations or other items that you cannot use or modify. reset: To return the DSP to a known state; an action initiated by the reset (RS) signal. return: 1) The operation of forcing program control to a return address. 2) An instruction that performs such an operation. See also call. return address: The address at which the CPU resumes processing after executing a subroutine or interrupt service routine.
Glossary
RISC: See reduced instruction set computer (RISC). rotate operation: An operation performed by the ROL (rotate accumulator left) or ROR (rotate accumulator right) instruction. The operation, which involves a shift by 1 bit, can be seen as the rotation of a 33-bit value that is the concatenation of the carry bit (C) and the accumulator (ACC). RPTC: See repeat counter (RPTC). RTOSINT : See real-time operating system interrupt (RTOSINT). RUN command : A debugger command used to execute all or a portion of a program. The RUN 1 command causes the debugger to execute a single instruction. run state: A debug execution state. In this state, the CPU is executing code and servicing interrupts freely. See also debug-halt state and single-instruction state.
S
select signal: An output signal from the C28x that can be used to select specific memory or peripheral devices for particular types of read and write operations. scan controller: A device that performs JTAG state sequences sent to it by a host processor. These sequences, in turn, control the operation of a target device. service an interrupt : The CPU services an interrupt by preparing for and then executing the corresponding interrupt service routine. See also interrupt request and approve an interrupt request. set: To set a bit is to write a 1 to it. If a bit is set, it contains 1. See also clear. sign extend: To fill the unused most significant bits (MSBs) of a value with copies of the values sign bit. sign-extension mode (SXM) bit: A bit in status register ST0 that enables or suppresses sign extension. When sign-extension is enabled (SXM = 1), operands of certain instructions are treated as signed and are sign extended during shifting. single-instruction state: A debug execution state. In this state, the CPU executes one instruction and then returns to the debug-halt state. See also debug-halt state and run state.
Glossary G-19
Glossary
16-bit operation: An operation that reads or writes 16 bits. software interrupt: An interrupt initiated by an instruction. See also hardware interrupt. SP: See stack pointer (SP). SPA bit: See stack pointer alignment (SPA) bit. ST0: See status registers ST0 and ST1. ST1: See status registers ST0 and ST1. stack : The C28x stack is a software stack implemented by the use of a stack pointer (SP). The SP, a 16-bit CPU register, can be used to reference a value in the first 64K words of data memory (addresses 00 00001600 FFFF16). stack pointer (SP): A 16-bit CPU register that enables you to use any portion of the first 64K words of data memory as a software stack. The SP always points to the next empty location in the stack. stack pointer alignment (SPA) bit: A bit in status register ST1 that indicates whether an ASP instruction has forced the SP to align to the next even address (SPA = 1). stack-pointer indirect addressing mode: The indirect addressing mode that references a data-memory value at the current position of the stack pointer (SP). See also PAGE0 stack addressing mode. status registers ST0 and ST1: These CPU registers contain control bits that affect the operation of the C28x and contain flag bits that reflect the results of operations. STEP command: A debugger command that causes the debugger to single-step through a program. The STEP1 command causes the debugger to execute a single instruction. stop mode: An emulation mode that provides complete control of program execution. When the CPU is halted in stop mode, all interrupts (including reset and nonmaskable interrupts) are ignored until the CPU receives a directive to run code again. See also real-time mode. suppress sign extension: Prevent sign extension from occurring during a shift operation. See also sign extend. SXM bit: See sign-extension mode (SXM) bit.
Glossary
T
T register: The primary function of this register, also called the multiplicand register, is to hold one of the values to be multiplied during a multiplication. The following shift instructions use the four LSBs to hold the shift count: ASR (arithmetic shift right), LSL (logical shift left), LSR (logical shift right), and SFR (shift accumulator right). The T register can also be used as a general-purpose 16-bit register. TAP: See test access port (TAP). target device/system: The device/system on which the code you have developed is executed. TC bit: See test/control flag (TC). test access port (TAP): A standard communication port defined by IEEE standard 1149.11990 included in the DSP to implement boundary scan functions and/or to provide communication between the DSP and emulator. test/control flag (TC): A bit in status register ST0 that shows the result of a test performed by the TBIT (test bit) instruction or the NORM (normalize) instruction. test-logic-reset: A test and emulation logic condition that occurs when the TRST signal is pulled low or when the TMS signal is used to advance the JTAG state machine to the TLR state. This logic is a different type than that used by the CPU, which resets functional logic. 32-bit operation: An operation that reads or writes 32 bits. TI extension pins: See EMU0 and EMU1 pins. time-critical interrupt: An interrupt that must be serviced even when background code is halted. For example, a time-critical interrupt might service a motor controller or a high-speed timer. See also debug interrupt enable register (DBGIER).
U
USER1USER12 interrupts: The interrupt vector table contains twelve locations for user-defined software interrupts. These interrupts, called USER1USER12 in this document, can be initiated only by way of the TRAP instruction.
Glossary G-21
Glossary
V
V bit (overflow flag): A bit in status register ST0 that indicates when the result of an operation causes an overflow in the location holding the result (V = 1). If no overflow occurs, V is not modified. vector: See interrupt vector. vector location: See interrupt vector location. vector map (VMAP) bit: A bit in status register ST1 that determines the addresses to which the interrupt vectors are mapped. When VMAP = 0, the interrupt vectors are mapped to addresses 00 00001600 003F16 in program memory. When VMAP = 1, the vectors are mapped to addresses 3F FFC0163F FFFF16 in program memory. vector table: See interrupt vector table.
W
W phase: See write (W) phase. wait state: A cycle during which the CPU waits for a memory or peripheral device to be ready for a read or write operation. watchpoint: A place in a routine where it is to be halted if an address or an address and data combination match specified compare values. When a watchpoint is reached, the routine is halted and the CPU enters the debug-halt state. word: In this document, a word is 16 bits unless specifically stated to be otherwise. write (W) phase: The last of eight pipeline phases an instruction passes through. In this phase, if a value or result is to be written to memory, the CPU sends to memory the destination address and the data to be written. See also pipeline phases.
Z
zero fill: Fill the unused low- and/or high-order bits of a value with 0s. zero flag (Z): A bit in status register ST0 that indicates when the result of an operation is 0 (Z = 1).
Index
Index
2s complement subtraction to ARx C-14 ADDB AX, #8bitSigned 6-31 ADDB SP, #7bit 6-32 ADDB XARn, #7bit 6-33 ADDCL ACC, loc32 6-34 ADDCU ACC, loc16 6-35 ADDL ACC, loc32 6-36 ADDL ACC, P < PM 6-37 ADDL loc32 ACC 6-38 address buses 1-9 address counters FC IC and PC 4-5 address maps 1-8 address reach B-5 address register arithmetic unit (ARAU) 1-5 2-2 addressing modes 5-1 5-2 byte 5-31 direct 2-10 direct addressing 5-2 indirect 2-12 indirect addressing 5-2 program space 5-30 register 5-25 stack addressing 5-2 Addressing Modes for loc16 or loc32 table 5-4 Addressing Modes Select Bit (AMODE) 5-4 ADDRH register 7-24 ADDRL register 7-24 ADDU ACC, loc16 6-39 ADDUL P, loc32 6-40
A
ABORTI 6-18 ABORTI instruction 7-15 ABS ACC 6-19 ABSTC ACC 6-20 access to CPU registers during emulation 7-16 access to memory during emulation 7-16 accesses polite 7-16 rude 7-16 Accumulator B-4 accumulator 2-6 AH (high word) 2-6 AH.LSB 2-7 AH.MSB 2-7 AL (low word) 2-6 AL.LSB 2-7 AL.MSB 2-7 portions that are individually accessible 2-7 ADD ACC, #16bit<#0..15 6-22 ADD ACC, loc16< T 6-24 ADD ACC, loc16<#0 6-25 ADD AX, loc16 6-27 ADD loc16, AX 6-28 ADD loc16, #16bitSigned 6-29 ADDB ACC, #8bit 6-30
Index-1
Index
ADDUL ACC loc32 6-41 ADRK #8bit 6-42 AH (high word of accumulator) 2-6 AL (low word of accumulator) 2-6 align stack pointer 6-52 AL.LSB (part of accumulator) 2-7 AL.MSB (part of accumulator) 2-7 AMODE 5-4, B-9, E-4 AMODE bit 1-2 analysis resources breakpoints 7-19 clearing resources 7-30 counters 7-20 data logging 7-23 sharing resources 7-30 watchpoints 7-19 AND ACC, #16bit < #0..15 6-43 AND ACC, loc16 6-43 6-44 AND AX, loc16, #16bit 6-45 AND IER, #16bit 6-46 AND IFR, #16bit 6-47 AND loc16, AX 6-48 AND AX, loc16 6-49 AND IER and OR IER instructions note about RTOSINT 3-9 AND loc16, #16bitSigned 6-50 ANDB AX, #8bit 6-51 architectural overview 1-1 architecture differences between the C27x and the C28x E-1 architecture differences between the C2xLP and the C28x B-1 arithmetic logic unit (ALU) 1-5 arithmetic shift right 6-53 ARP B-9 ARx registers C-14 ASP 6-52 ASR AX, #1016 6-53 ASR AX, T 6-54 ASR64 ACC:P, #1..16 6-55 ASR64 ACC:P ,T 6-56 ASRL ACC, T 6-57 atomic arithmetic logic unit (ALU) 2-2 Auxiliary registers B-4 Index-2
auxiliary registers AR0AR5, XAR6, XAR7, 2-12 pointer 2-34
B
B 16bitOffset, COND B0 Memory Map background code BANZ D-4 6-60 B-14 7-6 6-58
BANZ 16bitOffset, ARn 6-59 BAR 16bitOffset, ARn, ARm, EQ barrel shifter 1-5 7-20 6-61 benchmark counter
BF 16bitOffset, COND
bits auxiliary register pointer (ARP) 2-34 carry (C) 2-25 debug enable mask (DBGM) 2-37 debug interrupt enable register (DBGIER) 3-10 emulation access enable (EALLOW) 2-35 IDLE status (IDLESTAT) 2-35 interrupt enable register (IER) 3-9 interrupt flag register (IFR) 3-7 interrupt global mask (INTM) 2-37 loop instruction status (LOOP) 2-35 negative flag (N) 2-24 overflow counter (OVC) 2-16 overflow flag (V) 2-21 overflow mode (OVM) 2-32 PAGE0 addressing mode configuration 2-36 product shift mode (PM) 2-19 sign-extension mode 2-32 stack pointer alignment (SPA) 2-36 test/control flag (TC) 2-30 vector map (VMAP) 2-36 zero flag (Z) 2-25 block diagram of the CPU, figure branch 6-58 instructions introduced break event break events 7-6 7-7 7-11 2-39 2-3
breakpoints 7-19 caution about time-critical ISRs
Building a C27x Object File From C27x Source, figure E-8
Index
buses data-/program-write data 1-9 data-read address 1-9 data-read data 1-9 data-write address 1-9 program address 1-9 program-read data 1-9 special operations 1-10 summary table 1-10
caution: breakpoints within time-critical interrupt service routines 7-11 central processing unit (CPU) 1-4, 2-2 reset 3-23 in real-time mode debug-halt state circular addressing modes clear the AMODE bit 6-67 6-63 clear the OBJMODE bit CLRC AMODE 6-67 CLRC M0M1MAP 6-68 CLRC OBJMODE CLRC OVC 6-70 CLRC XF 6-71 CLRC mode 6-72 CMP AX, loc16 6-74 6-75 CMP loc16, #16bitSigned CMP64 ACC:P 6-77 CMPB AX, #8bit 6-79 CMPL ACC, loc32 CMPL ACC, P < PM 6-80 6-81 6-69 5-21
7-9
C
C bit 2-25 C27MAP 6-62 C27OBJ 6-63 C27x Compatible Mapping of ABlocks M0 and M1 figure E-7 C27x object mode E-8 C28ADDR 6-64 C28MAP 6-65 C28OBJ 6-66 C28x and C2xLP Flags table D-2 C28x features B-2 C28x Product Mode Shifter table B-8 C28x Status Register ST0 B-7 C28x Status Register ST1 B-7 C2xLP C-1 C2xLP and C28x architectural differences B-1 C2xLP and C28x Differences in Instructions and Registers, table C-13 C2xLP and C28x Differences in Interrupts, table C-10 C2xLp and C28x Differences in Memory Maps, table C-12 C2xLP and C28x Differences in Status Registers table C-11 C2xLP Instructions and C28x Equivalent Instructions, table D-3 C2xLP Product Mode Shifter B-8 C2xLP Status Register ST0 B-7 C2xLP Status Register ST1 B-7 calls 2-39 Carry bit (C) B-10 carry bit (C) 2-25
CMPR 0 6-82 code clear IFR C-8 conversion from C2xLP C-8 IER/IFR C-7 interrupt C-8 migration reference tables C-10 code examples C-7 Code for a Full Context Save/Restore for C28x vs C27x, figure E-6 compare 6-74 compatibility 1-2 compiler 5-7 core 1-2 components 1-4 diagram 1-4 count sign bits counters 7-20 6-83
CPU 1-4, 2-2 See also central processing unit reset 3-23 in real-time mode debug-halt state CPU registers 2-4 CSB ACC 6-83
7-9
Index-3
Index
D
data buses 1-9 3-6, 7-27 data log interrupt (DLOGINT) vector 3-5
data logging 1-5, 7-23 accessing emulation registers 7-26 creating a transfer buffer 7-23 examples 7-28 interrupt (DLOGINT) 3-6, 7-27 interrupt vector 3-5 with end address 7-29 with word counter 7-28 data logging end-address control register Data memory B-14 6-89 B-5 2-10 1-8 1-9 1-9 1-9 data move contents Data Page Pointer 7-26
data page pointer (DP)
data space, address map
data-/program-write data bus (DWDB) data-read address bus (DRAB) data-read data bus (DRDB) DBGIER A-2 B-9 1-9 data-write address bus (DWAB) DBGM E-4 debug enable mask bit DBGSTAT register
7-15, G-6
debug enable mask bit (DBGM) 2-37 event 7-6 execution control modes 7-7 halt state 7-6 interface 7-3 sharing resources 7-30 terminology 7-6 debug enable mask bit (DBGM) 2-37 role in accesses during emulation 7-16 set during interrupt handling 3-15, 3-20 debug interrupt enable register A-2 3-6, 3-8, debug interrupt enable register (DBGIER) 3-10, 7-9 quick reference figure A-9 Debug interruptenable register B-4 debug status register (DBGSTAT) Index-4 7-15, G-6
debug-and-test direct memory access (DT-DMA) 1-5 mechanism 7-16 debug-halt state 7-7, 7-9 DEC loc16 6-84 decoupled pipeline segments 4-4 decrement by 1 6-84 development interface 7-2 diagnostic features for emulation 7-31 diagrams CPU 2-3 multiplication 2-42, 2-43 pipeline activity 4-8 pipeline conflict 4-13, 4-14 relationship between pipeline and address counters 4-6 shift operations 2-45 T320C28x DSP core 1-4 DINT 6-85 Direct Addressing Mode 5-2, 5-8 direct addressing mode B-5 Direct Addressing Mode Mapping, figure B-6 direct addressing mode on the C2XLP B-5 direct memory access mechanism for emulation 7-16 disable write access to protected registers 6-91 discontinuity delay 4-11 DMA control register 7-25 DMA ID register 7-25 DMA registers (data logging) 7-25 DMAC ACC:P, loc32, *XAR7 6-86 DMOV loc16 6-89 DP 2-10 DTDMA 1-5 DT-DMA mechanism 7-16 DT-DMA request process, figure 7-17 dual multiply and accumulate 6-86
E
EALLOW 6-90, B-9 EALLOW bit 2-35 EALLOW instruction, use in data logging 7-23, 7-26 EDIS 6-91 EDIS instruction, use in data logging 7-24, 7-27
Index
EINT 6-92 EMU0/1 signals 7-4 emulation data logging 7-23 disabled 7-5 enabled 7-5 features 1-5, 7-2 logic 1-4, 1-5, 7-15 Emulation access enable bit B-9 emulation access enable bit (EALLOW) 2-35 emulation signals 1-6 enable maskable interrupts 6-92 enable write access to protected space 6-90 end address register (data logging) 7-26 ESTOP0 6-93 ESTOP1 6-94 event counter 7-20 events break 7-6 debug 7-6 examples code C-7 data logging with end address 7-29 data logging with word counter 7-28 execution control modes real-time mode 7-9 stop mode 7-7
full context save C-8 Full Context Save/Restore, figure E-5 Full Context Save/Restore Comparison, table
C-9
G
global space B-14 Glossary G-1 GREG register D-14
H
hardware reset 3-23 hardware reset interrupt 3-17 header, dimensions 14-pin 7-3 high-impedance mode 7-5
I
I/O space B-14 IACK #16bit 6-97 IC (instruction counter) 4-5 IDLE 6-98 IDLE status bit (IDLESTAT) 2-35 IDLESTAT B-9 IDLESTAT bit 2-35 IEEE 1149.1 (JTAG) signals 7-3 IER A-2 IFR A-2 illegal-instruction trap 3-17, 3-22 IMACL P, loc32, *XAR7 6-100 improvements over the C2xLP CPU B-2 IMPYAL P, XT, loc32 6-103 IMPYL ACC, XT, loc32 6-105 IMPYL P, XT, loc32 6-106 IMPYSL P, XT, loc32 6-107 IMPYXUL P, XT, loc32 6-109 IN loc16, *(PA) 6-111 INC loc16 6-113 increment by 1 6-113 Indirect Addressing Mode 5-2, 5-10 individually accessible portions of the accumulator 2-7 instruction counter (IC) 4-5 Instruction Syntax Change, table E-12
F
fast function call 6-95 FC (fetch counter) 4-5 fetch counter (FC) 4-5 FFC XAR7, 22bit 6-95 find the maximum 6-149 find the minimum 6-153 flags, interrupt flag register (IFR) 3-7 FLIP AX 6-96 flip order of bits in AX register 6-96 flow chart of recommended migration steps, figure C-4 flow charts handling DT-DMA request 7-17 interrupt initiated by the TRAP instruction 3-18 interrupt operation, maskable interrupts 3-12 foreground code 7-6
Index-5
Index
instruction-fetch mechanism
4-4 4-10
instruction-not-available condition
instructions ABORTI (abort interrupt) 7-15 ABS ACC (Absolute Value of Accumulator) 6-19 ADD (add constant) 6-29 ADD AX (Add value to AX) 6-27 ADDACC (Add value to accumulator) 6-22 ADDB XARn, #7bit 6-33 ADDUACC (add unsigned value to accumulator) 6-39 ADRK (add to current register) 6-42 ASP (align stack pointer) 6-52 ASRAX (arithmetic shift right) 6-53 B (branch) 6-58 C27MAP (set the M0M1MAP bit) 6-62 C27OBJ (clear the OBJMODE bit) 6-63 CLRCAMODE (clear the AMODE bit) 6-67 CMP AX (compare) 6-74 conditional 2-39 CSBACC (count sign bits) 6-83 DEC (decrement) 6-84 DMA ACC (dual multiply and accumulate) 6-86 DMOV (data move contents) 6-89 EALLOW (enable write access to protected space 6-90 EDIS (disable write access to protected registers) 6-91 EINT (enable maskable interrupts) 6-92 FFC XAR7,22bit (fast function call) 6-95 FLIP AX (flip order of bits in AX register) 6-96 IACK, #16bit (interrupt acknowledge 6-97 INCloc16 (increment by 1) 6-113 INTR (software interrupt) 3-17 LB *XAR7 (long indirect branch) 6-119 LC *XAR7 (long indirect call) 6-121 LCR #22bit (long call using RPC) 6-123 LOOPNZ loc16, #16bit (loop while not zero) 6-125 LPADDR (set the AMODE bit) 6-129 LRET (long return) 6-130 LSLACC, #1..16 (logical shift left) 6-133 LSR AX, #1..16 (logical shift right) 6-140 MAC (multiply and accumulate, preload T) 4-16 MAX AX, loc16 (find the maximum) 6-149 MIN AX, loc16 (find the minimum) 6-153 MOV AR6/7, loc16 (load auxiliary register) 6-160 MOV AX, loc16 (load AX) 6-161 Index-6
instructions (continued) MOV DP, #10bit (load data page pointer) 6-162 MOV IER, loc16 (load the interrupt enable register) 6-163 MOV loc16, #16bit (save 16-bit constant) 6-164 MOV loc16, OVC (store the overflow counter) 6-173 MOV OVC, loc16 (load the overflow counter) 6-176 MOV*(0:16bit), loc16 (move value) 6-156 OR ACC, loc16 (bitwise OR) 6-257 OUT *(PA), loc16 (output data to port) 6-265 POP ACC (pop top of stack to accumulator) 6-267 PREAD (read from program memory) 4-16 PREAD loc16, *XAR7 (read from program memory) 6-282 PUSH ACC (push accumulator onto stack) 6-284 PWRITE (write to program memory) 4-16 PWRITE *XAR7, loc16 (write to program memory) 6-299 ROL ACC (rotate accumulator left) 6-310 ROR ACC (rotate accumulator right) 6-311 SAT ACC (saturate accumulator) 6-313 SUBR loc16, AX 6-354 TBIT 6-359 TCLR 6-361 TRAP (software trap) 3-17 6-363 TSET 6-365 UOUT 6-366 TEST 6-362 XB 6-368 XBANZ 6-372 XCALL 6-374 XMACDP 6-380 XMACP 6-378 XOR 6-382 XORB 6-387 XPREAD 6-388 XPWRITE 6-390 XRET 6-391 XRETC 6-392 ZALR 6-394 ZAP 6-395 ZAPA 6-396 XB 6-370 interface, memory interrupt, signals 1-9 1-6 6-97
interrupt acknowledge
Index
interrupt-control registers (IFR, IER, DBIER) interrupt enable C-10 B-4 C-10 Interrupt enable register interrupt enable register
2-14
interrupt enable register (IER) 3-6, 3-8, 7-9 quick reference figure A-8 Interrupt flag register interrupt flag register B-4 A-2, C-10
interrupt flag register (IFR) 3-7 quick reference figure A-7 Interrupt global mask bit (INTM) interrupt global mask bit (INTM) interrupt handling in stop mode interrupt instructions AND IER 3-8 AND IFR 3-7 INTR 3-8, 3-17 OR IER 3-8 OR IFR 3-7 POP DBGIER 3-10 PUSH DBGIER 3-10 TRAP 3-17 interrupt service routine (ISR) 3-4 caution about breakpoints 7-11 interrupt vectors 1-7 interrupts 2-39, 3-1 aborting 7-15 control registers (IFR, IER, DBGIER) 2-14 data log interrupt (DLOGINT) 3-6, 7-27 effect on instructions in pipeline 4-4 general purpose 3-6 handling information by emulation mode and state 7-13 INT1INT14, 3-6 maskable 3-6 definition 3-2 flow chart of operation 3-12 NMI 3-21 nonmaskable 3-17 definition 3-2 operation overview 3-2 real-time mode 7-9 standard 3-11 stop mode 7-7 overview 3-2 B-10 2-37, 3-6, 7-9 7-9 7-7
interrupts (continued) real-time operating system interrupt (RTOSINT) 3-6 special cases, clearing IFR flag bit after TRAP instruction 3-7, 3-8 time-critical 7-6 serviced in real-time mode 7-9 vectors 3-4 INTM B-11 INTR INTx 6-114 INTR instruction 3-17, C-10 IRET 6-116 IRET instruction 7-15, E-5
interrupt handling in real-time mode
J
JTAG, signals 7-3 JTAG header to interface a target to the scan controller, figure 7-3 JTAG port 7-1
L
LACL dma C-15 LB *XAR7 6-119 LB 22bit 6-120 LC *XAR7 6-121 LC 22bit 6-122 LCR #22bit 6-123 LCR *XARn 6-124 load auxiliary register 6-160 load AX 6-161 load data page pointer 6-162 load the interrupt enable register 6-163 load the overflow counter 6-176 loc16 5-2 loc32 5-2 logical shift left 6-133 logical shift right 6-140 long call using RPC 6-123 long indirect branch 6-119 long indirect call 6-121 long return 6-130 LOOP B-9 LOOP bit 2-35 Loop instruction status bit B-9
Index-7
Index
loop instruction status bit (LOOP) loop while not zero 6-125 LOOPNZ loc16, #16bit 6-125 LOOPZ loc16, #16bit 6-127 LPADDR 6-129 LRET 6-130 LRETE 6-131 LRETER 6-132 LSL ACC, #1..16 6-133 LSL ACC, T 6-134 LSL AX, #1016 6-135 LSL AX, T 6-136 LSL64 ACC:P, #1..16 6-137 LSL64 ACC:P, T 6-138 LSLL ACC, T 6-139 LSR AX, #1016 6-140 LSR AX, T 6-141 LSR64 ACC:P, #1..16 6-142 LSR64 ACC:P, T 6-143 LSRL ACC, T 6-144
2-35
M
M0 M1 map bit B-9 M0M1MAP B-9, E-4 MAC P, loc16, 0:pma 6-145 MAC P, loc16, *XAR7 6-147 Mapping of memory blocks B0 and B1 on C27 maskable interrupts 3-6 definition 3-2 flow chart of operation 3-12 MAX AX, loc16 6-149 MAXCUL P, loc32 6-150 MAXL ACC, loc32 6-152 memory 1-9 address map 1-8 interface 1-9 reserved addresses 1-8 memory map B-12, B-13, E-2 Memory space B-12 memory wrappers 1-11 migration 1-2 migration flow C-3 migration guidelines C-1 Index-8
E-7
MIN AX, loc16 6-153 MINCUL P, loc32 6-154 MINL ACC, loc32 6-155 mixing of C2xLP code and C28x code segments C-6 modes high-impedance 7-5 nonpreemptive 7-16 normal with emulation disabled 7-5 normal with emulation enabled 7-5 preemptive 7-16 real-time 7-7, 7-9 slave 7-5 stop 7-7 MOV *(0:16bit), loc16 6-156 MOV AX, loc16 6-161 MOV ACC, #16bit<#0..15 6-157 MOV ACC, loc16 < T 6-158 MOV ACC, loc16<#0..16 6-159 MOV AR6, loc16 6-160 MOV DP, #10bit 6-162 MOV IER, loc16 6-163 MOV loc16, #0 6-166 MOV loc16, #16bit 6-164 MOV loc16, *(0:16bit) 6-165 MOV loc16, AX 6-169 MOV loc16, AX COND 6-170 MOV loc16, IER 6-172 MOV loc16, OVC 6-173 MOV loc16, P 6-174 MOV OVC, loc16 6-176 MOV PH, loc16 6-177 MOV PL, loc16 6-178 MOV PM, AX 6-179 MOV T, loc16 6-180 MOV TL, #0 6-181 MOV loc16, ARn 6-168 MOV XARn, PC 6-182 MOV loc16, T 6-175 MOVA T, loc16 6-183 MOVAD T, loc16 6-185 MOVB ACC, #8bit 6-187 MOVB AR6/7, #8bit 6-188 MOVB AX.LSB, loc16 6-190 MOVB AX.MSB, loc16 6-192
Index
MOVB AX, #8bit 6-189 MOVB loc16, AX.LSB 6-196 MOVB loc16, AX.MSB 6-198 MOVB loc16, #8bit, COND 6-194 MOVB XARn, #8bit 6-200 MOVDL XT, loc16 6-201 move value 6-156 MOVH loc16, P 6-203 MOVH loc16, ACC, < #1..8 6-167, 6-202 MOVL ACC, loc32 6-204 MOVL ACC, P < PM 6-205 MOVL loc32, ACC 6-206 MOVL loc32, XAR0 6-210 MOVL loc32, ACC, COND 6-207 MOVL loc32, P 6-209 MOVL loc32, XT 6-211 MOVL P, ACC 6-212 MOVL P, loc32 6-213 MOVL XAR0, loc32 6-214 MOVL XARn, #22bit 6-215 MOVL XT, loc32 6-216 MOVP T, loc16 6-217 MOVS, T, loc16 6-218 MOVU ACC, loc16 6-220 MOVU loc16, OVC 6-221 MOVU OVC, loc16 6-222 MOVW DP, #16bit 6-223 MOVX TL, loc16 6-224 MOVZ AR005, loc16 6-225 MOVZ DP, #10bit 6-226 MPY ACC, loc16, #16bit 6-227 MPY ACC, T,loc16 6-228 MPY P, loc16, #16bit 6-229 MPY P, T,loc16 6-230 MPYA P, loc16, #16bit 6-231 MPYA P, T,loc16 6-233 MPYB ACC, T, #8bit 6-235 MPYB P, T, #8bit 6-236 MPYS P, T, loc16 6-237 MPYU ACC, T, loc16 6-240 MPYU P, T, loc16 6-239 MPYXU ACC, T, loc16 6-241 MPYXU P, T, loc16 6-242
Multiplicand register B-4 multiplicand register (T) 2-8 multiplier, operation 2-41
N
N bit 2-24 NASP 6-243 NEG ACC 6-244 NEG AX 6-245 NEG64 ACC:P 6-246 Negative flag B-8 negative flag (N) 2-24 NEGTC ACC 6-248 NMI Instruction C-10 NMI interrupt 3-21 NMI pin 3-21 nonmaskable interrupts 3-17 definition 3-2 nonpreemptive mode 7-16 NOP {*ind}{,ARPn} 6-250 NORM ACC, *ind 6-251 NORM ACC, XARn++ 6-253 normal mode 7-5 NOT ACC 6-255 NOT AX 6-256
O
OBJMODE B-9, E-4, E-9 OBJMODE bit 1-2 operating modes, selecting by using TRST EMU0, and EMU1, 7-5 operations multiply 2-41 shift 2-44 special bus 1-10 stack 2-12 OR ACC, loc16 6-257 OR ACC, #16bit < #0..15 6-258 OR AX, loc16 6-259 OR loc16, AX 6-263 OR IER, #16bit 6-260 OR IFR, #16bit 6-261 OR loc16, #16bit 6-262
Index-9
Index
ORB AX, #8bit 6-264 OUT *(PA), loc16 6-265 output data to port 6-265 OVC, overflow counter B-9 OVC (overflow counter) 2-16 overflow counter (OVC) 2-16 Overflow flag B-8 overflow flag (V) 2-21 Overflow mode (OVM) B-10 overflow mode bit (OVM) 2-32 OVM B-11 OVM bit 2-32
P
P register 2-9 PAGE0 addressing mode configuration bit PAGE0 bit 2-36 PC (program counter) 2-14, 4-5 phases of pipeline 4-2 pipeline 2-40 decoupled segments 4-4 freezes in activity 4-10 instruction-fetch mechanism 4-4 operations not protected by 4-16 phases 4-2 protection 4-12 visualizing activity 4-7 wait states 4-10 pipeline phases 4-2 PM bits 2-19 POP ACC 6-267 POP AR1:AR0 6-268 POP AR1H:AR0H 6-269 POP AR3:AR2 6-268 POP AR5:AR4 6-268 POP DBGIER 6-270 POP DP 6-271 POP DP:ST1 6-272 POP IFR 6-273 POP loc16 6-274 POP P 6-275 POP RPC 6-276 POP ST0 6-277 POP ST1 6-278 Index-10 B-9
POP T:ST0 6-279 pop top of stack to accumulator 6-267 POP XAR0 6-280 POP XAR1 6-280 POP XAR2 6-280 POP XAR3 6-280 POP XAR4 6-280 POP XAR5 6-280 POP XAR6 6-280 POP XAR7 6-280 POP XT 6-281 PREAD loc16, *XAR7 6-282 preemptive mode 7-16 process for handling a DT-DMA request, figure 7-17 Product Mode Shifter B-8 Product register B-4 product register (P) 2-9 Product shift mode B-8 product shift mode bits (PM) 2-19 program address bus (PAB) 1-9, 4-4 Program counter B-4 program counter C-14 program counter (PC) 2-14, 4-5 program flow 2-39 Program space B-12 program space, address map 1-8 program-space read and write 1-10 program-address counters 4-5 program-read data bus (PRDB) 1-9 PUSH ACC 6-284 push accumulator onto stack 6-284 PUSH AR1:AR0 6-285 PUSH AR1H:AR0H 6-286 PUSH AR3:AR2 6-285 PUSH AR5:AR4 6-285 PUSH DBGIER 6-287 PUSH DP 6-288 PUSH DP:ST1 6-289 PUSH IFR 6-290 PUSH loc16 6-291 PUSH P 6-292 PUSH RPC 6-293 PUSH ST0 6-294
Index
PUSH ST1 6-295 PUSH T:ST0 6-296 PUSH XAR0 6-297 PUSH XAR1 6-297 PUSH XAR2 6-297 PUSH XAR3 6-297 PUSH XAR4 6-297 PUSH XAR5 6-297 PUSH XAR6 6-297 PUSH XAR7 6-297 PUSH XT 6-298 PWRITE *XAR7, loc16
6-299
Q
QMACL P, loc32, *XAR7 6-300 QMACL P, loc32, *XAR7++, 6-300 QMPYAL P, XT, loc32 6-302 QMPYL P, XT, loc32 6-304 QMPYL ACC, XT, loc32 6-305 QMPYSL P, XT, loc32 6-306 QMPYUL P, XT, loc32 6-308 QMPYXUL P, XT, loc32 6-309
R
read from program memory 6-282 reads and writes, unprotected 4-16 real-time mode 7-7, 7-9 figure of execution states 7-10 real-time mode versus stop mode, figure 7-12 real-time operating system interrupt (RTOSINT) 3-6, 7-14 Register Addressing Mode 5-2 register addressing modes 5-25 register changes B-4 register modifications B-3, E-2 register quick reference A-1 figures A-3 registers accumulator 2-6 ADDRH 7-24 ADDRL 7-24 after reset 3-23 auxiliary registers (XAR0 XAR7) 2-12
registers (continued) conflicts, protection against 4-13 CPU registers (summary) 2-4 data page pointer (DP) 2-10 debug interrupt enable register (DBGIER) 3-8 DMA control register 7-25 end address register (data logging) 7-26 interrupt-control registers (IFR, IER, DBGIER) 2-14 interrupt enable register (IER) 3-8 interrupt flag register (IFR) 3-7 multiplicand (T) 2-8 product register (P) 2-9 program counter (PC) 2-14 quick reference A-1 quick reference figures A-3 return program counter (RPC) 2-14 stack pointer (SP) 2-11 start address register (data logging) 7-25 status register ST0, 2-14, 2-16 status register ST1, 2-14, 2-34 T register 2-8 registers after reset 3-23 repeat counter (RPTC) 2-39 repeat instructions C-13 repeatable instructions D-9, E-13 reserved addresses 1-8 Reserved memory B-14 reset 1-3 reset and interrupt signals 1-6 reset conditions B-10 Reset Conditions of Internal Registers, table B-10 reset input signal (RS) 3-23 reset of CPU 3-23 Reset Values of the Status and Control Registers, table A-2 Return Program Counter 2-5 Return program counter B-4 return program counter (RPC) 2-14 returns 2-39 ROL ACC 6-310 ROR ACC 6-311 rotate accumulator left 6-310 RPC (return program counter) 2-14 RPT #8bit 6-312 RPT loc16 6-312 RPTC (repeat counter) 2-39
Index-11
Index
run state
7-7, 7-10
S
SARAM mapping C-13 SAT ACC 6-313 SAT64 ACC:P 6-314 save 16-bit constant 6-164 SB 8bitOffset, COND 6-316 SBBU ACC, loc16 6-317 SBF 8bitOffset, EQ 6-318 SBF 8bitOffset, NEQ 6-318 SBF 8bitOffset, NTC 6-318 SBF 8bitOffset, TC 6-318 selecting device operating modes 7-5 set the AMODE bit 6-129 set the M0M1MAP bit 6-62 SETC C 6-320 SETC DBGM 6-320 SETC INTM 6-320 SETC OVM 6-320 SETC PAGE0 6-320 SETC SXM 6-320 SETC TC 6-320 SETC VMAP 6-320 SETC M0M1MAP 6-322 SETC mode 6-320 SETC OBJMODE 6-323 SETC XF 6-324 SFR ACC, #1..16 6-325 SFR ACC, T 6-326 shift operations 2-44 shifter 1-5 shifting values in the accumulator 2-8 Sign extension mode (SXM) B-10 signal descriptions 14-pin header 7-4 signals 1-6 description 14-pin header 7-4 EMU0 7-5 EMU1 7-5 PD (VCC) 7-3 TCK 7-3 TCK_RET 7-3 TDI 7-3 TDO 7-3 Index-12
signals (continued) TMS 7-3 TRST 7-3, 7-5 sign-extension mode bit (SXM) 2-32 single-instruction state 7-7 slave mode 7-5 software breakpoints 7-7 software interrupts 3-17 SPA bit 2-36 special bus operations 1-11 SPM +1 6-327 SPM +4 6-327 SPM 1 6-327 SPM 2 6-327 SPM 3 6-327 SPM 4 6-327 SPM 5 6-327 SPM 6 6-327 SPM 0 6-327 SQRA loc16 6-329 SQRS loc16 6-331 ST0 A-2 ST0 Register Bits, table E-3 ST1 A-2 ST1 Register Bits, table E-4 stack 2-11 Stack Addressing Mode 5-2, 5-9 Stack Pointer B-4 stack pointer (SP) 2-11 Stack pointer alignment bit B-9 stack pointer alignment bit (SPA) 2-36 Stack space B-14 start address register (data logging) 7-25 status bits ARP 2-34 C 2-25 DBGM 2-37 EALLOW 2-35 IDLESTAT 2-35 INTM 2-37 LOOP 2-35 N 2-24 OVC 2-16 OVM 2-32 PAGE0, 2-36 PM 2-19
Index
status bits (continued) SPA 2-36 SXM 2-32 TC 2-30 V 2-21 VMAP 2-36 Z 2-25 status register A-2 Status Register Bits B-11 status register changes B-7 Status Register Comparison Between C2xLP and C28x, figure B-7 Status Registers B-5 status registers ST0, 2-14, 2-16 quick reference figure A-4 ST1, 2-14, 2-34 quick reference figure A-5 stop mode 7-7 figure of execution states 7-8 stop mode versus real-time mode, figure 7-12 store the overflow counter 6-173 SUB loc16, AX 6-339 SUB ACC, #16bit < #0..15 6-337 SUB ACC, loc16 < #0 6-333 SUB ACC, loc16 < T 6-335 SUB AX, loc16 6-338 SUBB ACC, #8bit 6-340 SUBB XARn, #7bit 6-342 SUBB SP, #7bit 6-341 SUBBL ACC, loc32 6-343 SUBCU ACC, loc16 6-345 SUBCU instruction E-14 SUBCUL ACC, loc32 6-347 SUBL ACC, loc32 6-350 SUBL ACC, P < PM 6-351 SUBL loc32, ACC 6-353 SUBR loc16, AX 6-354 SUBRL loc32, ACC 6-355 SUBU ACC, loc16 6-356 SUBUL ACC, loc32 6-357 SUBUL P, loc32 6-358 suspend program execution 7-7 SXM bit 2-32
syntax change increment/decrement C-15 repeat instructions C-15 shift C-15
T
T register 2-8 T320C28x core 1-2 TBIT loc16, #16bit 6-359 TBIT loc16, T 6-360 TC bit 2-30 TCK signal 7-4 TCLR loc16, #bit 6-361 TDI signal 7-4 terminology, debug 7-6 test, sharing resources 7-30 TEST ACC 6-362 test clock return signal (TCK_RET) 7-3 Test/control flag (TC) B-10 test/control flag bit (TC) 2-30 testing and debugging, signals 1-6 time-critical interrupts definition 7-6 serviced in real-time mode 7-9 TMS signal 7-4 TMS320C20x C-1 TMS320C24x C-1 TMS320C24xx C-1 TRAP #VectorNumber 6-363 TRAP instruction 3-18, C-10 TRST signal 7-4, 7-5 TSET loc16, #16bit 6-365 types of signals 1-6
U
unprotected program-space reads and writes UOUT *(PA),loc16 6-366 4-16
V
V bit 2-21 Vector map bit B-9 vector map bit (VMAP) 2-36
Index-13
Index
Vectors B-12 VMAP E-4
W
wait states, effects on pipeline 4-10 wait-in-reset mode 7-5 watchpoints 7-19 write to program memory 6-299
X
XAR6 register 2-12 XARn registers E-9 XB *AL 6-368 XB pma, COND 6-370 XB pma, *, ARPn 6-369 XBANZ pma, * 6-372 XBANZ pma, *, ARPn 6-372 XBANZ pma, *++ 6-372 XBANZ pma, *++, ARPn 6-372 XBANZ pma, * 6-372 XBANZ pma, *, ARPn 6-372 XBANZ pma, *0++ 6-372 XBANZ pma, *0++, ARPn 6-372 XBANZ pma, *0 6-372
XBANZ pma, *0, ARPn 6-372 XCALL *AL 6-374 XCALL pma, *, ARPn 6-375 XCALL pma, COND 6-376 XF E-4 XF pin status bit B-9 XMAC P, loc16, *(pma) 6-378 XMACD P, loc16, *(pma) 6-380 XOR AX, loc16 6-384 XOR ACC, #16bit < #0..15 6-383 XOR ACC, loc16 6-382 XOR loc16, AX 6-385 XOR loc16, #16bit 6-386 XORB AX, #8bit 6-387 XPREAD loc16, *(pma) 6-388 XPREAD loc16, *AL 6-389 XPWRITE *AL, loc16 6-390 XRET 6-391 XRETC COND 6-392
Z
ZAP OVC 6-395 ZAPA 6-396 Zero flag B-8 zero flag bit (Z) 2-25
Index-14
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TMS320C28x CPU and Instruction Set Reference Guide

Literature Number: SPRU430E August 2001 Revised January 2009

Read This First

Read This First

About This Manual

Appendix C Appendix D Appendix E Appendix G

About This Manual / Notational Conventions

ple line of program code:

Read This First

Bits n through m of register

Notational Conventions / Related Documentation From Texas Instruments

Related Documentation From Texas Instruments

Read This First

2.3 2.4 2.5

2-39 2-40 2-41 2-41 2-42 2-44

5.8 5.9 5.10 5.11 6

7.5 7.6 7.7

7-23 7-23 7-26 7-27 7-28 7-30 7-31

Introduction to the CPU

1.1 Introduction to the CPU

Compatibility With Other TMS320 CPUs

Table 11. Compatibility Modes

The C28x is in C27x-compatible mode at reset.

Introduction to the CPU

- C2xLP Source-Compatible Mode: C2xLP source-compatible mode al-

Switching to C28x Mode From Reset

Components of the CPU

1.2 Components of the CPU

lities of the DSP and for testing device operation

Figure 11. High-Level Conceptual Diagram of the CPU

Central Processing Unit (CPU)

mapped to data space. These registers function as system-control

Components of the CPU

metic and Boolean logic operations.

data to the left by up to 16 bits and to the right by up to 16 bits.

of memory contents between the C28x and a debug host.

break in program execution:

Components of the CPU

set and interrupts, and for monitoring the status of interrupts.

1.3 Memory Map

CPU Interrupt Vectors

Figure 12. TMS320C28x High-Level Memory Map

7FF Reserved Reserved

800 9FF 1000

Memory or Peripherals 3F 0000

Memory or Peripherals A000

High 64K C2xLP Compatible Program Space

1.4 Memory Interface

Address and Data Buses

Table 12 summarizes how these buses are used during accesses.

Special Bus Operations

Table 13. Special Bus Operations

Alignment of 32-Bit Accesses to Even Addresses

Central Processing Unit

2.1 CPU Architecture

that have been fetched from program memory.

Figure 21. Conceptual Block Diagram of the CPU

Data-write address bus, DWAB(0:31)

Central Processing Unit